CN101786594A - 电子元件封装体及其制作方法 - Google Patents

电子元件封装体及其制作方法 Download PDF

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Publication number
CN101786594A
CN101786594A CN201010001420A CN201010001420A CN101786594A CN 101786594 A CN101786594 A CN 101786594A CN 201010001420 A CN201010001420 A CN 201010001420A CN 201010001420 A CN201010001420 A CN 201010001420A CN 101786594 A CN101786594 A CN 101786594A
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CN
China
Prior art keywords
packaging body
electronic element
wafer
element packaging
opening
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Pending
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CN201010001420A
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English (en)
Inventor
刘建宏
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XinTec Inc
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XinTec Inc
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Priority to CN201510202690.3A priority Critical patent/CN104803346B/zh
Publication of CN101786594A publication Critical patent/CN101786594A/zh
Pending legal-status Critical Current

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    • B81—MICROSTRUCTURAL TECHNOLOGY
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    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00325—Processes for packaging MEMS devices for reducing stress inside of the package structure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
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Abstract

本发明提供一种电子元件封装体及其制作方法，上述电子元件封装体，包括感测芯片，上述感测芯片的上表面包括感测薄膜；具有开口结构的盖板，覆盖上述感测芯片的上述上表面，上述盖板与上述感测芯片之间于对应上述感测薄膜位置上包括连通上述开口结构的间隙；间隔层，介于上述盖板与上述感测芯片之间且围绕着上述间隙，其中上述间隔层与上述感测薄膜水平方向之间包括应力缓冲区。

Description

电子元件封装体及其制作方法
技术领域
本发明涉及一种电子元件封装体(electronics package)，特别是涉及一种利用晶片级封装(Wafer Level Package，WLP)工艺制作的电子元件封装体及其制作方法。
背景技术
微机电结构MEMS(Micro Electro Mechanical Systems)是利用半导体工艺技术，整合电子及机械功能制作而成的微型装置，主要的产品类别大致可分为加速计、陀螺仪、压力传感器、光通讯元件、DLP(数字光源处理)、喷墨头，以及无线网路RF感测元件等，目前已逐渐应用在包括汽车胎压量测、光通讯网路、投影机、感测网路、数字麦克风、时脉振荡器，以及包括游戏机在内的各种产品之中。甚至在新一代存储器技术、生物芯片、显示技术、新兴能源等先进研究方面，它也扮演了一个重要的角色。例如压力传感器(pressure sensor)主要是在感知物体所处环境压力的变化，部分汽车应用如油压表等已相当成熟，新应用如胎压监控等未来需求亦十分具有成长潜力，因此，亟需一种可用于上述微机电结构的封装体及其制造方法。
发明内容
有鉴于此，本发明的实施例提供一种电子元件封装体的制作方法，包括提供晶片，其具有上表面和下表面，上述上表面上设有导电电极；于上述晶片的上述上表面覆盖盖板；于上述晶片的上述下表面覆盖保护层；于上述保护层上形成电性接触上述导电电极的导电凸块；于上述盖板上形成开口结构；其中形成上述开口结构的步骤，是于上述晶片的上述上表面覆盖上述盖板之前实施，或者于上述晶片的上述下表面覆盖上述保护层之后且于形成上述导电凸块之前实施。
本发明的另一实施例提供一种电子元件封装体，包括感测芯片，上述感测芯片的上表面包括感测薄膜；具有开口结构的盖板，覆盖上述感测芯片的上述上表面，上述盖板与上述感测芯片之间于对应上述感测薄膜位置上包括连通上述开口结构的间隙；间隔层，介于上述盖板与上述感测芯片之间且围绕着上述间隙，其中上述间隔层与上述感测薄膜水平方向之间包括应力缓冲区。
附图说明
图1A-图1I显示制作一种根据本发明实施例的电子元件封装体的示意图；及
图2A-图2E显示制作一种根据本发明另一实施例的电子元件封装体的示意图。
附图标记说明
1～承载基板；             3～晶片；
5～凹洞；                 7～导电电极；
9～感测薄膜；             10～背面；
11～间隔层；              13、53～盖板；
15；55～间隙；
17、19、21、25、31、35、65～开口；
20～上表面；              23～绝缘层；
27～导线层；              29～保护层；
30～下表面；              33～导电凸块；
40～应力缓冲区；          67～密封层；
SC～切割道；
500a、500b～电子元件封装体。
具体实施方式
以下以各实施例详细说明并伴随着附图说明的范例，做为本发明的参考依据。在附图或说明书描述中，相似或相同的部分皆使用相同的图号。且在附图中，实施例的形状或是厚度可扩大，并以简化或是方便标示。再者，附图中各元件的部分将以分别描述说明，值得注意的是，图中未绘示或描述的元件，为所属技术领域中普通技术人员所知的形式，另外，特定的实施例仅为揭示本发明使用的特定方式，其并非用以限定本发明。
本发明是以制作电子元件封装体，例如是压力传感器(pressure sensor)的实施例作为说明。然而，可以了解的是，在本发明的封装体实施例中，其可应用于各种包含有源(主动)元件或无源(被动)元件(active or passiveelements)、数字电路或类比电路(digital or analog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(opto electronic devices)、微机电系统(Micro Electro Mechanical System；MEMS)、微流体系统(microfluidic systems)、或利用热、光线及压力等物理量变化来测量的物理传感器(Physical Sensor)。特别是可选择使用晶片级封装(Wafer Level Package，WLP)工艺对影像感测元件(image sensors)、发光二极管、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件(surface acoustic wave devices)、压力传感器(process sensors)或喷墨头(ink printer heads)等半导体芯片进行封装。
其中上述晶片级封装工艺主要是指在晶片阶段完成封装步骤后，再予以切割成独立的封装体，然而，在特定实施例中，例如将已分离的半导体芯片重新分布在承载晶片上，再进行封装工艺，亦可称之为晶片级封装工艺。另外，上述晶片级封装工艺亦适用于通过堆叠(stack)方式安排具有集成电路的多片晶片，以形成多层集成电路(multi-layer integrated circuit devices)的电子元件封装体。
图1A-图1I显示根据本发明的实施例中，制作例如压力传感器封装体的电子元件封装体500a的示意图。如图1A所示，提供晶片(wafer)3，其具有上表面20和下表面30，其下表面30向内部形成有多个凹洞(cavity)5，且通过接合晶片3的下表面30的承载基板1所密封。承载基板1可例如为玻璃基板，其厚度可介于300μm至500μm之间，优选可为400μm。在本发明实施例中，上述晶片3的材料可以是硅，或者是其它具有良好散热能力或高传导热系数的基底，并通过例如是湿蚀刻(wet etching)的方式，蚀刻此晶片3，以形成上述凹洞5。上述晶片3的厚度可介于100μm至200μm之间，优选可为140μm。在本发明实施例中，可采用粘着胶如环氧树脂(epoxy)，用以接合晶片3与承载基板1，但非必须采用环氧树脂接合。在本发明实施例中，晶片3上可设有包括压力感测芯片等多个微机电装置，感测薄膜9形成于晶片3中并邻近于晶片3的上表面20，且覆盖上述微机电装置，感测薄膜9例如可为压电材料，可用以感应外界环境或流体的变化，在感测薄膜9的周围则包括导电电极或导电垫7。如图1A所示，导电电极7与感测薄膜9连接，用以传导来自感测薄膜9的感测信号。在本发明另一实施例中，感测薄膜9亦可形成于晶片3的上表面20上且与导电电极7相连接。而且硅晶片3与导电电极7之间通过形成绝缘层予以隔离，例如，由氧化硅、氮氧化硅或低介电常数材料层组成，在此未予显示。
如图1B所示，接着，在晶片3的上表面20上还可以形成封装层或盖板13。在实施例中，盖板13与导电电极7之间可设置间隔层(spacer)11或支撑架(dam)，以在盖板13与感测薄膜9之间形成间隙(cavity)15，而间隔层11则围绕着间隙15。盖板13可以是例如玻璃、石英(quartz)、蛋白石(opal)、塑胶等，在此以硅基板为例，主要是用以在后续形成开口以供流体进出，其厚度可介于500μm至800μm之间，优选可为700μm。间隔层11可例如为环氧树脂(epoxy)等粘着材料，一般而言，间隔层11位于导电电极7上。
接着，可选择进一步薄化承载基板1的步骤。例如从承载基板1的背面10予以薄化至预定厚度，例如由400um研磨至120um。该薄化工艺可以是蚀刻(etching)、铣削(milling)、磨削(grinding)或研磨(polishing)等方式。
其次，请参阅图1C，在预定切割道或导电电极7下方的位置形成贯穿承载基板1并深入至部分晶片3的开口17，在实施例中，可通过刻痕装置(notch equipment)实施刻痕步骤，如以大致为60度角的切刀切开承载基板1及晶片3而形成可视为通道凹口(channel notch)的开口17。
然后，如图1D所示，沿着开口17对晶片3进行蚀刻以形成底部较宽的开口19，例如对硅晶片3实施硅蚀刻步骤以去除掉开口侧壁及底部的晶片材料，其中导电电极7与晶片3之间的绝缘层在此步骤中可作为蚀刻停止层。
请参阅图1E，接着，在开口19的位置形成由宽渐窄的开口21，例如使用刻痕装置(notch equipment)实施刻痕步骤以切割承载基板1，其中此刻痕装置的切刀较宽或切角较大，例如选择大于60度角的切刀，优选者为选择75度至80度角的切刀，因此所形成的开口21其上部(位于承载基板1内部的部分)较宽且倾斜角大于底部(位于晶片3内部的部分)，有利于后续导线层的沉积，此外，开口21的上部(位于承载基板1内部的部分)及底部(位于晶片3内部的部分)的侧壁连接在一起，因此，可避免后续填充如图1F所示的绝缘层23时产生孔洞。
请参阅图1F，在上述开口21中形成绝缘层23。在实施例中，上述绝缘层23形成于承载基板1下表面10，并填充至开口21中。上述绝缘层23优选可以是环氧树脂(epoxy)、防焊材料(solder mask)或其它适合的绝缘物质，例如无机材料的氧化硅层、氮化硅层、氮氧化硅层、金属氧化物或其组合，或者是有机高分材料的聚酰亚胺树脂(polyimide；PI)、苯环丁烯(butylcyclobutene；BCB)、聚对二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(accrylates)等的绝缘沉积层，且可以是利用涂布方式，例如旋转涂布(spin coating)、喷涂(spray coating)或淋幕涂布(curtain coating)，或者是其它适合的沉积方式，例如液相沉积(liquid phasedeposition)、物理气相沉积(physical vapor deposition；PVD)、化学气相沉积(chemical vapor deposition；CVD)、低压化学气相沉积(low pressure chemicalvapor deposition；LPCVD)、等离子体增强式化学气相沉积(plasma enhancedchemical vapor deposition；PECVD)、快速热化学气相沉积(rapid thermal-CVD；RTCVD)或常压化学气相沉积(atmospheric pressure chemical vapor deposition；APCVD)的方式形成。
接着，请参阅图1G，形成深入间隔层11中且暴露导电电极7的开口25。例如通过光刻/蚀刻(photolithography/etching)步骤，图案化此绝缘层23，介于导电电极7与晶片3之间的绝缘层以及部分间隔层11，以形成深入间隔层11中且暴露导电电极7的开口25(未显示)；或是通过刻痕装置实施刻痕步骤以切开绝缘层23及导电电极7而深入至部分的间隔层11，以形成暴露电极7侧边的开口25。
然后，在开口25内侧壁及底部上形成导线层27，且延伸至承载基板1下表面的部分绝缘层23上，其中，导线层27可与导电电极7电性接触，在本例中为与导电电极7的侧边电性接触；在另一实施例中，导线层27可与导电电极7的下表面电性接触。导线层27一般可以是铜、铝、银、镍或其合金的导电材料层，并利用例如是电镀或溅镀的方式，顺应性地沉积于承载基板1的背面10上，并延伸至开口25的倾斜侧面及底部。之后，进行光刻/蚀刻工艺(photolithography/etching)，图案化上述导电材料层，以形成导线层27。
其次，如图1H所示，在上述导线层27完成后，形成保护层(passivationlayer)29于各导线层27上，覆盖承载基板1的背面10及填满开口25，保护层29例如为阻焊膜(solder mask)，在实施例中，在形成上述保护层29后，可通过图案化此保护层29以形成暴露部分导线层27的开口31。
接着，请参阅图1I，在形成导电凸块(conductive bump)33之前，在盖板13中对应感测薄膜9的位置上形成连通至间隙15的开口35，其中此开口35可以是单一开口或是多孔结构以连通外在的流体，并薄化盖板13。在实施例中，感测薄膜9的面积大于或等于开口35的总面积，优选比例为介于1至1.5之间，如此可维持盖板13的强度和保护的效果，同时不影响感测薄膜9侦测通过开口35的流体，其中当盖板13由硅基板构成时，上述开口35可通过干蚀刻工艺形成；此外为避免盖板13透过间隔层11传导应力而影响到感测薄膜9的侦测，此间隔层11与感测薄膜9水平方向之间可包括应力缓冲区40，例如此间隔层11与感测薄膜9水平方向之间可相隔既定间距40，例如100um以上，或者在间隔层11与感测薄膜9水平方向之间的硅晶片3上可形成一或多个凹洞以阻隔应力，此凹洞中亦可考虑填入缓冲材料。最后，在开口31的位置形成导电凸块(conductive bump)33以与导线层27电性连接。在实施例中，可通过电镀或网版印刷(screen printing)的方式，将焊料(solder)填入于上述开口31中，且进行回焊(re-flow)工艺，以形成例如是焊球(solderball)或焊垫(solder paste)的导电凸块33。接着，沿切割道SC(scribe line)分割上述晶片3，以分离出各压力感测芯片，完成上述电子元件封装体500a的制作。
在上述实施例中，盖板13的开口35选择于保护层29工艺之后才暴露出来，因此可避免感测薄膜9遭受先前工艺的污染，而于导电凸块33工艺之前形成上述盖板13的开口35，则可避免于工艺中破坏导电凸块结构33。
图2A-2E显示根据本发明另一实施例的制作例如压力传感器封装体的电子元件封装体500b的示意图。如图2A所示，提供晶片(wafer)3，其具有上表面20和下表面30，其下表面30向内部形成有多个凹洞(cavity)5，且通过接合晶片3下表面30的承载基板1所密封，承载基板1可例如为玻璃基板，其厚度可介于300μm至500μm之间，优选可为400μm。上述晶片3的材料可以是硅，或者是其它具有良好散热能力或高传导热系数的基底，并通过例如是湿蚀刻(wet etching)的方式，蚀刻此晶片3，以形成上述凹洞5。上述晶片3的厚度可介于100μm至200μm之间，优选可为140μm。在实施例中，粘着胶如环氧树脂(epoxy)，可用来接合晶片3与承载基板1。在本发明实施例中，晶片3上可设有包括压力感测芯片等多个微机电装置，在晶片3的上表面20则覆盖着一层感测薄膜9，例如压电材料，可用以感应外界环境或流体的变化，在感测薄膜9的周围则包括导电电极或导电垫7，用以传导来自感测薄膜9的感测信号。而且硅晶片3与导电电极7之间通过形成绝缘层予以隔离，例如，由氧化硅、氮氧化硅或低介电常数材料层组成，在此未予显示。
如图2B所示，接着，在晶片3的上表面20上还可以形成封装层或盖板53。在实施例中，盖板53与导电电极7之间可设置间隔层(spacer)11，以在盖板53与感测薄膜9之间形成间隙(cavity)55，而间隔层11则围绕着间隙15。盖板53可以是例如玻璃、石英(quartz)、蛋白石(opal)、塑胶等，在此以硅基板为例，主要是用以在后续形成开口以供流体进出，其厚度可介于200μm至400μm之间，优选可为300μm。间隔层11可例如为环氧树脂(epoxy)等粘着材料，一般而言，间隔层11位于导电电极7上。其中，上述盖板53可先行制作开口65，并于盖板53上表面先行贴上一层密封层67如胶带并封住该开口65，之后再将此盖板53附着于晶片3的上表面上以连通间隙55与开口65，其中此开口65可以是单一开口或是多孔结构。
接着，可选择进一步薄化承载基板1的步骤。例如从承载基板1的背面10予以薄化至预定厚度，例如由400um研磨至120um。该薄化工艺可以是蚀刻(etching)、铣削(milling)、磨削(grinding)或研磨(polishing)等方式。
其次，请参阅图2C，在预定切割道或导电电极7下方的位置形成贯穿承载基板1并深入至晶片3的开口17，在实施例中可通过刻痕装置(notchequipment)实施刻痕步骤，如以大致为60度角的切刀切开承载基板1及晶片3而形成可视为通道凹口(channel notch)的开口17。然后，沿着开口17对晶片3进行蚀刻以形成底部较宽的开口19，例如对硅晶片3实施硅蚀刻步骤以去除掉开口侧壁及底部的晶片材料，其中导电电极7与晶片3之间的绝缘层在此步骤中可作为蚀刻停止层。
请参阅图2D，接着于开口19的位置形成上部较宽的开口21，例如使用刻痕装置(notch equipment)实施刻痕步骤以切割承载基板1，其中此刻痕装置的切刀较宽或切角较大，例如选择大于60度角的切刀，优选者为选择75度至80度角的切刀，因此所形成的开口21其上部(位于承载基板1内部的部分)较宽且倾斜角大于底部(位于晶片3内部的部分)，有利于后续导线的沉积，此外，开口21的上部(位于承载基板1内部的部分)及底部(位于晶片3内部的部分)的侧壁连接在一起，因此，可避免后续填充绝缘层23时产生孔洞。接着，形成绝缘层23于上述开口21中。在实施例中，上述绝缘层23形成于承载基板1下表面10，并填充至开口21中。上述绝缘层23优选可以是环氧树脂(epoxy)、防焊材料(solder mask)或其它适合的绝缘物质，例如无机材料的氧化硅层、氮化硅层、氮氧化硅层、金属氧化物或其组合，或者是有机高分材料的聚酰亚胺树脂(polyimide；PI)、苯环丁烯(butylcyclobutene；BCB)、聚对二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(accrylates)等的绝缘沉积层，且可以是利用涂布方式，例如旋转涂布(spin coating)、喷涂(spray coating)或淋幕涂布(curtain coating)，或者是其它适合的沉积方式，例如液相沉积(liquid phase deposition)、物理气相沉积(physical vapor deposition；PVD)、化学气相沉积(chemical vapor deposition；CVD)、低压化学气相沉积(low pressure chemical vapor deposition；LPCVD)、等离子体增强式化学气相沉积(plasma enhanced chemical vapor deposition；PECVD)、快速热化学气相沉积(rapid thermal-CVD；RTCVD)或常压化学气相沉积(atmospheric pressure chemical vapor deposition；APCVD)的方式形成
接着，仍请参阅图2D，形成暴露导电电极7的开口25。例如通过光刻/蚀刻(photolithography/etching)步骤，图案化此绝缘层23以及介于导电电极7与晶片3之间的绝缘层，以形成暴露导电电极7的开口25(未显示)；或是通过刻痕装置实施刻痕步骤以切开绝缘层23及导电电极7而深入至部分的间隔层11，以形成暴露导电电极7侧边的开口25。
然后，在开口25内侧壁及底部上形成导线层27，且延伸至承载基板1下表面的绝缘层上，其中，导线层27可与导电电极7电性接触，在本例中为与导电电极7的侧边电性接触；在另一实施例中，导线层27可与导电电极7的下表面电性接触。导线层27一般可以是铜、铝、银、镍或其合金的导电材料层，并利用例如是电镀或溅镀的方式，顺应性地沉积于承载基板1的背面10上，并延伸至开口25的倾斜侧面及底部。之后，进行光刻/蚀刻工艺(photolithography/etching)，图案化上述导电材料层，以形成导线层27。
其次，如图2E所示，在上述导线层27完成后，形成保护层(passivationlayer)29于各导线层27上，覆盖承载基板1的背面10及填满开口25，保护层29例如为阻焊膜(solder mask)，在实施例中，在形成上述保护层29后，可通过图案化此保护层29以形成暴露部分导线层27的开口31。
接着，在开口31的位置形成导电凸块(conductive bump)33以与导线层27电性连接。在实施例中，可通过电镀或网版印刷(screen printing)的方式，将焊料(solder)填入于上述开口31中，且进行回焊(re-flow)工艺，以形成例如是焊球(solder ball)或焊垫(solder paste)的导电凸块33。在形成导电凸块(conductive bump)33之后，将胶带67去除，以于盖板13中对应感测薄膜9的位置上露出连通至间隙55的开口65，其中此开口可以是单一开口或是多孔结构以连通外在的流体。在实施例中，感测薄膜9的面积大于或等于开口65的总面积，优选比例为介于1至1.5之间，如此可维持盖板53的强度和保护的效果，同时不影响感测薄膜9侦测通过开口65的流体；此外为避免盖板13透过间隔层11传导应力而影响到感测薄膜9的侦测，此外为避免盖板13透过间隔层11传导应力而影响到感测薄膜9的侦测，此间隔层11与感测薄膜9水平方向之间可包括应力缓冲区40，例如此间隔层11与感测薄膜水平方向之间可相隔既定间距40，例如100um以上，或者在间隔层11与感测薄膜9水平方向之间的硅晶片3上可形成一或多个凹洞以阻隔应力，此凹洞中亦可考虑填入缓冲材料。最后，将例如胶带的密封层67撕开，沿切割道SC(scribe line)分割上述晶片，以分离出各压力感测芯片，完成上述电子元件封装体500b。
在上述实施例中，由于盖板53先行制作开口65且以例如胶带的密封层67密封后，再附着于晶片3上，因此可避免制造过程中对感测薄膜9的污染。
由于上述实施例的电子元件封装体500a或500b皆以晶片级封装工艺制作，因此，电子元件封装体具有相对较小的尺寸。此外，在电子元件封装体中是使用导线层或导电凸块电性连接芯片的电极，并非是接合导线(wirebond)，因此，也可缩小电子元件封装体的尺寸。
虽然本发明已以实施例披露如上，然其并非用以限定本发明，任何本领域一般技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定为准。

Claims (24)

1.一种电子元件封装体的制作方法，包括：
提供晶片，其具有上表面和下表面，该上表面上设有导电电极；
在该晶片的该上表面覆盖盖板；
在该晶片的该下表面覆盖保护层；
在该保护层上形成电性接触该导电电极的导电凸块；以及
在该盖板上形成开口结构；其中形成该开口结构的步骤，是于该晶片的该上表面覆盖该盖板之前实施，或者在该晶片的该下表面覆盖该保护层之后且于形成该导电凸块之前实施。
2.如权利要求1所述的电子元件封装体的制作方法，其中该晶片上设有多个微机电装置。
3.如权利要求2所述的电子元件封装体的制作方法，其中所述微机电装置包括压力感测芯片，该上表面覆盖感测薄膜。
4.如权利要求3所述的电子元件封装体的制作方法，其中该感测薄膜与该盖板之间包括间隙，该间隙由间隔层所围绕，且该间隔层与该感测薄膜水平方向之间包括应力缓冲区。
5.如权利要求4所述的电子元件封装体的制作方法，其中该间隔层位于该盖板与该导电电极之间。
6.如权利要求4所述的电子元件封装体的制作方法，其中该间隔层与该感测薄膜相距既定间距。
7.如权利要求1所述的电子元件封装体的制作方法，其中该开口结构包括单一开口或多孔结构。
8.如权利要求1所述的电子元件封装体的制作方法，其中该晶片的该下表面向内部形成有多个凹洞，且所述凹洞通过接合该晶片的该下表面的承载基板所密封。
9.如权利要求8所述的电子元件封装体的制作方法，在该晶片的该上表面覆盖该盖板之后还包括对该承载基板的背面进行薄化工艺，以薄化该承载基板至预定厚度。
10.如权利要求9所述的电子元件封装体的制作方法，其中该薄化工艺包括蚀刻、铣削、磨削或研磨。
11.如权利要求1所述的电子元件封装体的制作方法，在该晶片的该下表面覆盖该保护层之前还包括：
从该晶片的该下表面移除部分该晶片，以于该导电电极下方的位置形成第一开口；
在该晶片的该下表面和该第一开口中形成绝缘层；
移除部分该第一开口中的部分该绝缘层，以形成第二开口，并暴露出该导电电极；以及
在该第二开口的内侧壁及底部上形成导线层，且延伸至该晶片的该下表面的部分该绝缘层上，其中该导线层电性接触该导电电极。
12.如权利要求11所述的电子元件封装体的制作方法，其中该保护层形成于该导线层上，且填入该第二开口。
13.如权利要求4所述的电子元件封装体的制作方法，其中该开口结构对应形成于该感测薄膜位置的正上方，且连通至该间隙。
14.如权利要求3所述的电子元件封装体的制作方法，其中该感测薄膜与该开口结构的面积比介于1至1.5之间。
15.一种电子元件封装体，包括：
感测芯片，该感测芯片的上表面包括感测薄膜；
具有开口结构的盖板，覆盖该感测芯片的该上表面，该盖板与该感测芯片之间于对应该感测薄膜位置上包括连通该开口结构的间隙；以及
间隔层，介于该盖板与该感测芯片之间且围绕着该间隙。
16.如权利要求15所述的电子元件封装体，其中该间隔层与该感测薄膜水平方向之间包括应力缓冲区。
17.如权利要求15所述的电子元件封装体，还包括导电电极，设置于该感测芯片的该上表面上，且介于该间隔层与该感测芯片之间。
18.如权利要求15所述的电子元件封装体，其中，该间隔层与该感测薄膜相距既定间距。
19.如权利要求15所述的电子元件封装体，其中，该盖板为硅基板。
20.如权利要求16所述的电子元件封装体，其中，该开口结构包括单一开口或多孔结构。
21.如权利要求15所述的电子元件封装体，其中该感测芯片的该下表面向内部形成有多个凹洞，且所述凹洞通过接合该感测芯片的该下表面的承载基板所密封。
22.如权利要求16所述的电子元件封装体，还包括：
开口，从该感测芯片的该下表面深入至该晶片，其中该开口的底部暴露出该导电电极；
绝缘层，形成于感测芯片的该下表面和该开口的内侧壁上；
导线层，形成于该开口的该内侧壁及该底部上，且延伸至该感测芯片的该下表面的部分该绝缘层上，其中该导线层电性接触该导电电极；
保护层，覆盖于感测芯片的该下表面；以及
导电凸块，形成于该保护层上，且电性接触该导电电极。
23.如权利要求22所述的电子元件封装体，其中该保护层形成于该导线层上，且填入该开口。
24.如权利要求15所述的电子元件封装体，其中该感测薄膜与该开口结构的面积比介于1至1.5之间。
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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102009378A (zh) * 2010-11-01 2011-04-13 天水七四九电子有限公司 电子器件特殊管基的启盖方法
CN102479808A (zh) * 2010-11-26 2012-05-30 三星电子株式会社 半导体器件及其制造方法
CN102593085A (zh) * 2011-01-10 2012-07-18 原相科技股份有限公司 芯片封装结构以及芯片封装制程
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CN102922961A (zh) * 2012-11-12 2013-02-13 西安交通大学 一种电容式微型胎压传感器
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Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI473223B (zh) 2009-08-19 2015-02-11 Xintec Inc 晶片封裝體及其製造方法
TWI579995B (zh) * 2009-08-19 2017-04-21 Xintex Inc 晶片封裝體及其製造方法
US8698316B2 (en) 2010-03-11 2014-04-15 Yu-Lin Yen Chip package
US8692382B2 (en) 2010-03-11 2014-04-08 Yu-Lin Yen Chip package
JP5911144B2 (ja) * 2010-07-02 2016-04-27 国立研究開発法人産業技術総合研究所 微小機械システム
US8618620B2 (en) 2010-07-13 2013-12-31 Infineon Technologies Ag Pressure sensor package systems and methods
TWI459529B (zh) * 2011-07-21 2014-11-01 Xintec Inc 晶片封裝體及其形成方法
US20130307147A1 (en) * 2012-05-18 2013-11-21 Xintec Inc. Chip package and method for forming the same
JP5877248B2 (ja) * 2012-10-17 2016-03-02 株式会社鷺宮製作所 圧力センサおよび、それを備えるセンサユニット
DE102013107862A1 (de) * 2013-07-23 2015-01-29 Osram Opto Semiconductors Gmbh Oberflächenmontierbares optoelektronisches Halbleiterbauteil und Verfahren zur Herstellung zumindest eines oberflächenmontierbaren optoelektronischen Halbleiterbauteils
US11033898B2 (en) * 2014-02-01 2021-06-15 Ezmems Ltd. Fluidic microelectromechanical sensors/devices and fabrication methods thereof
US10305019B1 (en) 2014-03-28 2019-05-28 Intel Corporation Piezoelectric devices fabricated in packaging build-up layers
US9704772B2 (en) 2014-04-02 2017-07-11 Xintec Inc. Chip package and method for forming the same
TWI569427B (zh) * 2014-10-22 2017-02-01 精材科技股份有限公司 半導體封裝件及其製法
TWI588954B (zh) * 2015-02-16 2017-06-21 精材科技股份有限公司 晶片封裝體及其製造方法
TWI600125B (zh) * 2015-05-01 2017-09-21 精材科技股份有限公司 晶片封裝體及其製造方法
US10672937B2 (en) * 2015-09-02 2020-06-02 Pixart Imaging Inc. Optical sensor module and sensor chip thereof
JP6557776B2 (ja) * 2015-09-02 2019-08-07 蘇州晶方半導体科技股▲分▼有限公司Ｃｈｉｎａ Ｗａｆｅｒ Ｌｅｖｅｌ Ｃｓｐ Ｃｏ．， Ｌｔｄ． パッケージ構造およびパッケージング方法
US10354114B2 (en) * 2016-06-13 2019-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor in InFO structure and formation method
TWI606560B (zh) * 2016-06-16 2017-11-21 思鷺科技股份有限公司 封裝結構
WO2019023646A2 (en) 2017-07-27 2019-01-31 Maxim Integrated Products, Inc. ANALYTE SENSOR HOUSING AND METHOD FOR ANALYZING FLUID SAMPLES
CN109794855B (zh) * 2017-11-17 2020-09-11 长鑫存储技术有限公司 对作用于基底上的压力的测量方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6278167B1 (en) * 1998-08-14 2001-08-21 Infineon Technologies Ag Semiconductor sensor with a base element and at least one deformation element
US6432737B1 (en) * 2001-01-03 2002-08-13 Amkor Technology, Inc. Method for forming a flip chip pressure sensor die package
JP2002315097A (ja) * 2001-04-16 2002-10-25 Mitsubishi Electric Corp 圧力感応装置及びこれに用いられる半導体基板の製造方法
DE102005053765B4 (de) * 2005-11-10 2016-04-14 Epcos Ag MEMS-Package und Verfahren zur Herstellung
GB0605576D0 (en) * 2006-03-20 2006-04-26 Oligon Ltd MEMS device
CN100423249C (zh) * 2006-10-17 2008-10-01 晶方半导体科技（苏州）有限公司 “n”形电连接晶圆级芯片尺寸封装结构及其制造方法
TWI315295B (en) 2006-12-29 2009-10-01 Advanced Semiconductor Eng Mems microphone module and method thereof
US7569409B2 (en) * 2007-01-04 2009-08-04 Visera Technologies Company Limited Isolation structures for CMOS image sensor chip scale packages
CN101236938A (zh) 2007-02-01 2008-08-06 精材科技股份有限公司 芯片封装模块的散热方法及构造
CN100552963C (zh) 2007-03-28 2009-10-21 精材科技股份有限公司 集成电路封装体及其制作方法
CN101123231B (zh) * 2007-08-31 2010-11-03 晶方半导体科技（苏州）有限公司 微机电系统的晶圆级芯片尺寸封装结构及其制造方法
CN101249936B (zh) 2008-04-10 2010-06-02 日月光半导体制造股份有限公司 微机电系统的封装构造及其制造方法

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