CN102034778B - 芯片封装体及其制造方法 - Google Patents
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Abstract
本发明提供一种芯片封装体及其制造方法,该芯片封装体包括:半导体基底,具有第一表面和相对的第二表面,其中半导体基底包含半导体元件和导电垫,设置于第一表面上。导通孔,自半导体基底的第二表面向内延伸并连通至导电垫。重布线路堆叠层,位于半导体基底第二表面之下,并与导通孔内的导电垫电性连接,且该重布线路堆叠层的边缘外露于该半导体基底侧壁。导线层,位于重布线路堆叠层之下,且延伸至半导体基底侧壁而与重布线路堆叠层构成电性接触。
Description
技术领域
本发明涉及一种芯片封装体,特别涉及一种具有导通孔以及重布线路堆叠层的芯片封装体及其制造方法。
背景技术
传统的芯片封装技术是将芯片粘着于印刷电路板上,然后再利用引线接合的方式,电性连接芯片与印刷电路板,最后利用封胶材料覆盖引线接合处,以形成芯片封装体。
然而由于传统的芯片封装体在引线接合处会形成封胶材料的凸块,使得传统的芯片封装体的表面为凹凸面,当其应用于指纹辨识器时,芯片封装体的凹凸面会降低指纹辨识率。
因此,业界亟需一种芯片封装体,其可以使得芯片封装体具有平坦的表面。
发明内容
为解决上述问题,本发明提供一种芯片封装体,包括:半导体基底,具有第一表面和相对的第二表面,其中半导体基底包含半导体元件和导电垫,设置于第一表面上。导通孔,自半导体基底的第二表面向内延伸并连通至导电垫。重布线路堆叠层,位于半导体基底第二表面之下,并与导通孔内的导电垫电性连接,且该重布线路堆叠层的边缘外露于该半导体基底侧壁。导线层,位于重布线路堆叠层之下,且延伸至半导体基底侧壁而与重布线路堆叠层构成电性接触。
此外,本发明还提供一种芯片封装体的制造方法,包括:提供半导体晶片,具有第一表面和相对的第二表面,其中该半导体晶片包含多个半导体元件和多个导电垫,设置于该第一表面上;自该半导体晶片的第二表面形成多个导通孔,其向内延伸并连通至该些导电垫;自该半导体基底第二表面之下形成重布线路堆叠层,其与该些导通孔内的导电垫电性连接,且该重布线路堆叠层的边缘外露于该半导体基底侧壁;及自该重布线路堆叠层之下形成导线层,其延伸至该半导体基底侧壁而与该重布线路堆叠层构成电性接触。
为了让本发明的上述目的、特征、及优点能更明显易懂,以下配合附图,作详细说明如下:
附图说明
图1A-图1J显示依据本发明的实施例,形成芯片封装体的制造方法的剖面示意图。
附图标记说明
100~半导体基底 100’~薄化的半导体基底
100a~半导体基底的第一表面
100b~半导体基底的第二表面
102~芯片 104~导电垫
108、124~粘着层 110~暂时的载体层
112~导通孔 114、118、128~绝缘层
120、136~开口 116、122~重布线路层
126~封装层 130~沟槽凹口
132~导线层 134、140~保护层
138~导电凸块 T~T型接触
SL~切割线 200~芯片封装体
具体实施方式
以下以实施例并配合附图详细说明本发明,在附图或说明书描述中,相似或相同的部分使用相同的图号。且在附图中,实施例的形状或是厚度可扩大,以简化或是方便标示。再者,附图中各元件的部分将以描述说明,值得注意的是,图中未绘示或描述的元件,为所属技术领域中普通技术人员所知的形式。另外,特定的实施例仅为揭示本发明使用的特定方式,其并非用以限定本发明。
本发明以制作感测元件封装体(sensor package)的实施例作为说明,特别是应用在指纹辨识器的芯片封装体。然而,可以了解的是,在本发明的芯片封装体的实施例中,其可应用于各种包含有源元件或无源元件(active orpassive elements)、数字电路或模拟电路(digital or analog circuits)等集成电路的电子元件(electronic components),例如是有关于光电元件(opto electronicdevices)、微机电系统(Micro Electro Mechanical System;MEMS)、微流体系统(micro fluidic systems)、或利用热、光线及压力等物理量变化来量测的物理传感器(Physical Sensor)。特别是可选择使用晶片级封装(wafer scale package;WSP)工艺对影像感测元件、发光二极管(light-emitting diodes;LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件(surface acoustic wavedevices)、压力传感器(process sensors)或喷墨头(ink printer heads)等半导体芯片进行封装。
其中上述晶片级封装工艺主要是指在晶片阶段完成封装步骤后,再予以切割成独立的封装体,然而,在特定实施例中,例如将已分离的半导体芯片重新分布在承载晶片上,再进行封装工艺,也可称之为晶片级封装工艺。另外,上述晶片级封装工艺也适用于通过堆叠(stack)方式安排具有集成电路的多片晶片,以形成多层集成电路(multi-layer integrated circuit devices)的芯片封装体。
本发明的实施例提供一种芯片封装体及其制造方法,利用导通孔(through hole)以及形成T型接触(T-contact)的工艺技术,使得芯片封装体具有平坦的感测表面。
请参阅图1A至图1J,其显示依据本发明的实施例,形成芯片封装体的制造方法的剖面示意图。如图1A所示,首先提供半导体基板100,一般为半导体晶片(如硅晶片)或硅基板。其次,半导体基板定义有多个元件区100A,围绕元件区100A者为周边接垫区100B。元件区100A及周边接垫区100B共同形成部分的管芯区。
接续,在元件区100A制作半导体元件102,例如指纹辨识器、影像传感器元件或是其他微机电结构,而覆盖上述半导体基板100及半导体元件102者为层间介电层103(IMD),一般可选择低介电系数(low k)的绝缘材料,例如多孔性氧化层。接着于周边接垫区100B的层间介电层103中制作多个导电垫结构104。在此实施例中,所形成的导电垫结构包括多层金属层,优选可以由铜(copper;Cu)、铝(aluminum;Al)或其它合适的金属材料所制成。
此外,半导体基板100可覆盖有芯片保护层106(passivation layer),同时为将芯片内的元件电性连接至外部电路,可事先定义芯片保护层106以形成多个暴露出导电垫结构的开口106h。
接着,请参阅图1B,提供载体层110,例如为半导体基底或玻璃基底,半导体基底可以是另一空白硅晶片,通过粘着层(adhesive layer)108将载体层110与半导体晶片100的第一表面100a接合,粘着层108可以是含有环氧树脂的粘着剂,其中为方便说明起见,上述半导体基板100仅揭示半导体元件102和导电垫结构104。然后,通过例如是化学机械抛光(chemical mechanicalpolishing;CMP)法或蚀刻(etching)、铣削(milling)、磨削(grinding)或抛光(polishing)的方式,将半导体晶片100薄化,在实施例中,薄化后的半导体晶片100’的厚度约为30至50μm。
请参阅图1C,以光刻及蚀刻工艺在半导体晶片100’的第二表面100b上形成多个导通孔112,暴露出该些导电垫104,接着在半导体晶片100’的第二表面100b上以涂布的方式形成绝缘层114,且延伸至该些导通孔112的侧壁上,绝缘层114的材料可以是氧化层或是感光绝缘材料,例如含有环氧树脂(epoxy)的光致抗蚀剂材料,其中位于导通孔112底部的绝缘层114可利用显影方式去除。在实施例中,绝缘层114的厚度可介于约5至15μm之间,优选为10μm。
接着,进行重布线路堆叠层的制作。请参阅图1D,在绝缘层114上顺应性地形成导电层116,且延伸至导通孔112的侧壁及底部上,与导电垫104接触,产生电性连接。由于导电层116可重新布局传递信号的传导线路,因此导电层116也可以称为重布线路层。可通过例如是溅镀(sputtering)、蒸镀(evaporating)或电镀(electroplating)的方式,沉积例如是铜、铝或镍(nickel;Ni)的导电材料层(未绘示)于绝缘层114上以及导通孔112内,再通过光刻及蚀刻工艺图案化导电材料层,以形成上述导电层116。
请参阅图1E,在半导体晶片100’的第二表面100b上形成绝缘层118,覆盖导电层116和绝缘层114,绝缘层118的材料可以是氧化层或是感光绝缘材料,例如含有环氧树脂(epoxy)的光致抗蚀剂材料,在实施例中,绝缘层118的厚度可介于约20至30μm之间,优选为25μm。此外,在实施例中,绝缘层118的材料可以与绝缘层114相同。
接着,以曝光显影方式在绝缘层118中形成开口120,暴露出导电层116的一部分,然后在绝缘层118上顺应性地形成重布线路层122,且延伸至开口120的侧壁及底部上,与导电层116接触,以产生电性连接。可通过例如是溅镀(sputtering)、蒸镀(evaporating)或电镀(electroplating)的方式,沉积例如是铜、铝或镍(nickel;Ni)的导电材料层(未绘示)于绝缘层118上以及开口120内,再通过光刻及蚀刻工艺图案化导电材料层,以形成上述重布线路层122。其中值得注意的是,由于后续工艺会于管芯区外缘形成沟槽凹口130,因此重布线路层116为内缩而与沟槽凹口相隔间距,而重布线路层122则至少延伸至沟槽凹口的预定区域内或管芯区的外缘,以便与后续的重布线路层132形成接触。
请参阅图1F,提供封装层126,封装层126例如为半导体基底或玻璃基底,通过粘着层124,例如为含有环氧树脂的粘着剂,将封装层126接合于重布线路层122以及绝缘层118上,封装层126可以支撑薄化后的半导体晶片100’,强化芯片封装体的机械强度。接着,在封装层126上形成绝缘层128,例如为环氧树脂(epoxy)或阻焊膜(solder mask)的材料,其可以作为应力释放层(stress release layer)。
请参阅图1G,对半导体晶片100’的第二表面100b上的绝缘层128、封装层126、粘着层124、重布线路层122以及绝缘层118进行刻痕(notching)步骤,形成沟槽凹口(channel of notch)130,沟槽凹口130由绝缘层128延伸至绝缘层118,但并未贯穿绝缘层118,并且重布线路层122的边缘经由沟槽凹口130暴露出来,其中,绝缘层118作为缓冲,以避免切割刀切至硅基底100’。
接着,请参阅图1H,在绝缘层128上形成导线层132,且延伸至沟槽凹口130的侧壁及底部上,与重布线路层122构成电性接触,例如形成T型接触T。可通过例如是溅镀(sputtering)、蒸镀(evaporating)或电镀(electroplating)的方式,沉积例如是铜、铝或镍(nickel;Ni)的导电材料层(未绘示)于绝缘层128上以及沟槽130内,再通过光刻及蚀刻工艺图案化导电材料层,以形成上述导线层132。然后,在绝缘层128以及导线层132上涂布例如是阻焊膜(solder mask)的保护层134,覆盖导线层132,接着,图案化保护层134,形成开口136,以暴露部分的导线层132。接着,在保护层134的开口136内涂布焊料,且进行回焊(reflow)步骤,以形成导电凸块138,导电凸块138可以是球状栅格阵列(ball grid array;BGA)或平面栅格阵列(land grid array;LGA)。
请参阅图1I,在实施例中,此载体层110可予以除去,例如通过化学机械抛光(chemical mechanical polishing;CMP)法或蚀刻(etching)、铣削(milling)、磨削(grinding)或抛光(polishing)的方式将暂时的载体层110除去,或者也可以利用剥离的方式移除暂时的载体层110。然后在选择性的步骤中,在粘着层108上形成保护层140,其可以是阻焊膜(solder mask)的材料,硬度高(约大于7),因此具有防刮及耐磨的功效。
然后沿着切割线SL将半导体晶片100’分割,即可形成多个芯片封装体200,如图1J所示。
请参阅图1J,其显示依据本发明实施例的芯片封装体的剖面示意图,沿着切割线SL分离晶片成芯片封装体200。半导体基底100’例如由包含管芯区的薄化后半导体晶片分割而来,管芯区中,半导体基底100’的元件区100A上具有半导体元件102,以及位于周边接垫区100B的多个导电垫(conductivepad)104围绕着元件区100A。导电垫104例如为接合垫(bonding pad),可透过金属连线(未显示)连接至半导体元件102。
在实施例中,芯片封装体200可应用于指纹辨识器,或感测元件,例如互补式金属氧化物半导体元件(CMOS)或电荷耦合元件(charge-couple device;CCD),此外如微机电元件等亦不在此限。
在实施例中,上述重布线路堆叠层116、122以及导线层132可通过例如是溅镀(sputtering)、蒸镀(evaporating)或电镀(electroplating)的方式,沉积例如是铜、铝或镍(nickel;Ni)的导电材料层(未绘示),再通过光刻及蚀刻工艺图案化导电材料层而形成,并且电性连接至导电垫104。
依据本发明的实施例,可在芯片封装体内利用导通孔112、重布线路堆叠层116、122,以及与其中的重布线路层122的边缘构成电性接触的导线层132,达到与芯片的导电垫104产生电性连接的目的,并形成具有平坦封装表面的芯片封装体。当本发明实施例的芯片封装体应用于指纹辨识器时,可提升指纹辨识率。
值得注意的是,重布线路堆叠层以及绝缘层可增加形成T型接触所需的绝缘层厚度,避免构成T型接触的导线层132过于接近半导体基底100’。
另外,本发明实施例的芯片封装体中的导通孔形成于减薄后的晶片内,由于导通孔的深度可降低,导通孔的直径也可以随之缩小,因此可应用于导电垫间距(pitch)较小的芯片上,在实施例中,芯片的导电垫的间距可小于100μm。
此外,本发明实施例的芯片封装体中的封装层126可支撑减薄后的半导体基底100’,增加芯片封装体200的机械强度,而设置于封装层126上的绝缘层128则可以作为应力释放层,当芯片封装体受到外力冲击时,可避免芯片封装体被损坏。另外,设置于芯片封装体外围的保护层140则可以提供防刮及耐磨的功效,避免芯片封装体受到损害。
虽然本发明已披露优选实施例如上,然其并非用以限定本发明,任何本领域一般技术人员,在不脱离本发明的精神和范围内,当可做些许更动与润饰,因此本发明的保护范围当视所附的权利要求所界定为准。
Claims (14)
1.一种芯片封装体,包括:
半导体基底,具有第一表面和相对的第二表面,包含半导体元件和导电垫,设置于该第一表面上;
导通孔,自该半导体基底的第二表面向内延伸并连通至该导电垫;
重布线路层,位于该半导体基底第二表面之下,并与该导通孔内的导电垫电性连接,且该重布线路层的边缘外露于该半导体基底侧壁;及
导线层,位于该重布线路层之下,且延伸至该半导体基底侧壁而与该重布线路层构成电性接触,
其中该导线层与该重布线路层构成T型接触,该重布线路层为一堆叠层,包括:第一重布线路层,位于该导通孔内以电性连接该导电垫,且延伸至该半导体基底第二表面之下;及第二重布线路层,位于该第一重布线路层之下并与该第一重布线路层电性连接,
其中所述封装体还包括:第一绝缘层,设置于该半导体基底与该第一重布线路层之间;以及第二绝缘层,设置于该第一重布线路层与该第二重布线路层之间,
其中该半导体基底侧壁具有沟槽凹口,该沟槽凹口底部延伸至该第二绝缘层上。
2.如权利要求1所述的芯片封装体,其中该第二绝缘层具有开口暴露出该第一重布线路层,该第二重布线路层形成于该开口中,与该第一重布线路层电性连接,且延伸至该第二绝缘层上。
3.如权利要求1所述的芯片封装体,其中该第二绝缘层的材料包括感光绝缘材料。
4.如权利要求1所述的芯片封装体,其中该导线层经由该沟槽凹口侧壁延伸至该第二绝缘层上。
5.如权利要求4所述的芯片封装体,其中该第一重布线路层与该沟槽凹口相隔间距,该第二重布线路层延伸至该沟槽凹口边缘而与该导线层电性连接。
6.如权利要求1所述的芯片封装体,还包括封装层,位于该半导体基底第二表面之下,且介于该重布线路层与该导线层之间。
7.如权利要求6所述的芯片封装体,还包括:
粘着层,位于该重布线路层与该封装层之间;及
第三绝缘层,位于该封装层与该导线层之间。
8.如权利要求7所述的芯片封装体,其中该第三绝缘层包括应力释放层。
9.如权利要求1所述的芯片封装体,还包括:
第一保护层,覆盖该导线层,并具有开口以暴露出该导线层;及
导电凸块,设置于该第一保护层的开口中,以与该导线层电性连接。
10.如权利要求1所述的芯片封装体,还包括:
第二保护层,覆盖该半导体基底的第一表面;及
粘着层,位于该半导体基底与该第二保护层之间。
11.如权利要求10所述的芯片封装体,其中该第二保护层具有平坦表面,且该第二保护层的材料包括硬度7以上的耐磨材料。
12.一种芯片封装体的制造方法,包括:
提供半导体晶片,具有第一表面和相对的第二表面,其中该半导体晶片包含多个半导体元件和多个导电垫,设置于该第一表面上;
自该半导体晶片的第二表面形成多个导通孔,其向内延伸并连通至所述导电垫;
自该半导体基底第二表面之下形成重布线路层,其与所述导通孔内的导电垫电性连接,且该重布线路层的边缘外露于该半导体基底侧壁;以及
自该重布线路层之下形成导线层,其延伸至该半导体基底侧壁而与该重布线路层构成电性接触,
其中该导线层与该重布线路层构成T型接触,
其中形成该重布线路层的步骤包括:
形成第一重布线路层于所述导通孔内以电性连接所述导电垫,且延伸至该半导体晶片第二表面之下;以及
形成第二重布线路层于该第一重布线路层之下并与该第一重布线路层电性连接,
其中该制造方法,还包括:
顺应性地形成第一绝缘层于该半导体晶片的该第二表面上以及所述导通孔的侧壁上;
形成第二绝缘层以覆盖该第一重布线路层与该第一绝缘层;
形成开口于该第二绝缘层内,暴露出该第一重布线路层;以及
形成第二重布线路层于该第二绝缘层的该开口内以电性连接该第一重布线路层,且延伸至该第二绝缘层上,
其中该制造方法还包括:
提供载体层,与该半导体晶片的该第一表面接合;
薄化该半导体晶片;
提供封装层,接合于该半导体晶片的该第二表面之下;
形成第三绝缘层于该封装层之下;以及
形成多个沟槽凹口于该第三绝缘层、该封装层和该第二绝缘层中,暴露出该第二重布线路层的边缘,并与该第一重布线路层相隔间距,其中该导线层顺应性地形成于所述沟槽凹口内,且延伸至该第三绝缘层上。
13.如权利要求12所述的芯片封装体的制造方法,还包括:
形成第一保护层覆盖该导线层;
形成多个开口于该第一保护层中,暴露出该导线层;以及
形成多个导电凸块于该第一保护层的所述开口中,与该导线层电性连接。
14.如权利要求13所述的芯片封装体的制造方法,其还包括
移除该载体层;
形成第二保护层于该半导体晶片的该第一表面之上;以及
分割该半导体晶片,形成多个芯片封装体。
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US20110079903A1 (en) | 2011-04-07 |
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