TWI593069B - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

Info

Publication number
TWI593069B
TWI593069B TW104131558A TW104131558A TWI593069B TW I593069 B TWI593069 B TW I593069B TW 104131558 A TW104131558 A TW 104131558A TW 104131558 A TW104131558 A TW 104131558A TW I593069 B TWI593069 B TW I593069B
Authority
TW
Taiwan
Prior art keywords
substrate
chip package
sidewall
insulating layer
layer
Prior art date
Application number
TW104131558A
Other languages
English (en)
Other versions
TW201631720A (zh
Inventor
黃玉龍
Original Assignee
精材科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 精材科技股份有限公司 filed Critical 精材科技股份有限公司
Publication of TW201631720A publication Critical patent/TW201631720A/zh
Application granted granted Critical
Publication of TWI593069B publication Critical patent/TWI593069B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/02016—Circuit arrangements of general character for the devices
    • H01L31/02019—Circuit arrangements of general character for the devices for devices characterised by at least one potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/00238—Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02335—Free-standing redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10156—Shape being other than a cuboid at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

晶片封裝體及其製造方法
本發明係有關於一種晶片封裝技術，特別為有關於一種晶片封裝體及其製造方法。
晶片封裝製程是形成電子產品過程中之重要步驟。晶片封裝體除了將晶片保護於其中，使其免受外界環境污染外，還提供晶片內部電子元件與外界之電性連接通路。
具有感測功能之晶片封裝體通常透過在晶片的上表面形成導電層作為信號接墊的外部電性連接路徑，並透過打線將導電層電性連接至電路板。
然而，上述製造方法通常在晶片的感測區上方沉積了多層膜層(例如，絕緣層)，造成感測區的敏感度降低。再者，上述晶片封裝體的整體高度也受限於打線高度，導致具有感測功能之電子產品的尺寸難以進一步縮小。
因此，有必要尋求一種新穎的晶片封裝體及其製造方法，其能夠解決或改善上述的問題。
本發明實施例係提供一種晶片封裝體，包括一第一基底，具有一上表面、一下表面及一側壁，其中一感測區或元件區及一導電墊鄰近於上表面。一通孔貫穿第一基底。一重 佈線層自下表面延伸至通孔內，且與導電墊電性連接，其中重佈線層更自下表面橫向延伸而突出於第一基底的側壁。
本發明實施例係提供一種晶片封裝體的製造方法，包括提供一第一基底，其具有一上表面、一下表面及一側壁，其中一感測區或元件區及一導電墊鄰近於上表面。形成一通孔，貫穿第一基底。形成一重佈線層，自下表面延伸至通孔內，且與導電墊電性連接，其中重佈線層更自下表面橫向延伸而突出於第一基底的側壁。
100‧‧‧第一基底
100a‧‧‧上表面
100b‧‧‧下表面
101‧‧‧側壁
110‧‧‧感測區或元件區
120‧‧‧晶片區
140、260‧‧‧絕緣層
160‧‧‧導電墊
180、280、400‧‧‧開口
200‧‧‧暫時性基底
220‧‧‧黏著層
240‧‧‧通孔
300‧‧‧重佈線層
320‧‧‧第二基底
340‧‧‧接合層
360、380‧‧‧側邊凹陷
420‧‧‧外部元件
440‧‧‧外部導電結構
460‧‧‧封裝層
第1A至1H圖係繪示出根據本發明一實施例之晶片封裝體的製造方法的剖面示意圖。
第2圖係繪示出根據本發明一實施例之晶片封裝體的平面示意圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝微機電系統晶片。然其應用不限於此，例如在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(MicroElectro Mechanical System，MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線、電容及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package，WSP)製程對影像感測元件、發光二極體(light-emitting diodes，LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。
請參照第1H圖，其繪示出根據本發明一實施例之晶片封裝體的剖面示意圖。在本實施例中，晶片封裝體包括一 第一基底100、一通孔240及一重佈線層(redistribution layer，RDL)300。第一基底100具有一上表面100a及一下表面100b，且具有一側壁101。在一實施例中，第一基底100可為一矽基底或其他半導體基底。
一絕緣層140設置於第一基底100的上表面100a上。一般而言，絕緣層140可由層間介電層(interlayer dielectric，ILD)、金屬間介電層(inter-metal dielectric，IMD)及覆蓋之鈍化層(passivation)組成。為簡化圖式，此處僅繪示出單層絕緣層140。在本實施例中，絕緣層140可包括無機材料，例如氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合或其他適合的絕緣材料。
在本實施例中，絕緣層140內具有一個或一個以上的導電墊160，鄰近於第一基底100的上表面100a。在一實施例中，導電墊160可為單層導電層或具有多層之導電層結構。為簡化圖式，此處僅以單層導電層作為範例說明，並以絕緣層140內的一個導電墊160作為範例說明。在本實施例中，絕緣層140內包括一個或一個以上的開口180，以露出對應的導電墊160。舉例來說，當導電墊160為具有多層之導電層結構時，開口180可露出多層導電層結構中的頂層導電層。
在本實施例中，晶片封裝體包括一感測區或元件區110，其可鄰近於第一基底100的上表面100a，且可透過內連線結構(未繪示)與導電墊160電性連接。在一實施例中，感測區或元件區110內可包括一影像感測元件。在另一實施例中，感測區或元件區110可用以感測生物特徵。舉例來說，感測區或 元件區110內可包括指紋辨識感測元件或其他生物特徵感測元件。在其他實施例中，感測區或元件區110可用以感測環境特徵，例如感測區或元件區110內可包括一溫度感測元件、一溼度感測元件、一壓力感測元件或其他適合的感測元件。
一個或一個以上的通孔240對應於導電墊160，自第一基底100的下表面100b朝上表面100a延伸，且貫穿第一基底100而露出鄰近於導電墊160的絕緣層140。
一絕緣層260設置於第一基底100的下表面100b，且延伸至通孔240的側壁及底部。在本實施例中，絕緣層260可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
一開口280貫穿通孔240底部上的絕緣層260，且延伸至絕緣層140內，以露出導電墊160的一部份。舉例來說，當導電墊160為具有多層之導電層結構時，開口280可露出多層導電層結構中的底層導電層。在某些實施例中，開口180與開口280位於導電墊160的相對兩側。
圖案化的重佈線層300設置於第一基底100的下表面100b，且順應性延伸至通孔240的側壁及底部上，並填滿開口280，因此重佈線層300突出於第一基底100的上表面100a。在其他實施例中，重佈線層300可同時填滿通孔240及開口280。重佈線層300可透過絕緣層260與第一基底100電性隔離，且可經由通孔240及開口280直接電性接觸或間接電性連接露 出的導電墊160。因此，通孔240及開口280內的重佈線層300也稱為矽通孔電極(through silicon via，TSV)。在一實施例中，重佈線層300可包括鋁、銅、金、鉑、鎳、錫、前述之組合、導電高分子材料、導電陶瓷材料(例如，氧化銦錫或氧化銦鋅)或其他適合的導電材料。
在本實施例中，晶片封裝體還包括互相連通的一側邊凹陷360及一側邊凹陷380，位於導電墊160外側。側邊凹陷360貫穿絕緣層140，且側邊凹陷380自側邊凹陷360的底部朝下表面100b延伸而貫穿第一基底100，進而露出第一基底100的下表面100b上的絕緣層260。在本實施例中，側邊凹陷380的一側壁構成第一基底100的側壁101。在一實施例中，側壁101傾斜於第一基底100的上表面100a。在其他實施例中，側壁101可大致上垂直於第一基底100的上表面100a。
在本實施例中，側邊凹陷380的尺寸大於側邊凹陷360的尺寸，使得絕緣層140自第一基底100的上表面100a橫向延伸而突出於第一基底100的側壁101。在本實施例中，第一基底100的下表面100b上的絕緣層260及重佈線層300皆自第一基底100的下表面100b橫向延伸而突出於第一基底100的側壁101。再者，絕緣層260具有一個或一個以上的開口400，對應地露出突出於側壁101的重佈線層300。
另外，請同時參照第1H圖及第2圖，其分別繪示出根據本發明一實施例之晶片封裝體的剖面示意圖及平面示意圖。在本實施例中，側邊凹陷360及側邊凹陷380沿著第一基底100的周圍延伸而橫跨第一基底100的四個側邊的全部長度，進 而露出第一基底100的四個側邊下方的絕緣層260。在另一實施例中，側邊凹陷360及側邊凹陷380可僅沿著第一基底100的其中一個側邊的一部份或全部長度橫向延伸。又另一實施例中，側邊凹陷360及側邊凹陷380可橫跨第一基底100的其中一個側邊的全部長度，且更沿著相鄰的另一側邊的一部份或全部長度橫向延伸。在其它實施例中，側邊凹陷360及側邊凹陷380可橫跨第一基底100的其中一個側邊的全部長度，且更沿著相鄰的兩側邊的一部份或全部長度橫向延伸。可以理解的是，雖然未繪示於圖式中，只要側邊凹陷沿著第一基底100的至少一個側邊的一部份或全部長度橫向延伸，側邊凹陷的實際數量及位置取決於設計需求。
再者，如第2圖所示，絕緣層140具有多個開口180，露出對應的導電墊160。通孔240位於對應的導電墊160下方，而重佈線層300自導電墊160及通孔240下方橫向延伸至絕緣層260下方。為清楚表示，此處以虛線繪示出重佈線層300的輪廓。絕緣層260具有多個開口400，露出對應的重佈線層300。可以理解的是，第2圖所示之部件的數量、形狀及位置係取決於設計需求而不限定於此。
第二基底320可透過一接合層340設置於下表面100b的絕緣層260上。在本實施例中，第二基底320可包括玻璃、矽或其他適合作為承載基底的材料。在某些實施例中，第二基底320內可包括特定應用積體電路(application-specific integrated circuit，ASIC)、訊號處理器(signal processor)或其他電子部件。在本實施例中，接合層340填滿通孔240。在其他 實施例中，接合層340可部分填入通孔240或完全不填入通孔240。在本實施例中，接合層340可包括黏著膠(glue)、氧化物、氧化物及金屬、聚合物或其他適合的接合材料。
一外部元件420可透過一黏著層(未繪示)貼附於第二基底320。在本實施例中，外部元件420可為電路板、晶片或中介層(interposer)。
一個或一個以上的外部導電結構440設置於對應的開口400內，以透過露出的重佈線層300電性連接至對應的導電墊160。再者，外部導電結構440延伸至外部元件420上，以將導電墊160與外部元件420電性連接。在其他實施例中，外部導電結構440可設置於絕緣層140的開口180內，而電性連接至對應的導電墊160。可以理解的是，外部導電結構440的實際數量及位置取決於設計需求。雖然未繪示於圖式中，可選擇性將一個以上的外部導電結構440分別設置於開口400及開口180內。在一實施例中，外部導電結構440可由開口400內的接合球(bonding ball)及自接合球延伸至外部元件420的接線(wire)所構成。再者，外部導電結構440可包括金或其他適合的導電材料。
在一實施例中，外部導電結構440的最高部分低於第一基底100的上表面100a。在其他實施例中，外部導電結構440的最高部分可突出於第一基底100的上表面100a。
一封裝層(encapsulant)460可選擇性覆蓋外部導電結構440及一部分的第一基底100，或可更延伸至第一基底100上表面100a上，以於感測區或元件區110上方形成一扁平化接 觸表面。此處僅繪示出封裝層460於感測區或元件區110上方形成扁平化接觸表面的實施例作為範例說明。在本實施例中，封裝層460可由形塑材料(molding material)或密封材料(sealing material)所構成。
一般而言，晶片的感測區或元件區及導電墊通常位於晶片的主動面，若將晶片的外部電性連接路徑形成於主動面上，則需要在主動面上沉積多層膜層(例如，絕緣層)，因而造成主動面上的感測區之敏感度降低。
根據本發明的上述實施例，重佈線層300透過第一基底100內的通孔240而電性連接至導電墊160，並自第一基底100的下表面100b橫向延伸至突出於第一基底100的側壁101。如此一來，第一基底100的外部電性連接路徑係自第一基底100的內部經由第一基底100的下表面100b而延伸至第一基底100的外側，因此能夠避免由於第一基底100的上表面100a上具有過多膜層造成感測區或元件區110之敏感度降低或光線穿透率降低的問題。再者，由於本發明實施例之重佈線層300橫向突出於第一基底100的側壁101，因此用以將導電墊160與外部元件420彼此電性連接的外部導電結構(例如，打線)440可設置於第一基底100的外側，而非第一基底100的上表面100a上，使得外部導電結構440的最高高度可低於上表面100a。如此一來，能夠降低晶片封裝體的整體高度，進而可縮小具有感測功能之電子產品的尺寸。
以下配合第1A至1H圖及第2圖說明本發明一實施例之晶片封裝體的製造方法，其中第1A至1H圖以及第2圖分別 繪示出根據本發明一實施例之晶片封裝體的剖面示意圖及平面示意圖。
請參照第1A圖，提供一第一基底100，其具有一上表面100a及一下表面100b，且包括複數晶片區。為簡化圖式，此處僅繪示出局部的單一晶片區120。在一實施例中，第一基底100可為一矽基底或其他半導體基底。舉例來說，第一基底100可為一矽晶圓，以利於進行晶圓級封裝製程。
在本實施例中，第一基底100的上表面100a上具有一絕緣層140。一般而言，絕緣層140可由層間介電層、金屬間介電層及覆蓋之鈍化層組成。為簡化圖式，此處僅繪示出單層絕緣層140。在本實施例中，絕緣層140可包括無機材料，例如氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合或其他適合的絕緣材料。
在本實施例中，每一晶片區120內的絕緣層140內具有一個或一個以上的導電墊160，鄰近於第一基底100的上表面100a。在一實施例中，導電墊160可為單層導電層或具有多層之導電層結構。為簡化圖式，此處僅以單層導電層作為範例說明。在本實施例中，絕緣層140內包括一個或一個以上的開口180，以露出對應的導電墊160。舉例來說，當導電墊160為具有多層之導電層結構時，開口180可露出多層導電層結構中的頂層導電層。
再者，晶片封裝體還包括一感測區或元件區110，其可鄰近於第一基底100的上表面100a，且可透過內連線結構(未繪示)與導電墊160電性連接。在一實施例中，感測區或元件 區110內可包括一影像感測元件。在另一實施例中，感測區或元件區110可包括指紋辨識感測元件或其他生物特徵感測元件。在其他實施例中，感測區或元件區110可包括一溫度感測元件、一溼度感測元件、一壓力感測元件或其他適合的感測元件。
請參照第1B圖，可透過一黏著層(例如，黏著膠)220，將一暫時性基底200貼附於上表面100a上的絕緣層140上。在本實施例中，暫時性基底200可為玻璃或其他適合的基底材料。接著，以暫時性基底200作為承載基板，自第一基底100的下表面100b進行薄化製程(例如，蝕刻製程、銑削(milling)製程、機械研磨(mechanical grinding)製程或化學機械研磨(chemical mechanical polishing)製程)，以減少第一基底100的厚度。
請參照第1C圖，可透過微影製程及蝕刻製程(例如，乾蝕刻製程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程或其他適合的製程)，在第一基底100的每一晶片區120內形成一個或一個以上的通孔240，對應於導電墊160。通孔240自第一基底100的下表面100b朝上表面100a延伸，且貫穿第一基底100而露出鄰近於導電墊160的絕緣層140。
接著，可透過沉積製程(例如，塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)，在第一基底100的下表面100b上順應性形成一絕緣層260，其延伸至通孔240的側壁及底部。在本實施例中，絕緣層260可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化 物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
請參照第1D圖，可透過微影製程及蝕刻製程(例如，乾蝕刻製程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程或其他適合的製程)，去除通孔240底部上的絕緣層260以及鄰近於導電墊160的絕緣層140，以形成一開口280。開口280露出導電墊160的一部分。舉例來說，當導電墊160為具有多層之導電層結構時，開口280可露出多層導電層結構中的底層導電層。
接著，可透過沉積製程(例如，塗佈製程、物理氣相沉積製程、化學氣相沉積製程、電鍍製程、無電鍍製程或其他適合的製程)、微影製程及蝕刻製程，在絕緣層260上形成圖案化的重佈線層300。
重佈線層300形成於第一基底100的下表面100b，且順應性延伸至通孔240的側壁及底部上，並填滿開口280，因此重佈線層300突出於第一基底100的上表面100a。在其他實施例中，重佈線層300可同時填滿通孔240及開口280。在本實施例中，重佈線層300可透過絕緣層260與第一基底100電性隔離，且可經由通孔240及開口280直接電性接觸或間接電性連接露出的導電墊160。因此，通孔240及開口280內的重佈線層300也稱為矽通孔電極(TSV)。在一實施例中，重佈線層300可包括鋁、銅、金、鉑、鎳、錫、前述之組合、導電高分子材料、導電陶瓷材料(例如，氧化銦錫或氧化銦鋅)或其他適合的導電材 料。
請參照第1E圖，可透過一接合層340，將第二基底320設置於下表面100b的絕緣層260上，以作為永久性的承載基底。在本實施例中，第二基底320可包括玻璃、矽或其他適合作為承載基底的材料。在本實施例中，接合層340填滿通孔240。在其他實施例中，接合層340可部分填入通孔240或完全不填入通孔240。在本實施例中，接合層340可包括黏著膠(glue)、氧化物、氧化物及金屬、聚合物或其他適合的接合材料。在提供第二基底320之後，可移除黏著層220及暫時性基底200。
請參照第1F圖，可透過刻痕(notching)製程、微影及蝕刻製程或其他適合的製程，在每一晶片區120內形成一個或一個以上的側邊凹陷360，其位於導電墊160外側，且貫穿絕緣層140而延伸至第一基底100內。舉例來說，可去除絕緣層140及第一基底100對應於晶片區120以及相鄰晶片區120之間的切割道(未繪示)的部分。
請參照第1G圖，可利用位於上表面100a的絕緣層140作為硬式罩幕層，進行微影製程及蝕刻製程(例如，乾蝕刻製程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程或其他適合的製程)，在每一晶片區120內形成一個或一個以上的側邊凹陷380。在其他實施例中，也可額外形成圖案化光阻層，以進行上述微影製程及蝕刻製程。在本實施例中，側邊凹陷380位於導電墊160外側，且與側邊凹陷360互相連通，並朝下表面100b延伸而貫穿第一基底100，進而露出第一基底100的下表面 100b上的絕緣層260。舉例來說，可去除第一基底100對應於晶片區120以及相鄰晶片區120之間的切割道(未繪示)的部分，使得相鄰晶片區120之間的第一基底100局部或完全分離。
在本實施例中，側邊凹陷380的一側壁構成第一基底100的一側壁101。在一實施例中，側壁101傾斜於第一基底100的上表面100a。在其他實施例中，側壁101可大致上垂直於第一基底100的上表面100a。
在本實施例中，側邊凹陷380的尺寸大於側邊凹陷360的尺寸，使得絕緣層140自第一基底100的上表面100a橫向延伸而突出於第一基底100的側壁101。在本實施例中，第一基底100的下表面100b上的絕緣層260及重佈線層300皆自第一基底100的下表面100b橫向延伸而突出於第一基底100的側壁101。
一般而言，若重佈線層自基底的上表面沿著基底的側壁延伸，則基底需要具有傾斜的側壁，以將重佈線層順利地自上表面沿著側壁形成。然而，由於本發明實施例之重佈線層係自第一基底的內部經由下表面而延伸至橫向突出第一基底的側壁，而並未形成於第一基底的上表面及側壁上，因此不論第一基底的側壁為傾斜或垂直的，皆不會影響重佈線層的形成。再者，雖然位於第一基底的上表面的絕緣層橫向突出第一基底的側壁，然而由於本發明實施例之重佈線層並未形成於第一基底的上表面及側壁上，因此絕緣層的突出部分並不會影響重佈線層的形成，因而無需進行額外的製程將絕緣層的突出部分去除。
接著，可透過微影製程及蝕刻製程(例如，乾蝕刻製程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程或其他適合的製程)，去除突出於側壁101的絕緣層260的一部分，以形成一個或一個以上的開口400，其露出突出於側壁101的重佈線層300的一部分。
請同時參照第1G及2圖，其中第1G圖係繪示出沿著第2圖中的剖線I-I’的剖面示意圖。在本實施例中，側邊凹陷360及側邊凹陷380沿著第一基底100的周圍延伸而橫跨四個側邊的全部長度，進而露出第一基底100的四個側邊下方的絕緣層260。在另一實施例中，側邊凹陷360及側邊凹陷380可僅沿著第一基底100的其中一個側邊的一部份或全部長度橫向延伸。又另一實施例中，側邊凹陷360及側邊凹陷380可橫跨第一基底100的其中一個側邊的全部長度，且更沿著相鄰的另一側邊的一部份或全部長度橫向延伸。在其它實施例中，側邊凹陷360及側邊凹陷380可橫跨第一基底100的其中一個側邊的全部長度，且更沿著相鄰的兩側邊的一部份或全部長度橫向延伸。
在本實施例中，當透過刻痕製程形成側邊凹陷360且透過微影製程及蝕刻製程形成側邊凹陷380時，側邊凹陷360及側邊凹陷380係沿著第一基底100的側邊的全部長度延伸，而當透過微影製程及蝕刻製程形成側邊凹陷360及側邊凹陷380時，側邊凹陷360及側邊凹陷380可沿著第一基底100的側邊的一部份或全部長度延伸。可以理解的是，雖然未繪示於圖式中，只要側邊凹陷沿著第一基底100的至少一個側邊的一部份或全部長度橫向延伸，側邊凹陷的實際數量及位置取決於設計 需求。
再者，如第2圖所示，多個開口180形成於絕緣層140內，以露出對應的導電墊160。通孔240形成於對應的導電墊160下方，而重佈線層300自導電墊160及通孔240下方橫向延伸至絕緣層260下方。為清楚表示，此處以虛線繪示出重佈線層300的輪廓。多個開口400形成於絕緣層260內，以露出對應的重佈線層300。可以理解的是，第2圖所示之部件的數量、形狀及位置係取決於設計需求而不限定於此。
接著，請參照第1H圖，沿著相鄰晶片區120之間的切割道(未繪示)，對絕緣層260及第二基底320進行切割製程，以形成複數獨立的晶片封裝體。
接著，可透過一黏著層(未繪示)，將一外部元件420貼附於獨立的晶片封裝體中的第二基底320-上。在本實施例中，外部元件420可為電路板、晶片或中介層。
接著，可透過打線接合(Wire Bonding)製程，將一個或一個以上的外部導電結構440形成於對應的開口400內，以透過露出的重佈線層300電性連接至對應的導電墊160，並將外部導電結構440延伸至外部元件420上，以將導電墊160與外部元件420電性連接。在其他實施例中，外部導電結構440可設置於絕緣層140的開口180內，而電性連接至對應的導電墊160。可以理解的是，外部導電結構440的實際數量及位置取決於設計需求。雖然未繪示於圖式中，可選擇性將一個以上的外部導電結構440分別設置於開口400及開口180內。在一實施例中，外部導電結構440可由開口400內的接合球及自接合球延伸至 外部元件420的接線所構成。再者，外部導電結構440可包括金或其他適合的導電材料。
在一實施例中，外部導電結構440的最高部分低於第一基底100的上表面100a。在其他實施例中，外部導電結構440的最高部分可突出於第一基底100的上表面100a。
接著，可透過模塑成型(molding)製程或沉積製程(例如，塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)，在外部元件420及獨立的晶片封裝體上形成選擇性的封裝層460，其可覆蓋外部導電結構440及一部分的第一基底100，或可更延伸至第一基底100上表面100a上，以於感測區或元件區110上方形成一扁平化接觸表面。此處僅繪示出封裝層460於感測區或元件區110上方形成扁平化接觸表面的實施例作為範例說明。在本實施例中，封裝層460可由形塑材料或密封材料所構成。
根據本發明的上述實施例，由於在晶片內形成電性連接至導電墊的矽通孔電極，且將矽通孔電極中的重佈線層自晶片的非主動面橫向延伸至突出於晶片的側壁，因此晶片的外部電性連接路徑係自晶片的內部經由晶片的非主動面而延伸至晶片的外側，進而能夠避免由於在主動面上沉積過多膜層造成感測敏感度降低的問題。舉例來說，當晶片封裝體內具有感光元件時，本發明的上述實施例能夠增加感測區或元件區的光線穿透率，進而提升晶片封裝體的感測敏感度。
再者，由於本發明實施例之重佈線層橫向突出於晶片的側壁，因此用以將晶片與外部元件彼此電性連接的外部 導電結構(例如，打線)可形成於晶片的外側，而非晶片的主動面上，使得晶片封裝體的尺寸能夠進一步縮小。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可更動與組合上述各種實施例。
100‧‧‧第一基底
100a‧‧‧上表面
100b‧‧‧下表面
101‧‧‧側壁
110‧‧‧感測區或元件區
140、260‧‧‧絕緣層
160‧‧‧導電墊
180、280、400‧‧‧開口
240‧‧‧通孔
300‧‧‧重佈線層
320‧‧‧第二基底
340‧‧‧接合層
360、380‧‧‧側邊凹陷
420‧‧‧外部元件
440‧‧‧外部導電結構
460‧‧‧封裝層

Claims (24)

  1. 一種晶片封裝體，包括：一第一基底，具有一上表面、一下表面及一側壁，其中一感測區或元件區及一導電墊鄰近於該上表面；一通孔，貫穿該第一基底；以及一重佈線層，自該下表面延伸至該通孔內，且與該導電墊電性連接，其中該重佈線層更自該下表面橫向延伸而突出於該第一基底的該側壁。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該重佈線層更延伸突出於該上表面，以電性連接至該導電墊。
  3. 如申請專利範圍第1項所述之晶片封裝體，更包括一絕緣層，設置於該第一基底與該重佈線層之間，其中該絕緣層自該下表面橫向延伸而突出於該側壁，且其中該絕緣層具有一開口，露出突出於該側壁的該重佈線層。
  4. 如申請專利範圍第3項所述之晶片封裝體，更包括一外部導電結構，設置於該開口內，且電性連接至突出於該側壁的該重佈線層。
  5. 如申請專利範圍第1項所述之晶片封裝體，更包括一絕緣層，其中該導電墊位於該絕緣層內，且其中該絕緣層自該上表面橫向延伸而突出於該側壁。
  6. 如申請專利範圍第1項所述之晶片封裝體，更包括一第二基底，其中透過一接合層將該第一基底的該下表面設置於該第二基底上。
  7. 如申請專利範圍第6項所述之晶片封裝體，其中該接合層 填入該通孔。
  8. 如申請專利範圍第6項所述之晶片封裝體，其中該第二基底內包括特定應用積體電路或訊號處理器。
  9. 如申請專利範圍第1項所述之晶片封裝體，其中該感測區或元件區內包括影像感測元件、生物特徵感測元件或環境特徵感測元件。
  10. 如申請專利範圍第1項所述之晶片封裝體，更包括一側邊凹陷，其中該側邊凹陷的一側壁構成該第一基底的該側壁，且其中該側邊凹陷沿著該第一基底的一側邊的至少一部份長度橫向延伸。
  11. 如申請專利範圍第10項所述之晶片封裝體，其中該側邊凹陷沿著該側邊的全部長度橫向延伸。
  12. 如申請專利範圍第11項所述之晶片封裝體，其中該側邊凹陷更延伸至與該側邊相鄰的至少一另一側邊的至少一部份長度。
  13. 一種晶片封裝體的製造方法，包括：提供一第一基底，其具有一上表面、一下表面及一側壁，其中一感測區或元件區及一導電墊鄰近於該上表面；形成一通孔，貫穿該第一基底；以及形成一重佈線層，自該下表面延伸至該通孔內，且與該導電墊電性連接，其中該重佈線層更自該下表面橫向延伸而突出於該第一基底的該側壁。
  14. 如申請專利範圍第13項所述之晶片封裝體的製造方法，其中該重佈線層更延伸突出於該上表面，以電性連接至該導 電墊。
  15. 如申請專利範圍第13項所述之晶片封裝體的製造方法，更包括在該第一基底與該重佈線層之間形成一絕緣層，其中該絕緣層自該下表面橫向延伸而突出於該側壁，且其中該絕緣層具有一開口，露出突出於該側壁的該重佈線層。
  16. 如申請專利範圍第15項所述之晶片封裝體的製造方法，更包括在該開口內形成一外部導電結構，並電性連接至突出於該側壁的該重佈線層。
  17. 如申請專利範圍第13項所述之晶片封裝體的製造方法，其中該導電墊位於一絕緣層內，且其中該絕緣層自該上表面橫向延伸而突出於該側壁。
  18. 如申請專利範圍第13項所述之晶片封裝體的製造方法，更包括透過一接合層，將該第一基底的該下表面設置於一第二基底上。
  19. 如申請專利範圍第18項所述之晶片封裝體的製造方法，其中該接合層填入該通孔。
  20. 如申請專利範圍第18項所述之晶片封裝體的製造方法，其中該第二基底內包括特定應用積體電路或訊號處理器。
  21. 如申請專利範圍第13項所述之晶片封裝體的製造方法，其中該感測區或元件區內包括影像感測元件、生物特徵感測元件或環境特徵感測元件。
  22. 如申請專利範圍第13項所述之晶片封裝體的製造方法，更包括形成一側邊凹陷，其中該側邊凹陷的一側壁構成該第一基底的該側壁，且其中該側邊凹陷沿著該第一基底的一 側邊的至少一部份長度橫向延伸。
  23. 如申請專利範圍第22項所述之晶片封裝體的製造方法，其中該側邊凹陷沿著該側邊的全部長度橫向延伸。
  24. 如申請專利範圍第23項所述之晶片封裝體的製造方法，其中該側邊凹陷更延伸至與該側邊相鄰的至少一另一側邊的至少一部份長度。
TW104131558A 2014-10-07 2015-09-24 晶片封裝體及其製造方法 TWI593069B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201462060984P 2014-10-07 2014-10-07

Publications (2)

Publication Number Publication Date
TW201631720A TW201631720A (zh) 2016-09-01
TWI593069B true TWI593069B (zh) 2017-07-21

Family

ID=55633311

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104131558A TWI593069B (zh) 2014-10-07 2015-09-24 晶片封裝體及其製造方法

Country Status (3)

Country Link
US (1) US9865526B2 (zh)
CN (1) CN105489659B (zh)
TW (1) TWI593069B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9484373B1 (en) * 2015-11-18 2016-11-01 Omnivision Technologies, Inc. Hard mask as contact etch stop layer in image sensors
CN106293239B (zh) * 2016-08-16 2017-11-24 广东欧珀移动通信有限公司 输入组件的制造方法、输入组件及终端
US11251138B2 (en) * 2018-12-21 2022-02-15 Texas Instruments Incorporated Through wafer trench isolation between transistors in an integrated circuit
US20230069311A1 (en) * 2021-08-27 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method of package containing chip structure with inclined sidewalls

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8367477B2 (en) * 2009-03-13 2013-02-05 Wen-Cheng Chien Electronic device package and method for forming the same
JP5355504B2 (ja) * 2009-07-30 2013-11-27 株式会社東芝 半導体装置の製造方法および半導体装置
US8890268B2 (en) 2010-02-26 2014-11-18 Yu-Lung Huang Chip package and fabrication method thereof
US8952501B2 (en) * 2010-05-11 2015-02-10 Xintec, Inc. Chip package and method for forming the same
KR20130027628A (ko) * 2011-06-27 2013-03-18 삼성전자주식회사 적층형 반도체 장치

Also Published As

Publication number Publication date
US20160099195A1 (en) 2016-04-07
TW201631720A (zh) 2016-09-01
CN105489659B (zh) 2017-07-25
US9865526B2 (en) 2018-01-09
CN105489659A (zh) 2016-04-13

Similar Documents

Publication Publication Date Title
TWI629759B (zh) 晶片封裝體及其製造方法
TWI597813B (zh) 晶片封裝體及其製造方法
US10157811B2 (en) Chip package and method for forming the same
TWI596722B (zh) 晶片堆疊封裝體及其製造方法
TWI512930B (zh) 晶片封裝體及其形成方法
US9761510B2 (en) Chip package and method for forming the same
US9425134B2 (en) Chip package
US9437478B2 (en) Chip package and method for forming the same
TWI619211B (zh) 晶片封裝體及其製造方法
TWI575779B (zh) 晶片封裝體及其製造方法
US20140332983A1 (en) Stacked chip package and method for forming the same
US9633935B2 (en) Stacked chip package including substrate with recess adjoining side edge of substrate and method for forming the same
TW201543641A (zh) 晶片封裝體及其製造方法
US20150228557A1 (en) Chip package and method for forming the same
TWI611528B (zh) 晶片模組及其製造方法
US20150284244A1 (en) Method for forming chip package
TW201715662A (zh) 晶片封裝體及其製造方法
TWI593069B (zh) 晶片封裝體及其製造方法
TWI595618B (zh) 感測模組及其製造方法
TWI632665B (zh) 晶片封裝體之製造方法
US9601460B2 (en) Chip package including recess in side edge
US20150325551A1 (en) Chip package and method for forming the same