TWI619211B - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

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TWI619211B
TWI619211B TW105138211A TW105138211A TWI619211B TW I619211 B TWI619211 B TW I619211B TW 105138211 A TW105138211 A TW 105138211A TW 105138211 A TW105138211 A TW 105138211A TW I619211 B TWI619211 B TW I619211B
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chip package
hard coating
conductive
coating layer
item
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TW105138211A
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TW201729365A (zh
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劉建宏
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精材科技股份有限公司
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Abstract

本揭露提供一種晶片封裝體的製造方法，包括提供一裝置基底，其包括一感測裝置及露出於裝置基底的一表面的複數個導電墊。上述方法更包括於每一導電墊上對應形成一導電結構，接著於裝置基底的表面上覆蓋一硬塗層，且完全覆蓋位於每一導電墊上的導電結構。上述方法更包括對硬塗層進行薄化，以露出位於每一導電墊上的導電結構。硬塗層及位於每一導電墊上的導電結構具有實質上平坦且彼此切齊的表面。本揭露也提供一種晶片封裝體。

Description

晶片封裝體及其製造方法
本發明係有關於一種晶片封裝技術，特別為有關於一種晶片封裝體及其製造方法。
隨著電子或光電產品諸如數位相機、具有影像拍攝功能的手機、條碼掃瞄器(bar code reader)以及監視器需求的增加，半導體技術發展的相當快速，且半導體晶片的尺寸有微縮化(miniaturization)的趨勢，而其功能也變得更為複雜。
大多數的半導體晶片通常為了效能上的需求而置放於一密封的封裝體，其有助於操作上的穩定性。因此，晶片封裝製程是製造電子產品過程中之重要步驟。晶片封裝體除了將晶片保護於其中，使其免受外界環境污染外，還提供晶片內部電子元件與外界之電性連接通路。然而，由於電子或光電產品的功能複雜化，因此增加封裝體的製造困難度及/或可靠度。
第1圖係繪示出一晶片封裝體10的剖面示意圖。晶片封裝體10的製作包括將一晶片100(例如，一感測晶片)裝設於一封裝基底200上。接著，進行打線製程，以將接線102電性連接於晶片100導電墊100a與封裝基底200的導電墊200a之間。之後，進行模塑製程以形成封裝層104，其密封封裝基底200、接線102及部分的晶片100而露出晶片100的感測區。最後，利用 噴塗製程在封裝層104的表面及晶片100的感測區上形成一硬塗層106，以保護晶片100的感測區。
然而，由於封裝層104與晶片100之間形成高度落差(step height)，且硬塗層106的材料在固化以前具有流動性，因而造成硬塗層106的厚度不均而影響晶片封裝體10的裝置效能及可靠度。
因此，有必要尋求一種新穎的晶片封裝體及其製造方法，其能夠解決或改善上述的問題。
本揭露的實施例係提供一種晶片封裝體的製造方法，包括：提供一裝置基底，其包括一感測裝置及露出於裝置基底的一表面的複數個導電墊；於每一導電墊上對應形成一導電結構；於裝置基底的表面上覆蓋一硬塗層，且完全覆蓋位於每一導電墊上的導電結構；以及對硬塗層進行薄化，以露出位於每一導電墊上的導電結構，且使硬塗層及位於每一導電墊上的導電結構具有實質上平坦且彼此切齊的表面。
本揭露的另一實施例係提供一種晶片封裝體，包括：一裝置基底，包括一感測裝置及露出於裝置基底的一表面的複數個導電墊；一硬塗層，覆蓋裝置基底的表面，且具有複數個開口分別露出導電墊；以及複數個導電結構，對應設置於開口內而電性連接至導電墊，其中硬塗層及導電結構具有實質上平坦且彼此切齊的表面。
10、20、30‧‧‧晶片封裝體
100‧‧‧晶片
100a、200a、304、400a‧‧‧導電墊
102、310‧‧‧接線
104、312‧‧‧封裝層
106、308‧‧‧硬塗層
200‧‧‧封裝基底
300‧‧‧本體
301‧‧‧感測裝置
302‧‧‧金屬化層
303‧‧‧裝置基底
306‧‧‧光阻圖案層
306a‧‧‧開口
307‧‧‧導電結構
400‧‧‧封裝基底
第1圖係繪示出一晶片封裝體的剖面示意圖。
第2A至2C圖係繪示出本揭露一實施例之晶片封裝體的不同中間製造階段的剖面示意圖。
第3A至3D圖係繪示出本揭露另一實施例之晶片封裝體的不同中間製造階段的剖面示意圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝微機電系統晶片。然其應用不限於此，例如在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System,MEMS)、生物辨識元件(biometric device)、微流體系統(micro fluidic systems)、或利用熱、光線、電容及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package,WSP)製程對影像感測元件、發光二極體(light-emitting diodes,LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、指紋辨識元件(fingerprint-recognition device)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)或系統級封裝(System in Package,SIP)之晶片封裝體。
請參照第2C圖，其繪示出根據本揭露一實施例之晶片封裝體20的剖面示意圖。在本實施例中，晶片封裝體20包括一裝置基底303。在本實施例中，裝置基底303可包括一本體300以及形成於本體300上的一金屬化層302。在一實施例中，本體300可包括矽本體或其他半導體本體。再者，金屬化層302可包括一介電材料層及位於介電材料層內的內連接結構(未繪示)。
在本實施例中，裝置基底303的本體300內具有一 感測裝置301，其鄰近於金屬化層302的下表面。在一實施例中，感測裝置301用以感測生物特徵，且可包括一指紋辨識元件。在其他實施例中，感測裝置301用以感測環境特徵，且可包括一電容感測元件或其他適合的感測元件。
再者，裝置基底303的金屬化層302內具有一個或一個以上的導電墊304。通常位於金屬化層302內的導電墊304可為一頂部金屬層且露出於裝置基底300的一表面(例如，金屬化層302的上表面)。在一實施例中，感測裝置301內的感測元件可透過金屬化層302內的內連接結構而與導電墊304電性連接。
在一實施例中，導電墊304可為單層導電層或具有多層之導電層結構。為簡化圖式，此處僅以單層導電層作為範例說明(如第2C圖所示)，且僅繪示出位於裝置基底303內的兩個導電墊304作為範例說明。
在本實施例中，晶片封裝體20更包括一硬塗層308設置於裝置基底303的表面上，且位於感測裝置301正上方。硬塗層308作為感測裝置301的保護層並露出裝置基底303的導電墊304。在一實施例中，硬塗層308可包括一高硬度材料，且其硬度(即，摩氏(mohs)硬度)值不小於6。再者，硬塗層308可包括一高介電常數材料，且其介電常數為5以上。舉例來說，硬塗層308可包括二甲基乙醯胺(dimethylacetamide,DMAC)、鈦酸鍶、二氧化鈦或其他適合的高介電常數絕緣保護材料。
請參照第2A至2C圖，其繪示出根據本揭露一實施例之晶片封裝體20的不同中間製造階段的剖面示意圖。如第2A 圖所示，提供一裝置基底303，其包括一本體300以及形成於本體300上的金屬化層302。在一實施例中，本體300可包括矽本體或其他半導體本體。再者，金屬化層302可包括一介電材料層及位於介電材料層內的內連接結構(未繪示)。在一實施例中，裝置基底303為一晶片。在另一實施例中，裝置基底303為一晶圓，以利於進行晶圓級封裝製程。在本實施例中，裝置基底303包括複數晶片區。為簡化圖式及說明，此處僅繪示出單一晶片區中的裝置基底303。
在本實施例中，晶片區中的裝置基底303內具有一感測裝置301及一個或一個以上的導電墊304。通常感測裝置301位於本體300內且鄰近於金屬化層302的下表面。再者，導電墊304通常位於金屬化層302內且可為一頂部金屬層而鄰近於金屬化層302的上表面。在一實施例中，感測裝置301內的感測元件(例如，一指紋辨識元件)可透過裝置基底303內的內連線結構而與導電墊304電性連接。在一實施例中，導電墊304可為單層導電層或具有多層之導電層結構。為簡化圖式，此處僅以單層導電層作為範例說明，且僅繪示出裝置基底303內的兩個導電墊304作為範例說明。
接著，在裝置基底303的表面上覆蓋一光阻材料層(未繪示)。之後，藉由光學微影製程來圖案化光阻材料層，以形成光阻圖案層306。在本實施例中，光阻圖案層306具有一開口306a露出裝置基底303的表面且對應於裝置基底303的感測裝置301。在本實施例中，光阻圖案層306係用於後續進行硬塗層(其不易被蝕刻)圖案化。
請參照第2B圖，在光阻圖案層306上形成一硬塗層308並完全填滿光阻圖案層306的開口306a。光阻圖案層306上方的硬塗層308的厚度約在5至30微米(μm)範圍。在一實施例中，硬塗層308可包括一高硬度材料，且其硬度值(即，摩氏硬度)不小於6。再者，硬塗層308可包括一高介電常數材料，且其介電常數為5以上。舉例來說，硬塗層308可包括二甲基乙醯胺(dimethylacetamide,DMAC)、鈦酸鍶、二氧化鈦或其他適合的高介電常數絕緣保護材料。
請參照第2C圖，如先前所述，由於硬塗層308不易被蝕刻，因此利用光阻圖案層306作為犧牲材料進行一掀離(lift-off)製程，以將位於光阻圖案層306上方的硬塗層308的部分移除。舉例來說，利用氧電漿在硬塗層308內形成穿孔(未繪示)而露出位於硬塗層308下方的光阻圖案層306。接著，利用濕式蝕刻經由上述孔洞去除光阻圖案層306，使光阻圖案層306上方的硬塗層308的部分也同時被移除，而留下位於感測裝置301上方的硬塗層308的部分。餘留的硬塗層308係用以作為位於下方的感測裝置301的保護層。
相較於第1圖所示的晶片封裝體10，晶片封裝體20的保護層(即，硬塗層308)是在進行打線製程及模塑製程之前利用掀離製程製作而成，因此形成的硬塗層308的厚度具有較佳的均勻性，進而維持或改善晶片封裝體20的裝置效能及可靠度。
請參照第3D圖，其繪示出根據本揭露另一實施例之晶片封裝體30的剖面示意圖，其中相同於前述第2C圖的實施 例的部件係使用相同的標號並省略其說明。在本實施例中，晶片封裝體30包括一裝置基底303。如先前第2C圖的實施例所述，裝置基底303可包括一本體300以及形成於本體300上的一金屬化層302。裝置基底303的本體300內具有一感測裝置301，其鄰近於金屬化層302的下表面，且可包括一指紋辨識元件。 裝置基底303的金屬化層302內具有一個或一個以上的導電墊304，其露出於裝置基底300的一表面，且可透過金屬化層302內的內連接結構(未繪示)而與感測裝置301內的感測元件電性連接。
在一實施例中，導電墊304可為單層導電層或具有多層之導電層結構。為簡化圖式，此處僅以位於裝置基底303內的兩個單層導電墊304作為範例說明(如第3D圖所示)。
在本實施例中，晶片封裝體30更包括一硬塗層308覆蓋裝置基底303的表面。不同於第2C圖的實施例，硬塗層308內具有複數個開口對應於導電墊304且露出導電墊304。如先前第2C圖的實施例所述，硬塗層308可包括一高硬度材料，且其硬度值不小於6。再者，硬塗層308可包括一高介電常數材料，且其介電常數為5以上。舉例來說，硬塗層308可包括二甲基乙醯胺(dimethylacetamide,DMAC)、鈦酸鍶、二氧化鈦或其他適合的高介電常數絕緣保護材料。
在本實施例中，晶片封裝體30更包括複數個導電結構307，對應設置於硬塗層308的開口內而與導電墊304形成電性連接。再者，硬塗層308及導電結構307具有實質上平坦且彼此切齊的表面。舉例來說，硬塗層308的上表面與導電結構307的上表面為共平面，而硬塗層308的下表面與導電結構307 的下表面也可為共平面。在一實施例中，導電結構307包括金屬凸塊或金屬柱體。再者，導電結構307可包括金、銀、錫、銅或其合金。
在本實施例中，晶片封裝體30更包括一封裝基底400，具有導電墊400a位於其上。裝置基底303裝設於封裝基底400上。在本實施例中，晶片封裝體30更包括一封裝層312及埋設於封裝層312內的複數個接線310。封裝層312設置於封裝基底400上，以密封硬塗層308及裝置基底303。封裝層312包括一開口，使對應於感測裝置301的硬塗層308的部分露出於封裝層312。在本實施例中，封裝層312可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯(butylcyclobutene,BCB)、聚對二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物、或丙烯酸酯(acrylates))、或其他適合的絕緣材料。
請參照第3A至3D圖，其繪示出根據本揭露另一實施例之晶片封裝體30的不同中間製造階段的剖面示意圖，其中相同於前述第2A至2C圖的實施例的部件係使用相同的標號並省略其說明。如第3A圖所示，提供一裝置基底303，其包括一本體300以及形成於本體300上的金屬化層302。在一實施例中，裝置基底303為一晶片。在另一實施例中，裝置基底303為一晶圓，以利於進行晶圓級封裝製程。在本實施例中，裝置基底303包括複數晶片區。為簡化圖式及說明，此處僅繪示出單一晶片區中的裝置基底303。
在本實施例中，晶片區中的裝置基底303的本體300內具有一感測裝置301，其鄰近於金屬化層302的下表面，且可包括一指紋辨識元件。裝置基底303的金屬化層302內具有一個或一個以上的導電墊304，其露出於裝置基底300的一表面，且可透過金屬化層302內的內連接結構(未繪示)而，與感測裝置301內的感測元件電性連接。為簡化圖式，此處僅繪示出裝置基底303內的兩個單層導電墊304作為範例說明。
接著，於每一導電墊304上對應形成一導電結構307，以作為導電墊304的延伸部或導電通道。在一實施例中，導電結構307可包括金屬凸塊或金屬柱體。再者，導電結構307可包括金、銀、錫、銅或其合金。在一實施例中，可藉由植球(ball bumping)製程形成導電結構307。在其他實施例中，也可利用電鍍製程、濺鍍製程或其他適合的沉積製程形成導電結構307。
請參照第3B圖，於裝置基底300的表面上覆蓋一硬塗層308，且完全覆蓋位於每一導電墊304上的導電結構307。亦即，導電結構307完全埋入硬塗層308內而未露出於硬塗層308的表面。在一實施例中，可藉由印刷、塗佈製程形成硬塗層308。如先前所述，硬塗層308可包括一高硬度材料，且其硬度值不小於6。再者，硬塗層308可包括一高介電常數材料，且其介電常數為5以上。舉例來說，硬塗層308可包括二甲基乙醯胺(dimethylacetamide,DMAC)、鈦酸鍶、二氧化鈦或其他適合的高介電常數絕緣保護材料。
請參照第3C圖，對硬塗層308進行薄化或平坦化製 程，以露出位於每一導電墊304上的導電結構307。舉例來說，薄化製程可包括化學機械研磨(chemical mechanical polishing,CMP)製程、機械研磨(mechanical grinding)製程或其他適合的平坦化製程。在進行薄化製程之後，硬塗層308及導電結構307具有實質上平坦且彼此切齊的表面。舉例來說，硬塗層308的上表面與導電結構307的上表面為共平面。
請參照第3D圖，提供一封裝基底400，其具有導電墊400a。第3C圖的結構裝設於封裝基底400上。接著，進行打線接合製程，使複數個接線310電性連接於硬塗層308內的導電結構307與封裝基底400的導電墊400a之間。之後，進行一模塑製程，以在封裝基底400上形成一封裝層312，其密封硬塗層308、裝置基底303及接線310。封裝層312包括一開口，使對應於感測裝置301的硬塗層308的部分露出於封裝層312。
根據第3A至3D圖的實施例，由於晶片封裝體30的保護層(即，硬塗層308)是在進行打線製程及模塑製程之前利用平坦化製程製作而成，因此相較於第1圖所示的晶片封裝體10，硬塗層308的厚度具有較佳的均勻性，進而維持或改善晶片封裝體20的裝置效能及可靠度。再者，如以上所述，由於硬塗層308係利用平坦化製程製作而成，因此無需使用任何光學微影製程及掀離製程。相較於第2圖所示的晶片封裝體20的製作，可進一步簡化製程及降低製造成本。再者，由於硬塗層308與導電結構307為實質上共平面，因此有助於後續對晶片封裝體30進行打線製程及模塑製程。
雖然本發明已以較佳實施例揭露如上，然其並非 用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可更動與組合上述各種實施例。
30‧‧‧晶片封裝體
300‧‧‧本體
301‧‧‧感測裝置
302‧‧‧金屬化層
303‧‧‧裝置基底
304、400a‧‧‧導電墊
307‧‧‧導電結構
308‧‧‧硬塗層
310‧‧‧接線
312‧‧‧封裝層
400‧‧‧封裝基底

Claims (17)

  1. 一種晶片封裝體，包括：一裝置基底，其包括一感測裝置及露出於該裝置基底的一表面的複數個導電墊；一硬塗層，覆蓋該裝置基底的該表面，且具有複數個開口分別露出該等導電墊；複數個導電結構，對應設置於該等開口內而電性連接至該等導電墊，其中該硬塗層及該等導電結構具有實質上平坦且彼此切齊的表面；一封裝基底，裝設於該裝置基底下方；一封裝層，設置於該封裝基底上，以密封該硬塗層及該裝置基底，其中對應於該感測裝置的該硬塗層的部分露出於該封裝層；以及複數個接線，埋設於該封裝層內且電性連接於該等導電結構與該封裝基底之間。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該感測裝置包括一指紋辨識元件。
  3. 如申請專利範圍第1項所述之晶片封裝體，其中該硬塗層包括一高硬度材料，且其硬度值不小於6。
  4. 如申請專利範圍第1項所述之晶片封裝體，其中該硬塗層包括一高介電常數材料，且其介電常數為5以上。
  5. 如申請專利範圍第1項所述之晶片封裝體，其中該硬塗層包括二甲基乙醯胺。
  6. 如申請專利範圍第1項所述之晶片封裝體，其中該等導電 結構包括金屬凸塊或金屬柱體。
  7. 如申請專利範圍第6項所述之晶片封裝體，該等導電結構包括金、銀、錫、銅或其合金。
  8. 一種晶片封裝體的製造方法，包括：提供一裝置基底，其包括一感測裝置及露出於該裝置基底的一表面的複數個導電墊；於每一該等導電墊上對應形成一導電結構；於該裝置基底的該表面上覆蓋一硬塗層，且完全覆蓋位於每一該等導電墊上的該導電結構；對該硬塗層進行薄化，以露出位於每一該等導電墊上的該導電結構，且使該硬塗層及位於每一該等導電墊上的該導電結構具有實質上平坦且彼此切齊的表面；裝設該裝置基底於一封裝基底上方；形成複數個接線，使該等接線電性連接於該等導電結構與該封裝基底之間；以及形成一封裝層於該封裝基底上，以密封該硬塗層、該裝置基底及該等接線，其中對應於該感測裝置的該硬塗層的部分露出於該封裝層。
  9. 如申請專利範圍第8項所述之晶片封裝體的製造方法，其中該感測裝置包括一指紋辨識元件。
  10. 如申請專利範圍第7項所述之晶片封裝體的製造方法，其中該硬塗層包括一高硬度材料，且其硬度值不小於6。
  11. 如申請專利範圍第7項所述之晶片封裝體的製造方法，其中該硬塗層包括一高介電常數材料，且其介電常數為5以 上。
  12. 如申請專利範圍第7項所述之晶片封裝體的製造方法，其中該硬塗層包括二甲基乙醯胺。
  13. 如申請專利範圍第7項所述之晶片封裝體的製造方法，其中該等導電結構包括金屬凸塊或金屬柱體。
  14. 如申請專利範圍第13項所述之晶片封裝體的製造方法，該等導電結構包括金、銀、錫、銅或其合金。
  15. 如申請專利範圍第8項所述之晶片封裝體的製造方法，其中利用植球製程形成該等導電結構。
  16. 如申請專利範圍第8項所述之晶片封裝體的製造方法，其中利用電鍍製程形成該等導電結構。
  17. 如申請專利範圍第8項所述之晶片封裝體的製造方法，其中對該硬塗層進行薄化的步驟包括實施化學機械研磨。
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