CN105489659A - 晶片封装体及其制造方法 - Google Patents

晶片封装体及其制造方法 Download PDF

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Publication number
CN105489659A
CN105489659A CN201510641258.4A CN201510641258A CN105489659A CN 105489659 A CN105489659 A CN 105489659A CN 201510641258 A CN201510641258 A CN 201510641258A CN 105489659 A CN105489659 A CN 105489659A
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China
Prior art keywords
substrate
layer
wafer encapsulation
sidewall
insulating barrier
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CN201510641258.4A
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CN105489659B (zh
Inventor
黃玉龙
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XinTec Inc
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XinTec Inc
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    • H01L31/02019—Circuit arrangements of general character for the devices for devices characterised by at least one potential jump barrier or surface barrier
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Abstract

本发明揭露一种晶片封装体及其制造方法，该晶片封装体包括：一第一基底，具有一上表面、一下表面及一侧壁，其中一感测区或元件区及一导电垫邻近于上表面；一通孔，贯穿第一基底；以及一重布线层，自下表面延伸至通孔内，且与导电垫电性连接，其中重布线层还自下表面横向延伸而突出于第一基底的侧壁。本发明不仅能够提升晶片封装体的感测敏感度，还可缩小晶片封装体的尺寸。

Description

晶片封装体及其制造方法
技术领域
本发明有关于一种晶片封装技术，特别为有关于一种晶片封装体及其制造方法。
背景技术
晶片封装制程是形成电子产品过程中的重要步骤。晶片封装体除了将晶片保护于其中，使其免受外界环境污染外，还提供晶片内部电子元件与外界的电性连接通路。
具有感测功能的晶片封装体通常通过在晶片的上表面形成导电层作为信号接垫的外部电性连接路径，并通过打线将导电层电性连接至电路板。
然而，上述制造方法通常在晶片的感测区上方沉积了多层膜层(例如，绝缘层)，造成感测区的敏感度降低。再者，上述晶片封装体的整体高度也受限于打线高度，导致具有感测功能的电子产品的尺寸难以进一步缩小。
因此，有必要寻求一种新颖的晶片封装体及其制造方法，其能够解决或改善上述的问题。
发明内容
本发明提供一种晶片封装体，包括：一第一基底，具有一上表面、一下表面及一侧壁，其中一感测区或元件区及一导电垫邻近于上表面；一通孔，贯穿第一基底；以及一重布线层，自下表面延伸至通孔内，且与导电垫电性连接，其中重布线层还自下表面横向延伸而突出于第一基底的侧壁。
本发明提供一种晶片封装体的制造方法，包括：提供一第一基底，第一基底具有一上表面、一下表面及一侧壁，其中一感测区或元件区及一导电垫邻近于上表面；形成一通孔，通孔贯穿第一基底；以及形成一重布线层，重布线层自下表面延伸至通孔内，且与导电垫电性连接，其中重布线层还自下表面横向延伸而突出于第一基底的侧壁。
本发明不仅能够提升晶片封装体的感测敏感度，还可缩小晶片封装体的尺寸。
附图说明
图1A至1H是绘示出根据本发明一实施例的晶片封装体的制造方法的剖面示意图。
图2是绘示出根据本发明一实施例的晶片封装体的平面示意图。
其中，附图中符号的简单说明如下：
100第一基底
100a上表面
100b下表面
101侧壁
110感测区或元件区
120晶片区
140、260绝缘层
160导电垫
180、280、400开口
200暂时性基底
220粘着层
240通孔
300重布线层
320第二基底
340接合层
360、380侧边凹陷
420外部元件
440外部导电结构
460封装层。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然而应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关联性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装微机电系统晶片。然其应用不限于此，例如在本发明的晶片封装体的实施例中，其可应用于各种包含有源元件或无源元件(activeorpassiveelements)、数字电路或模拟电路(digitaloranalogcircuits)等集成电路的电子元件(electroniccomponents)，例如是有关于光电元件(optoelectronicdevices)、微机电系统(MicroElectroMechanicalSystem，MEMS)、微流体系统(microfluidicsystems)、或利用热、光线、电容及压力等物理量变化来测量的物理感测器(PhysicalSensor)。特别是可选择使用晶圆级封装(waferscalepackage，WSP)制程对影像感测元件、发光二极管(light-emittingdiodes，LEDs)、太阳能电池(solarcells)、射频元件(RFcircuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(microactuators)、表面声波元件(surfaceacousticwavedevices)、压力感测器(processsensors)或喷墨头(inkprinterheads)等半导体晶片进行封装。
其中上述晶圆级封装制程主要指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于通过堆叠(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layerintegratedcircuitdevices)的晶片封装体。
请参照图1H，其绘示出根据本发明一实施例的晶片封装体的剖面示意图。在本实施例中，晶片封装体包括一第一基底100、一通孔240及一重布线层(redistributionlayer，RDL)300。第一基底100具有一上表面100a及一下表面100b，且具有一侧壁101。在一实施例中，第一基底100可为一硅基底或其他半导体基底。
一绝缘层140设置于第一基底100的上表面100a上。一般而言，绝缘层140可由层间介电层(interlayerdielectric，ILD)、金属间介电层(inter-metaldielectric，IMD)及覆盖的钝化层(passivation)组成。为简化图式，此处仅绘示出单层绝缘层140。在本实施例中，绝缘层140可包括无机材料，例如氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合或其他适合的绝缘材料。
在本实施例中，绝缘层140内具有一个或一个以上的导电垫160，邻近于第一基底100的上表面100a。在一实施例中，导电垫160可为单层导电层或具有多层的导电层结构。为简化图式，此处仅以单层导电层作为范例说明，并以绝缘层140内的一个导电垫160作为范例说明。在本实施例中，绝缘层140内包括一个或一个以上的开口180，以露出对应的导电垫160。举例来说，当导电垫160为具有多层的导电层结构时，开口180可露出多层导电层结构中的顶层导电层。
在本实施例中，晶片封装体包括一感测区或元件区110，其可邻近于第一基底100的上表面100a，且可通过内连线结构(未绘示)与导电垫160电性连接。在一实施例中，感测区或元件区110内可包括一影像感测元件。在另一实施例中，感测区或元件区110可用以感测生物特征。举例来说，感测区或元件区110内可包括指纹辨识感测元件或其他生物特征感测元件。在其他实施例中，感测区或元件区110可用以感测环境特征，例如感测区或元件区110内可包括一温度感测元件、一湿度感测元件、一压力感测元件或其他适合的感测元件。
一个或一个以上的通孔240对应于导电垫160，自第一基底100的下表面100b朝上表面100a延伸，且贯穿第一基底100而露出邻近于导电垫160的绝缘层140。
一绝缘层260设置于第一基底100的下表面100b，且延伸至通孔240的侧壁及底部。在本实施例中，绝缘层260可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
一开口280贯穿通孔240底部上的绝缘层260，且延伸至绝缘层140内，以露出导电垫160的一部分。举例来说，当导电垫160为具有多层的导电层结构时，开口280可露出多层导电层结构中的底层导电层。在某些实施例中，开口180与开口280位于导电垫160的相对两侧。
图案化的重布线层300设置于第一基底100的下表面100b，且顺应性延伸至通孔240的侧壁及底部上，并填满开口280，因此重布线层300突出于第一基底100的上表面100a。在其他实施例中，重布线层300可同时填满通孔240及开口280。重布线层300可通过绝缘层260与第一基底100电性隔离，且可经由通孔240及开口280直接电性接触或间接电性连接露出的导电垫160。因此，通孔240及开口280内的重布线层300也称为硅通孔电极(throughsiliconvia，TSV)。在一实施例中，重布线层300可包括铝、铜、金、铂、镍、锡、前述的组合、导电高分子材料、导电陶瓷材料(例如，氧化铟锡或氧化铟锌)或其他适合的导电材料。
在本实施例中，晶片封装体还包括互相连通的一侧边凹陷360及一侧边凹陷380，位于导电垫160外侧。侧边凹陷360贯穿绝缘层140，且侧边凹陷380自侧边凹陷360的底部朝下表面100b延伸而贯穿第一基底100，进而露出第一基底100的下表面100b上的绝缘层260。在本实施例中，侧边凹陷380的一侧壁构成第一基底100的侧壁101。在一实施例中，侧壁101倾斜于第一基底100的上表面100a。在其他实施例中，侧壁101可大致上垂直于第一基底100的上表面100a。
在本实施例中，侧边凹陷380的尺寸大于侧边凹陷360的尺寸，使得绝缘层140自第一基底100的上表面100a横向延伸而突出于第一基底100的侧壁101。在本实施例中，第一基底100的下表面100b上的绝缘层260及重布线层300皆自第一基底100的下表面100b横向延伸而突出于第一基底100的侧壁101。再者，绝缘层260具有一个或一个以上的开口400，对应地露出突出于侧壁101的重布线层300。
另外，请同时参照图1H及图2，其分别绘示出根据本发明一实施例的晶片封装体的剖面示意图及平面示意图。在本实施例中，侧边凹陷360及侧边凹陷380沿着第一基底100的周围延伸而横跨第一基底100的四个侧边的全部长度，进而露出第一基底100的四个侧边下方的绝缘层260。在另一实施例中，侧边凹陷360及侧边凹陷380可仅沿着第一基底100的其中一个侧边的一部分或全部长度横向延伸。又另一实施例中，侧边凹陷360及侧边凹陷380可横跨第一基底100的其中一个侧边的全部长度，且还沿着相邻的另一侧边的一部分或全部长度横向延伸。在其它实施例中，侧边凹陷360及侧边凹陷380可横跨第一基底100的其中一个侧边的全部长度，且还沿着相邻的两侧边的一部分或全部长度横向延伸。可以理解的是，虽然未绘示于图式中，只要侧边凹陷沿着第一基底100的至少一个侧边的一部分或全部长度横向延伸，侧边凹陷的实际数量及位置取决于设计需求。
再者，如图2所示，绝缘层140具有多个开口180，露出对应的导电垫160。通孔240位于对应的导电垫160下方，而重布线层300自导电垫160及通孔240下方横向延伸至绝缘层260下方。为清楚表示，此处以虚线绘示出重布线层300的轮廓。绝缘层260具有多个开口400，露出对应的重布线层300。可以理解的是，图2所示的部件的数量、形状及位置取决于设计需求而不限定于此。
第二基底320可通过一接合层340设置于下表面100b的绝缘层260上。在本实施例中，第二基底320可包括玻璃、硅或其他适合作为承载基底的材料。在某些实施例中，第二基底320内可包括特定应用集成电路(application-specificintegratedcircuit，ASIC)、信号处理器(signalprocessor)或其他电子部件。在本实施例中，接合层340填满通孔240。在其他实施例中，接合层340可部分填入通孔240或完全不填入通孔240。在本实施例中，接合层340可包括粘着胶(glue)、氧化物、氧化物及金属、聚合物或其他适合的接合材料。
一外部元件420可通过一粘着层(未绘示)贴附于第二基底320。在本实施例中，外部元件420可为电路板、晶片或中介层(interposer)。
一个或一个以上的外部导电结构440设置于对应的开口400内，以通过露出的重布线层300电性连接至对应的导电垫160。再者，外部导电结构440延伸至外部元件420上，以将导电垫160与外部元件420电性连接。在其他实施例中，外部导电结构440可设置于绝缘层140的开口180内，而电性连接至对应的导电垫160。可以理解的是，外部导电结构440的实际数量及位置取决于设计需求。虽然未绘示于图式中，可选择性将一个以上的外部导电结构440分别设置于开口400及开口180内。在一实施例中，外部导电结构440可由开口400内的接合球(bondingball)及自接合球延伸至外部元件420的接线(wire)所构成。再者，外部导电结构440可包括金或其他适合的导电材料。
在一实施例中，外部导电结构440的最高部分低于第一基底100的上表面100a。在其他实施例中，外部导电结构440的最高部分可突出于第一基底100的上表面100a。
一封装层(encapsulant)460可选择性覆盖外部导电结构440及一部分的第一基底100，或可还延伸至第一基底100上表面100a上，以于感测区或元件区110上方形成一扁平化接触表面。此处仅绘示出封装层460于感测区或元件区110上方形成扁平化接触表面的实施例作为范例说明。在本实施例中，封装层460可由形塑材料(moldingmaterial)或密封材料(sealingmaterial)所构成。
一般而言，晶片的感测区或元件区及导电垫通常位于晶片的有源面，若将晶片的外部电性连接路径形成于有源面上，则需要在有源面上沉积多层膜层(例如，绝缘层)，因而造成有源面上的感测区的敏感度降低。
根据本发明的上述实施例，重布线层300通过第一基底100内的通孔240而电性连接至导电垫160，并自第一基底100的下表面100b横向延伸至突出于第一基底100的侧壁101。如此一来，第一基底100的外部电性连接路径自第一基底100的内部经由第一基底100的下表面100b而延伸至第一基底100的外侧，因此能够避免由于第一基底100的上表面100a上具有过多膜层造成感测区或元件区110的敏感度降低或光线穿透率降低的问题。再者，由于本发明实施例的重布线层300横向突出于第一基底100的侧壁101，因此用以将导电垫160与外部元件420彼此电性连接的外部导电结构(例如，打线)440可设置于第一基底100的外侧，而非第一基底100的上表面100a上，使得外部导电结构440的最高高度可低于上表面100a。如此一来，能够降低晶片封装体的整体高度，进而可缩小具有感测功能的电子产品的尺寸。
以下配合图1A至1H及图2说明本发明一实施例的晶片封装体的制造方法，其中图1A至1H以及图2分别绘示出根据本发明一实施例的晶片封装体的剖面示意图及平面示意图。
请参照图1A，提供一第一基底100，其具有一上表面100a及一下表面100b，且包括多个晶片区。为简化图式，此处仅绘示出局部的单一晶片区120。在一实施例中，第一基底100可为一硅基底或其他半导体基底。举例来说，第一基底100可为一硅晶圆，以利于进行晶圆级封装制程。
在本实施例中，第一基底100的上表面100a上具有一绝缘层140。一般而言，绝缘层140可由层间介电层、金属间介电层及覆盖的钝化层组成。为简化图式，此处仅绘示出单层绝缘层140。在本实施例中，绝缘层140可包括无机材料，例如氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合或其他适合的绝缘材料。
在本实施例中，每一晶片区120内的绝缘层140内具有一个或一个以上的导电垫160，邻近于第一基底100的上表面100a。在一实施例中，导电垫160可为单层导电层或具有多层的导电层结构。为简化图式，此处仅以单层导电层作为范例说明。在本实施例中，绝缘层140内包括一个或一个以上的开口180，以露出对应的导电垫160。举例来说，当导电垫160为具有多层的导电层结构时，开口180可露出多层导电层结构中的顶层导电层。
再者，晶片封装体还包括一感测区或元件区110，其可邻近于第一基底100的上表面100a，且可通过内连线结构(未绘示)与导电垫160电性连接。在一实施例中，感测区或元件区110内可包括一影像感测元件。在另一实施例中，感测区或元件区110可包括指纹辨识感测元件或其他生物特征感测元件。在其他实施例中，感测区或元件区110可包括一温度感测元件、一湿度感测元件、一压力感测元件或其他适合的感测元件。
请参照图1B，可通过一粘着层(例如，粘着胶)220，将一暂时性基底200贴附于上表面100a上的绝缘层140上。在本实施例中，暂时性基底200可为玻璃或其他适合的基底材料。接着，以暂时性基底200作为承载基板，自第一基底100的下表面100b进行薄化制程(例如，蚀刻制程、铣削(milling)制程、机械研磨(mechanicalgrinding)制程或化学机械研磨(chemicalmechanicalpolishing)制程)，以减少第一基底100的厚度。
请参照图1C，可通过微影制程及蚀刻制程(例如，干蚀刻制程、湿蚀刻制程、电浆蚀刻制程、反应性离子蚀刻制程或其他适合的制程)，在第一基底100的每一晶片区120内形成一个或一个以上的通孔240，对应于导电垫160。通孔240自第一基底100的下表面100b朝上表面100a延伸，且贯穿第一基底100而露出邻近于导电垫160的绝缘层140。
接着，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)，在第一基底100的下表面100b上顺应性形成一绝缘层260，其延伸至通孔240的侧壁及底部。在本实施例中，绝缘层260可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
请参照图1D，可通过微影制程及蚀刻制程(例如，干蚀刻制程、湿蚀刻制程、电浆蚀刻制程、反应性离子蚀刻制程或其他适合的制程)，去除通孔240底部上的绝缘层260以及邻近于导电垫160的绝缘层140，以形成一开口280。开口280露出导电垫160的一部分。举例来说，当导电垫160为具有多层的导电层结构时，开口280可露出多层导电层结构中的底层导电层。
接着，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)、微影制程及蚀刻制程，在绝缘层260上形成图案化的重布线层300。
重布线层300形成于第一基底100的下表面100b，且顺应性延伸至通孔240的侧壁及底部上，并填满开口280，因此重布线层300突出于第一基底100的上表面100a。在其他实施例中，重布线层300可同时填满通孔240及开口280。在本实施例中，重布线层300可通过绝缘层260与第一基底100电性隔离，且可经由通孔240及开口280直接电性接触或间接电性连接露出的导电垫160。因此，通孔240及开口280内的重布线层300也称为硅通孔电极(TSV)。在一实施例中，重布线层300可包括铝、铜、金、铂、镍、锡、前述的组合、导电高分子材料、导电陶瓷材料(例如，氧化铟锡或氧化铟锌)或其他适合的导电材料。
请参照图1E，可通过一接合层340，将第二基底320设置于下表面100b的绝缘层260上，以作为永久性的承载基底。在本实施例中，第二基底320可包括玻璃、硅或其他适合作为承载基底的材料。在本实施例中，接合层340填满通孔240。在其他实施例中，接合层340可部分填入通孔240或完全不填入通孔240。在本实施例中，接合层340可包括粘着胶(glue)、氧化物、氧化物及金属、聚合物或其他适合的接合材料。在提供第二基底320之后，可移除粘着层220及暂时性基底200。
请参照图1F，可通过刻痕(notching)制程、微影及蚀刻制程或其他适合的制程，在每一晶片区120内形成一个或一个以上的侧边凹陷360，其位于导电垫160外侧，且贯穿绝缘层140而延伸至第一基底100内。举例来说，可去除绝缘层140及第一基底100对应于晶片区120以及相邻晶片区120之间的切割道(未绘示)的部分。
请参照图1G，可利用位于上表面100a的绝缘层140作为硬式罩幕层，进行微影制程及蚀刻制程(例如，干蚀刻制程、湿蚀刻制程、电浆蚀刻制程、反应性离子蚀刻制程或其他适合的制程)，在每一晶片区120内形成一个或一个以上的侧边凹陷380。在其他实施例中，也可额外形成图案化光阻层，以进行上述微影制程及蚀刻制程。在本实施例中，侧边凹陷380位于导电垫160外侧，且与侧边凹陷360互相连通，并朝下表面100b延伸而贯穿第一基底100，进而露出第一基底100的下表面100b上的绝缘层260。举例来说，可去除第一基底100对应于晶片区120以及相邻晶片区120之间的切割道(未绘示)的部分，使得相邻晶片区120之间的第一基底100局部或完全分离。
在本实施例中，侧边凹陷380的一侧壁构成第一基底100的一侧壁101。在一实施例中，侧壁101倾斜于第一基底100的上表面100a。在其他实施例中，侧壁101可大致上垂直于第一基底100的上表面100a。
在本实施例中，侧边凹陷380的尺寸大于侧边凹陷360的尺寸，使得绝缘层140自第一基底100的上表面100a横向延伸而突出于第一基底100的侧壁101。在本实施例中，第一基底100的下表面100b上的绝缘层260及重布线层300皆自第一基底100的下表面100b横向延伸而突出于第一基底100的侧壁101。
一般而言，若重布线层自基底的上表面沿着基底的侧壁延伸，则基底需要具有倾斜的侧壁，以将重布线层顺利地自上表面沿着侧壁形成。然而，由于本发明实施例的重布线层自第一基底的内部经由下表面而延伸至横向突出第一基底的侧壁，而并未形成于第一基底的上表面及侧壁上，因此不论第一基底的侧壁为倾斜或垂直的，皆不会影响重布线层的形成。再者，虽然位于第一基底的上表面的绝缘层横向突出第一基底的侧壁，然而由于本发明实施例的重布线层并未形成于第一基底的上表面及侧壁上，因此绝缘层的突出部分并不会影响重布线层的形成，因而无需进行额外的制程将绝缘层的突出部分去除。
接着，可通过微影制程及蚀刻制程(例如，干蚀刻制程、湿蚀刻制程、电浆蚀刻制程、反应性离子蚀刻制程或其他适合的制程)，去除突出于侧壁101的绝缘层260的一部分，以形成一个或一个以上的开口400，其露出突出于侧壁101的重布线层300的一部分。
请同时参照图1G及图2，其中图1G是绘示出沿着图2中的剖线I-I’的剖面示意图。在本实施例中，侧边凹陷360及侧边凹陷380沿着第一基底100的周围延伸而横跨四个侧边的全部长度，进而露出第一基底100的四个侧边下方的绝缘层260。在另一实施例中，侧边凹陷360及侧边凹陷380可仅沿着第一基底100的其中一个侧边的一部分或全部长度横向延伸。又另一实施例中，侧边凹陷360及侧边凹陷380可横跨第一基底100的其中一个侧边的全部长度，且还沿着相邻的另一侧边的一部分或全部长度横向延伸。在其它实施例中，侧边凹陷360及侧边凹陷380可横跨第一基底100的其中一个侧边的全部长度，且还沿着相邻的两侧边的一部分或全部长度横向延伸。
在本实施例中，当通过刻痕制程形成侧边凹陷360且通过微影制程及蚀刻制程形成侧边凹陷380时，侧边凹陷360及侧边凹陷380沿着第一基底100的侧边的全部长度延伸，而当通过微影制程及蚀刻制程形成侧边凹陷360及侧边凹陷380时，侧边凹陷360及侧边凹陷380可沿着第一基底100的侧边的一部分或全部长度延伸。可以理解的是，虽然未绘示于图式中，只要侧边凹陷沿着第一基底100的至少一个侧边的一部分或全部长度横向延伸，侧边凹陷的实际数量及位置取决于设计需求。
再者，如图2所示，多个开口180形成于绝缘层140内，以露出对应的导电垫160。通孔240形成于对应的导电垫160下方，而重布线层300自导电垫160及通孔240下方横向延伸至绝缘层260下方。为清楚表示，此处以虚线绘示出重布线层300的轮廓。多个开口400形成于绝缘层260内，以露出对应的重布线层300。可以理解的是，图2所示的部件的数量、形状及位置取决于设计需求而不限定于此。
接着，请参照图1H，沿着相邻晶片区120之间的切割道(未绘示)，对绝缘层260及第二基底320进行切割制程，以形成多个独立的晶片封装体。
接着，可通过一粘着层(未绘示)，将一外部元件420贴附于独立的晶片封装体中的第二基底320上。在本实施例中，外部元件420可为电路板、晶片或中介层。
接着，可通过打线接合(WireBonding)制程，将一个或一个以上的外部导电结构440形成于对应的开口400内，以通过露出的重布线层300电性连接至对应的导电垫160，并将外部导电结构440延伸至外部元件420上，以将导电垫160与外部元件420电性连接。在其他实施例中，外部导电结构440可设置于绝缘层140的开口180内，而电性连接至对应的导电垫160。可以理解的是，外部导电结构440的实际数量及位置取决于设计需求。虽然未绘示于图式中，可选择性将一个以上的外部导电结构440分别设置于开口400及开口180内。在一实施例中，外部导电结构440可由开口400内的接合球及自接合球延伸至外部元件420的接线所构成。再者，外部导电结构440可包括金或其他适合的导电材料。
在一实施例中，外部导电结构440的最高部分低于第一基底100的上表面100a。在其他实施例中，外部导电结构440的最高部分可突出于第一基底100的上表面100a。
接着，可通过模塑成型(molding)制程或沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)，在外部元件420及独立的晶片封装体上形成选择性的封装层460，其可覆盖外部导电结构440及一部分的第一基底100，或可还延伸至第一基底100上表面100a上，以于感测区或元件区110上方形成一扁平化接触表面。此处仅绘示出封装层460于感测区或元件区110上方形成扁平化接触表面的实施例作为范例说明。在本实施例中，封装层460可由形塑材料或密封材料所构成。
根据本发明的上述实施例，由于在晶片内形成电性连接至导电垫的硅通孔电极，且将硅通孔电极中的重布线层自晶片的非有源面横向延伸至突出于晶片的侧壁，因此晶片的外部电性连接路径自晶片的内部经由晶片的非有源面而延伸至晶片的外侧，进而能够避免由于在有源面上沉积过多膜层造成感测敏感度降低的问题。举例来说，当晶片封装体内具有感光元件时，本发明的上述实施例能够增加感测区或元件区的光线穿透率，进而提升晶片封装体的感测敏感度。
再者，由于本发明实施例的重布线层横向突出于晶片的侧壁，因此用以将晶片与外部元件彼此电性连接的外部导电结构(例如，打线)可形成于晶片的外侧，而非晶片的有源面上，使得晶片封装体的尺寸能够进一步缩小。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (24)

1.一种晶片封装体，其特征在于，包括：
一第一基底，具有一上表面、一下表面及一侧壁，其中一感测区或元件区及一导电垫邻近于该上表面；
一通孔，贯穿该第一基底；以及
一重布线层，自该下表面延伸至该通孔内，且与该导电垫电性连接，其中该重布线层还自该下表面横向延伸而突出于该第一基底的该侧壁。
2.根据权利要求1所述的晶片封装体，其特征在于，该重布线层还延伸突出于该上表面，以电性连接至该导电垫。
3.根据权利要求1所述的晶片封装体，其特征在于，还包括一绝缘层，该绝缘层设置于该第一基底与该重布线层之间，其中该绝缘层自该下表面横向延伸而突出于该侧壁，且该绝缘层具有一开口，该开口露出突出于该侧壁的该重布线层。
4.根据权利要求3所述的晶片封装体，其特征在于，还包括一外部导电结构，该外部导电结构设置于该开口内，且电性连接至突出于该侧壁的该重布线层。
5.根据权利要求1所述的晶片封装体，其特征在于，还包括一绝缘层，其中该导电垫位于该绝缘层内，且该绝缘层自该上表面横向延伸而突出于该侧壁。
6.根据权利要求1所述的晶片封装体，其特征在于，还包括一第二基底，其中通过一接合层将该第一基底的该下表面设置于该第二基底上。
7.根据权利要求6所述的晶片封装体，其特征在于，该接合层填入该通孔。
8.根据权利要求6所述的晶片封装体，其特征在于，该第二基底内包括特定应用集成电路或信号处理器。
9.根据权利要求1所述的晶片封装体，其特征在于，该感测区或元件区内包括影像感测元件、生物特征感测元件或环境特征感测元件。
10.根据权利要求1所述的晶片封装体，其特征在于，还包括一侧边凹陷，其中该侧边凹陷的一侧壁构成该第一基底的该侧壁，且该侧边凹陷沿着该第一基底的一侧边的至少一部分长度横向延伸。
11.根据权利要求10所述的晶片封装体，其特征在于，该侧边凹陷沿着该侧边的全部长度横向延伸。
12.根据权利要求11所述的晶片封装体，其特征在于，该侧边凹陷还延伸至与该侧边相邻的至少一另一侧边的至少一部分长度。
13.一种晶片封装体的制造方法，其特征在于，包括：
提供一第一基底，该第一基底具有一上表面、一下表面及一侧壁，其中一感测区或元件区及一导电垫邻近于该上表面；
形成一通孔，该通孔贯穿该第一基底；以及
形成一重布线层，该重布线层自该下表面延伸至该通孔内，且与该导电垫电性连接，其中该重布线层还自该下表面横向延伸而突出于该第一基底的该侧壁。
14.根据权利要求13所述的晶片封装体的制造方法，其特征在于，该重布线层还延伸突出于该上表面，以电性连接至该导电垫。
15.根据权利要求13所述的晶片封装体的制造方法，其特征在于，还包括在该第一基底与该重布线层之间形成一绝缘层，其中该绝缘层自该下表面横向延伸而突出于该侧壁，且该绝缘层具有一开口，该开口露出突出于该侧壁的该重布线层。
16.根据权利要求15所述的晶片封装体的制造方法，其特征在于，还包括在该开口内形成一外部导电结构，该外部导电结构电性连接至突出于该侧壁的该重布线层。
17.根据权利要求13所述的晶片封装体的制造方法，其特征在于，该导电垫位于一绝缘层内，且该绝缘层自该上表面横向延伸而突出于该侧壁。
18.根据权利要求13所述的晶片封装体的制造方法，其特征在于，还包括通过一接合层，将该第一基底的该下表面设置于一第二基底上。
19.根据权利要求18所述的晶片封装体的制造方法，其特征在于，该接合层填入该通孔。
20.根据权利要求18所述的晶片封装体的制造方法，其特征在于，该第二基底内包括特定应用集成电路或信号处理器。
21.根据权利要求13所述的晶片封装体的制造方法，其特征在于，该感测区或元件区内包括影像感测元件、生物特征感测元件或环境特征感测元件。
22.根据权利要求13所述的晶片封装体的制造方法，其特征在于，还包括形成一侧边凹陷，其中该侧边凹陷的一侧壁构成该第一基底的该侧壁，且该侧边凹陷沿着该第一基底的一侧边的至少一部分长度横向延伸。
23.根据权利要求22所述的晶片封装体的制造方法，其特征在于，该侧边凹陷沿着该侧边的全部长度横向延伸。
24.根据权利要求23所述的晶片封装体的制造方法，其特征在于，该侧边凹陷还延伸至与该侧边相邻的至少一另一侧边的至少一部分长度。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101989557A (zh) * 2009-07-30 2011-03-23 株式会社东芝 半导体装置的制造方法以及半导体装置
US20120326307A1 (en) * 2011-06-27 2012-12-27 Jeong Se-Young Stacked semiconductor device
US20130307125A1 (en) * 2010-05-11 2013-11-21 Xintec Inc. Chip package and method for forming the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8367477B2 (en) * 2009-03-13 2013-02-05 Wen-Cheng Chien Electronic device package and method for forming the same
CN102782862B (zh) 2010-02-26 2015-08-26 精材科技股份有限公司 芯片封装体及其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101989557A (zh) * 2009-07-30 2011-03-23 株式会社东芝 半导体装置的制造方法以及半导体装置
US20130307125A1 (en) * 2010-05-11 2013-11-21 Xintec Inc. Chip package and method for forming the same
US20120326307A1 (en) * 2011-06-27 2012-12-27 Jeong Se-Young Stacked semiconductor device

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