CN104979426A - 晶片封装体的制造方法 - Google Patents

晶片封装体的制造方法 Download PDF

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Publication number
CN104979426A
CN104979426A CN201510143980.5A CN201510143980A CN104979426A CN 104979426 A CN104979426 A CN 104979426A CN 201510143980 A CN201510143980 A CN 201510143980A CN 104979426 A CN104979426 A CN 104979426A
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China
Prior art keywords
substrate
encapsulation body
wafer encapsulation
manufacture method
layer
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Pending
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CN201510143980.5A
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English (en)
Inventor
何彦仕
刘沧宇
林佳升
张义民
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XinTec Inc
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XinTec Inc
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Publication of CN104979426A publication Critical patent/CN104979426A/zh
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    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
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    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00865—Multistep processes for the separation of wafers into individual elements
    • B81C1/00896—Temporary protection during separation into individual elements
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Abstract

本发明揭露一种晶片封装体的制造方法，包括提供一基底及一盖层，其中基底内具有邻近于基底的一表面的一感测装置。通过一粘着层将盖层贴附于基底的表面上，其中粘着层覆盖感测装置。沿着一方向，对基底、粘着层及盖层进行一切割制程，以形成独立的晶片封装体。本发明能够在晶片封装体的制作过程中以及在使用晶片封装体的感测功能的过程中保护感测装置，避免受到污染或破坏，因此可改善感测装置的感测效能，进而提升晶片封装体的可靠度或品质。

Description

晶片封装体的制造方法
技术领域
本发明有关于一种晶片封装技术，特别为有关于一种晶片封装体的制造方法。
背景技术
晶片封装制程是形成电子产品过程中的重要步骤。晶片封装体除了将晶片保护于其中，使免受外界环境污染外，还提供晶片内部电子元件与外界的电性连接通路。
具有感测功能的晶片封装体的感测装置在传统的制作过程中以及在使用晶片封装体的感测功能的过程中容易受到污染或破坏，造成感测装置的效能降低，进而降低晶片封装体的可靠度或品质。
因此，有必要寻求一种新颖的晶片封装体的制造方法，其能够解决或改善上述的问题。
发明内容
本发明实施例提供一种晶片封装体的制造方法，包括：提供一基底及一盖层，其中基底内具有邻近于基底的一第一表面的一感测装置。通过一粘着层将盖层贴附于基底的第一表面上，其中粘着层覆盖感测装置。沿着一方向，对基底、粘着层及盖层进行一切割制程，以形成独立的晶片封装体。
本发明能够在晶片封装体的制作过程中以及在使用晶片封装体的感测功能的过程中保护感测装置，避免受到污染或破坏，因此可改善感测装置的感测效能，进而提升晶片封装体的可靠度或品质。
附图说明
图1A至1E绘示出根据本发明一实施例的晶片封装体的制造方法的剖面示意图。
图2绘示出根据本发明另一实施例的晶片封装体的制造方法的剖面示意图。
图3及4绘示出根据本发明不同实施例的晶片封装体的剖面示意图。
其中，附图中符号的简单说明如下：
100：基底；100a：第一表面；100b：第二表面；120：晶片区；140：导电垫；160：感测装置；180：粘着层；200：盖层；310：第一开口；320：绝缘层；340：重布线层；360：钝化保护层；380：第二开口；400：导电结构；420：保护层；500：电路板；540：接触垫；560：焊线；L：切割道。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关连性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装微机电系统晶片。然其应用不限于此，例如在本发明的晶片封装体的实施例中，其可应用于各种包含有源元件或无源元件(active or passive elements)、数字电路或模拟电路(digital oranalog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(opto electronic devices)、微机电系统(Micro Electro MechanicalSystem；MEMS)、微流体系统(micro fluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package；WSP)制程对影像感测元件、发光二极管(light-emitting diodes；LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件(surface acoustic wave devices)、压力感测器(process sensors)或喷墨头(ink printer heads)等半导体晶片进行封装。
其中上述晶圆级封装制程主要是指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于通过堆叠(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layer integrated circuit devices)的晶片封装体。
以下配合图1A至1E说明本发明一实施例的晶片封装体的制造方法，其中图1A至1E绘示出根据本发明一实施例的晶片封装体的制造方法的剖面示意图。
请参照图1A，提供一基底100，其具有一第一表面100a及与其相对的一第二表面100b，且包括多个晶片区120。在一实施例中，基底100可为一硅基底或其他半导体基底。在另一实施例中，基底100为一硅晶圆，以利于进行晶圆级封装制程。
在本实施例中，基底100的每一晶片区120内具有多个导电垫，其可邻近于第一表面100a。为简化图式，此处仅绘示出相邻的两个晶片区120以及分别位于基底100的单一晶片区120内的两个导电垫140。在一实施例中，导电垫140可为单层导电层或具有多层的导电层结构。此处，仅以单层导电层作为范例说明。
在本实施例中，基底100的每一晶片区120内具有一感测装置160，其可邻近于基底100的第一表面100a。在一实施例中，感测装置160可包括影像感测元件。在另一实施例中，感测装置160用以感测生物特征，且可包括一指纹辨识元件。又另一实施例中，感测装置160用以感测环境特征，且可包括一温度感测元件、一湿度感测元件、一压力感测元件或其他适合的感测元件。在一实施例中，感测装置160可通过内连线结构(未绘示)而与导电垫140电性连接。
接着，可通过一粘着层180，将一盖层200贴附于基底100的第一表面100a上。在本实施例中，粘着层180覆盖感测装置160，且粘着层180与感测装置160之间不具有空隙。在一实施例中，盖层200与感测装置160之间仅具有粘着层180，而不具有其他间隔层(或称作围堰(dam)。在一实施例中，粘着层180可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的粘着材料。再者，盖层200包括玻璃、氮化铝(AlN)、胶带、蓝宝石(Sapphire)或其他适合的保护材料。
请参照图1B，以盖层200作为承载基板，对基底100的第二表面100b进行薄化制程(例如，蚀刻制程、铣削(milling)制程、机械研磨(mechanical grinding)制程或化学机械研磨(chemical mechanical polishing)制程)，以减少基底100的厚度。
接着，可通过微影制程及蚀刻制程(例如，干蚀刻制程、湿蚀刻制程、等离子蚀刻制程、反应性离子蚀刻制程或其他适合的制程)，在基底100的每一晶片区120内形成多个第一开口310。第一开口310自基底100的第二表面100b朝第一表面100a延伸，且分别暴露出邻近于第一表面100a的对应的导电垫140。
接着，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)，在基底100的第二表面100b上顺应性形成一绝缘层320，其延伸至基底100的第一开口310内。在本实施例中，绝缘层320可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
请参照图1C，可通过微影制程及蚀刻制程(例如，干蚀刻制程、湿蚀刻制程、等离子蚀刻制程、反应性离子蚀刻制程或其他适合的制程)，去除第一开口310的底部上的绝缘层320，以暴露出导电垫140的表面。接着，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)、微影制程及蚀刻制程，在绝缘层320上形成图案化的重布线层340。
重布线层340顺应性延伸至基底100的第一开口310的底部，且与暴露出的导电垫140直接接触，以电性连接至导电垫140，并通过绝缘层320与基底100电性隔离。因此，第一开口310内的重布线层340也称为硅通孔电极(through silicon via，TSV)。在一实施例中，重布线层340可包括铜、铝、金、铂、镍、锡、前述的组合、导电高分子材料、导电陶瓷材料(例如，氧化铟锡或氧化铟锌)或其他适合的导电材料。
在另一实施例中，基底100的第一开口310可暴露出导电垫140的侧壁，且重布线层340通过绝缘层320与基底100电性隔离，并与暴露出的导电垫140的侧壁直接接触，而以T型接触(T-contact)的方式电性连接至导电垫140。又另一实施例中，基底100的第一开口310可至少穿过导电垫140，使得重布线层340可与导电垫140的内部直接接触，而以环型接触(ring-contact)的方式电性连接至导电垫140。
接着，可通过沉积制程，在重布线层340上形成一钝化保护层360，且填入基底100的第一开口310内，以覆盖重布线层340。接着，可通过微影制程及蚀刻制程，在每一晶片区120的钝化保护层360内形成多个第二开口380，以暴露出位于基底100的第二表面100b上的重布线层340的一部分。在本实施例中，钝化保护层360可包括环氧树脂、绿漆(solder mask)、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。在另一实施例中，钝化保护层360可包括光阻材料，且可通过曝光制程及显影制程，在钝化保护层360内形成第二开口380。
请参照图1D，在钝化保护层360的第二开口380内形成导电结构(例如，焊球、凸块或导电柱)400，以直接接触暴露出的重布线层340，而与图案化的重布线层340电性连接。举例来说，可通过电镀制程、网版印刷制程或其他适合的制程，在钝化保护层360的第二开口380内形成焊料(solder)，且进行回焊(reflow)制程，以形成导电结构400。另外，虽然未绘示于图式中，但从上视方向来看，导电结构400可在基底100的第二表面100b上排列成一矩阵。在本实施例中，导电结构400可包括锡、铅、铜、金、镍、前述的组合或其他适合的导电材料。
接着，在钝化保护层360及导电结构400上形成一保护层420(例如，胶带)，以提供平坦的表面及保护导电结构400。接着，以保护层420作为支撑，沿着相邻晶片区120之间的切割道L，且沿着自盖层200朝基底100的方向，对基底100、粘着层180及盖层200进行切割制程，并去除保护层420，以形成多个独立的晶片封装体，如图1E所示。在上述实施例中，盖层200由透光材料(例如，玻璃、蓝宝石或其他适合的透光材料)所构成，有利于沿着自盖层200朝基底100的方向进行切割制程，进而提升对位的精准度。
在另一实施例中，如图2所示，亦可直接利用盖层200提供平坦的表面，沿着自基底100朝盖层200的方向进行上述切割制程，而无需额外形成保护导电结构400的保护层(例如，图1D中的保护层420)。再者，盖层200由非透光材料(例如，氮化铝、胶带或其他适合的非透光材料)所构成时，可预先在基底100的第二表面100b上方形成对准标记(alignment mark)，以提升切割制程的精准度。举例来说，在形成钝化保护层360的第二开口380的步骤中，可同时在钝化保护层360内形成作为对准标记的孔洞(未绘示)，以利于后续沿着自基底100朝盖层200的方向进行切割制程。
在本实施例中，可进一步在独立的晶片封装体的基底100的第二表面100b上提供一电路板(未绘示)，且通过导电结构400将重布线层340及导电垫140电性连接至电路板的接触垫(未绘示)。
请参照图3及4，其绘示出根据本发明不同实施例的晶片封装体的剖面示意图，其中相同于图1E中的部件使用相同的标号并省略其说明。图3中的晶片封装体的制造方法类似于图1E中的晶片封装体的制造方法，差异在于图3中的晶片封装体的制造方法不包括在钝化保护层360的第二开口380内形成图1E中的导电结构400，而是在进行切割制程之后，仍暴露出位于基底100的第二表面100b上的重布线层340的一部分。再者，另一差异在于图3中的晶片封装体的制造方法还包括在进行切割制程之后，在基底100的第二表面100b上提供一电路板(例如，软性印刷电路板(flexible print circuit，FPC))500，且进行打线接合(wire bond)制程，在暴露出的重布线层340上形成对应的焊线560，并将焊线560延伸至电路板500内的接触垫540上，以将基底100内的导电垫140电性连接至电路板500内对应的接触垫540。另外，虽然图3中的焊线560分别自感测装置160相对两侧的基底100的第二表面100b上延伸至电路板500上，然而可以理解的是，各个焊线560可皆自感测装置160的同一侧或分别自感测装置160的相邻两侧延伸至电路板500上。
再者，图4中的晶片封装体的制造方法类似于图1E中的晶片封装体的制造方法，差异在于图4中的晶片封装体的制造方法中形成第一开口310的步骤还包括通过同一蚀刻制程，同时去除基底100的侧壁的一部分，以暴露出粘着层180的一部分，使得晶片封装体具有阶梯状的侧壁。
在其他实施例中，可结合图3及4中的晶片封装体的制造方法的实施例。举例来说，在形成独立的晶片封装体之前，不在图4中的晶片封装体的钝化保护层360的第二开口380内形成导电结构400，而是在形成独立的晶片封装体之后，仍暴露出位于基底100的第二表面100b上的重布线层340的一部分。接着，可进一步在图4中的晶片封装体的基底100的第二表面100b上提供图3中的电路板500，且在暴露出的重布线层340上及电路板500内对应的接触垫540上形成图3中的焊线560，以通过焊线560，将基底100内的导电垫140电性连接至电路板500内的接触垫540。
根据本发明的上述实施例，通过粘着层180将盖层200贴附于基底100的第一表面100a上，且盖层200及粘着层180覆盖基底100的第一表面100a上的感测装置160而与感测装置160之间不具有空隙，能够在晶片封装体的制作过程中以及在使用晶片封装体的感测功能的过程中保护感测装置，避免受到污染或破坏，因此可改善感测装置的感测效能，进而提升晶片封装体的可靠度或品质。
再者，采用晶圆级制程来制作晶片封装体，可大量生产晶片封装体，进而降低成本并节省制程时间。另外，由于使用硅通孔电极、环型接触或T型接触作为具有感测装置的基底的外部电性连接的路径，而不需使用焊线及导线架，能够节省成本，并使得晶片封装体的尺寸能够进一步缩小。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (11)

1.一种晶片封装体的制造方法，其特征在于，包括：
提供一基底及一盖层，其中该基底内具有邻近于该基底的一第一表面的一感测装置；
通过一粘着层将该盖层贴附于该基底的该第一表面上，其中该粘着层覆盖该感测装置；以及
沿着一方向，对该基底、该粘着层及该盖层进行一切割制程，以形成独立的晶片封装体。
2.根据权利要求1所述的晶片封装体的制造方法，其特征在于，该感测装置与该粘着层之间不具有空隙。
3.根据权利要求1所述的晶片封装体的制造方法，其特征在于，该方向为自该盖层朝该基底。
4.根据权利要求1所述的晶片封装体的制造方法，其特征在于，该方向为自该基底朝该盖层。
5.根据权利要求1所述的晶片封装体的制造方法，其特征在于，该盖层包括玻璃、氮化铝、胶带或蓝宝石。
6.根据权利要求1所述的晶片封装体的制造方法，其特征在于，还包括在进行该切割制程之前，在该基底相对于该第一表面的一第二表面上形成一导电结构以及覆盖该导电结构的一保护层。
7.根据权利要求1所述的晶片封装体的制造方法，其特征在于，该基底内具有一导电垫，该导电垫邻近于该第一表面，且在进行该切割制程之前，该晶片封装体的制造方法还包括：
在该基底内形成一第一开口，该第一开口自该基底相对于该第一表面的一第二表面朝该第一表面延伸，且暴露出该导电垫；
在该第二表面上形成一绝缘层，且该绝缘层延伸至该第一开口内；
在该绝缘层上形成一重布线层，且该重布线层接触暴露出的该导电垫；以及
在该重布线层上形成一钝化保护层，且该钝化保护层暴露出位于该第二表面上一部分的该重布线层。
8.根据权利要求7所述的晶片封装体的制造方法，其特征在于，还包括在进行该切割制程之前，在暴露出的该重布线层上形成焊球、凸块或导电柱。
9.根据权利要求7所述的晶片封装体的制造方法，其特征在于，还包括在进行该切割制程之后，在暴露出的该重布线层上形成焊线。
10.根据权利要求7所述的晶片封装体的制造方法，其特征在于，形成该第一开口的步骤还包括去除该基底的侧壁的一部分，以暴露出该粘着层的一部分。
11.根据权利要求7所述的晶片封装体的制造方法，其特征在于，还包括在进行该切割制程之前，薄化该基底。
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