CN105047619B - 晶片堆叠封装体及其制造方法 - Google Patents

晶片堆叠封装体及其制造方法 Download PDF

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CN105047619B
CN105047619B CN201510187746.2A CN201510187746A CN105047619B CN 105047619 B CN105047619 B CN 105047619B CN 201510187746 A CN201510187746 A CN 201510187746A CN 105047619 B CN105047619 B CN 105047619B
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substrate
packaging body
wafer stacking
layer
stacking packaging
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CN105047619A (zh
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何彦仕
何志伟
刘沧宇
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XinTec Inc
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XinTec Inc
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Abstract

本发明揭露一种晶片堆叠封装体及其制造方法。该晶片堆叠封装体包括：至少一第一基底，其具有一第一侧及相对的一第二侧，且包括一凹口及多个重布线层，凹口位于第一基底内且邻接其一侧边，多个重布线层设置于第一基底上且延伸至凹口的一底部；至少一第二基底，设置于第一基底的第一侧；多个焊线，对应设置于凹口内的重布线层上，且延伸至第二基底上；以及至少一装置基底，设置于第一基底的第二侧。本发明可有效降低晶片堆叠封装体的整体尺寸。

Description

晶片堆叠封装体及其制造方法
技术领域
本发明有关于一种封装技术，特别为有关于一种晶片堆叠封装体及其制造方法。
背景技术
一般而言，在完成晶片封装体的制作之后，可将晶片封装体接合于封装部件(例如，中介层或印刷电路板(Printed Circuit Board，PCB))上，且在晶片封装体与封装部件之间形成外部导电结构，以通过外部导电结构将晶片封装体内的导电垫电性连接至封装部件上的电路，进而形成晶片堆叠封装体。
然而，上述外部导电结构使得晶片堆叠封装体的整体尺寸增加，而无法进一步缩小晶片堆叠封装体的尺寸。
因此，有必要寻求一种新颖的晶片堆叠封装体及其制造方法，其能够解决或改善上述的问题。
发明内容
本发明提供一种晶片堆叠封装体，包括：至少一第一基底，其具有一第一侧及相对的一第二侧，且包括位于第一基底内且邻接其一侧边的一凹口、以及设置于第一基底上且延伸至凹口的一底部的多个重布线层；至少一第二基底，设置于第一基底的第一侧；多个焊线，对应设置于凹口内的重布线层上，且延伸至第二基底上；以及至少一装置基底，设置于第一基底的第二侧。
本发明还提供一种晶片堆叠封装体的制造方法，包括：提供至少一第一基底，至少一第一基底具有一第一侧及相对的一第二侧，且包括位于第一基底内且邻接其一侧边的一凹口、以及设置于第一基底上且延伸至凹口的一底部的多个重布线层；在第一基底的第一侧提供至少一第二基底；在凹口内的重布线层上对应形成多个焊线，并延伸至第二基底上；以及在第一基底的第二侧提供至少一装置基底。
本发明可有效降低晶片堆叠封装体的整体尺寸。
附图说明
图1A至1C是绘示出根据本发明一实施例的晶片堆叠封装体的第一基底的制造方法的剖面示意图。
图2是绘示出本发明另一实施例的晶片堆叠封装体的第一基底的剖面示意图。
图3至7是绘示出本发明各种实施例的晶片堆叠封装体的第一基底的平面示意图。
图8是绘示出本发明一实施例的晶片堆叠封装体的剖面示意图。
图9是绘示出本发明另一实施例的晶片堆叠封装体的剖面示意图。
其中，附图中符号的简单说明如下：
100 第一基底；
100a、300a、400a、500a 上表面；
101、102、103、104 侧边；
110 晶片区；
120 切割道区；
140 第三导电垫；
150、340、440 钝化保护层；
200 凹口；
220 重布线层；
220a 扩大部；
300 装置基底；
300b 下表面；
310 第一导电垫；
320、420 绝缘层；
330、430 导电层；
350 第一导电结构；
360 焊线；
400 第二基底；
410 第四导电垫；
450 第二导电结构；
500 第三基底；
510 第二导电垫；
H 高度。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定形式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关连性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装微机电系统晶片。然其应用不限于此，例如在本发明的晶片封装体的实施例中，其可应用于各种包含有源元件或无源元件(active or passive elements)、数字电路或模拟电路(digital or analog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(optoelectronic devices)、微机电系统(Micro Electro Mechanical System；MEMS)、微流体系统(micro fluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package；WSP)制程对影像感测元件、发光二极管(light-emitting diodes；LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(microactuators)、表面声波元件(surface acoustic wave devices)、压力感测器(processsensors)或喷墨头(ink printer heads)等半导体晶片进行封装。
其中上述晶圆级封装制程主要是指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于通过堆叠(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layerintegrated circuit devices)的晶片封装体。
请参照图8，其绘示出根据本发明一实施例的晶片堆叠封装体的剖面示意图。在本实施例中，晶片堆叠封装体包括一第一基底100、一第二基底400、一装置基底300及多个焊线360。第一基底100具有一第一侧及相对的一第二侧，且第一基底100内具有多个第三导电垫140，邻近于其上表面100a。在本实施例中，第一基底100可为晶片或中介层(interposer)。在一实施例中，第一基底100为一硅晶圆，以利于进行晶圆级封装。在本实施例中，第三导电垫140可为单层导电层或具有多层的导电层结构。此处，仅以单层导电层作为范例说明。
请同时参照图7及8，其中图7是绘示出本发明一实施例的晶片堆叠封装体的第一基底100的平面示意图。在此实施例中，第一基底100内具有两个凹口200，分别邻接于第一基底100的两相对侧边101及103。再者，凹口200的侧壁倾斜于第一基底100的上表面100a，且凹口200的底部平行于第一基底100的上表面100a。在另一实施例中，凹口200的侧壁倾斜于第一基底100的上表面100a，且凹口200的底部可非平行于第一基底100的上表面100a。在其他实施例中，凹口200的侧壁可垂直于第一基底100的上表面100a，且凹口200的底部可平行或非平行于第一基底100的上表面100a。另外，凹口200的侧壁及底部可能凹凸不平而呈现锯齿状轮廓。在图7及8的实施例中，邻接于第一基底100的侧边101及103的凹口200为单阶凹口，然而在其他实施例中，第一基底100内可具有由多个连续凹口所构成的多阶凹口(未绘示)。
一钝化保护(passivation)层150设置于第一基底100的上表面100a上，并延伸至凹口200的侧壁及底部。钝化保护层150具有多个开口，以暴露出对应的第三导电垫140。在本实施例中，钝化保护层150可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的介电材料。
多个重布线层(redistribution layer，RDL)220设置于钝化保护层150上，且接触暴露出的第三导电垫140，并延伸至凹口200的侧壁及底部。在一实施例中，重布线层220局部覆盖暴露出的第三导电垫140。在另一实施例中，重布线层220可完全覆盖暴露出的第三导电垫140。在本实施例中，重布线层220可包括铜、铝、金、铂、镍、锡、前述的组合或其他适合的导电材料。
在图7的实施例中，重布线层220延伸至凹口200底部的一端可具有一扩大部220a，且各个扩大部220a彼此可具有相同或不同的尺寸及/或形状。举例来说，邻接于侧边101的凹口200内的两个圆形扩大部220a具有相同的尺寸，而分别邻接于侧边101及103的凹口200内的两个圆形扩大部220a具有不同的尺寸。再者，邻接于侧边101及103的凹口200内的扩大部220a各自具有圆形、椭圆形及矩形的外型。在其他实施例中，重布线层220的扩大部220a可具有其他适合作为电路图案的形状及尺寸。另外，可以理解的是，图式中第三导电垫140的位置、重布线层220的数量及延伸路径、扩大部220a的尺寸及形状仅作为范例说明，并不限定于此。
请再参照图8，一第二基底400设置于第一基底100的第一侧。在本实施例中，第二基底400可为晶片、中介层或电路板。第二基底400内可具有多个第四导电垫410，邻近于其上表面400a。在本实施例中，第四导电垫410可为单层导电层或具有多层的导电层结构。此处，仅以单层导电层作为范例说明。
多个焊线360设置于第一基底100的凹口200内对应的重布线层220上，且延伸至第二基底400的第四导电垫410上，以将重布线层220电性连接至对应的第四导电垫410。在本实施例中，焊线360位于第一基底100的上表面100a与第二基底400的上表面400a之间，且焊线360的最高高度H低于第一基底100的上表面100a。
一装置基底300设置于第一基底100的第二侧，以形成三维(Three-Dimensional)晶片堆叠封装体。在本实施例中，装置基底300可为晶片，且可具有感测装置(未绘示)位于其上表面300a上。在一实施例中，上述感测装置可包括生物特征感测元件(例如，指纹辨识元件)、影像感测元件或其他适合的感测元件。在本实施例中，装置基底300内具有多个第一导电垫310，邻近于其上表面300a。在本实施例中，第一导电垫310可为单层导电层或具有多层的导电层结构，且可通过内连线结构(未绘示)而与装置基底300上的感测装置(未绘示)电性连接。此处，仅以单层导电层作为范例说明。再者，第一导电垫310可通过装置基底300内的多个硅通孔电极(through silicon via，TSV)及多个第一导电结构350电性连接至第一基底100上的重布线层220。
举例来说，装置基底300内具有自下表面300b朝上表面300a延伸的多个开口，暴露出第一导电垫310的表面。一绝缘层320设置于下表面300b上且延伸进入装置基底300的开口内。在本实施例中，绝缘层320可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
一图案化的导电层330设置于绝缘层320上且延伸进入装置基底300的开口内，以电性接触暴露出的第一导电垫310，且通过绝缘层320与装置基底300电性隔离。因此，装置基底300的开口内的导电层330为硅通孔电极。在本实施例中，导电层330可包括铜、铝、金、铂、镍、锡、前述的组合或其他适合的导电材料。
在另一实施例中，装置基底300内的开口可暴露出第一导电垫310的侧壁，且图案化的导电层330通过绝缘层320与装置基底300电性隔离，并与暴露出的第一导电垫310的侧壁直接接触，而以T型接触(T-contact)的方式电性连接至第一导电垫310。又另一实施例中，装置基底300内的开口可穿过第一导电垫310，使得图案化的导电层330可与第一导电垫310的内部直接接触，而以环型接触(ring-contact)的方式电性连接至第一导电垫310。
一钝化保护层340设置于图案化的导电层330上，且填入装置基底300的开口内，以覆盖导电层330。钝化保护层340具有多个开口，暴露出位于装置基底300的下表面300b上的导电层330的一部分。在本实施例中，钝化保护层340可包括环氧树脂、绿漆(solder mask)、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)、光阻材料或其他适合的绝缘材料。
第一导电结构350设置于钝化保护层340的开口内，且装置基底300通过第一导电结构350接合至第一基底100上。再者，第一导电结构350电性接触第一基底100上对应的重布线层220。在本实施例中，第一导电结构350可为焊球、凸块或导电柱，且可包括锡、铅、铜、金、镍、前述的组合或其他适合的导电材料。
虽然图8中的装置基底300的尺寸大于第一基底100的尺寸，然而装置基底300的尺寸也可等于或小于第一基底100的尺寸。再者，第一基底100可具有足够大的尺寸，以在第一基底100的第二侧设置一个以上的装置基底300。同样地，第二基底400亦可具有足够大的尺寸，以将一个以上的第一基底100接合至第二基底400。
请参照图9，其绘示出根据本发明另一实施例的晶片堆叠封装体的剖面示意图，其中相同于前述图7及8的实施例的部件使用相同的标号并省略其说明。图9中的晶片堆叠封装体的结构类似于图8中的晶片堆叠封装体的结构，差异在于图9中的晶片堆叠封装体还包括一第三基底500，设置于第一基底100的第一侧，且第二基底400位于第一基底100与第三基底500之间。在本实施例中，第三基底500可为晶片、中介层或电路板。第三基底500内具有多个第二导电垫510，邻近于其上表面500a，且可为单层导电层或具有多层的导电层结构。此处，仅以单层导电层作为范例说明。
图8中的第一导电垫310通过装置基底300内的硅通孔电极及第一导电结构350，而电性连接至对应的第三导电垫140。类似地，在图9的实施例中，第四导电垫410通过第二基底400内的多个硅通孔电极及多个第二导电结构450(例如，焊球、凸块或导电柱)电性连接至对应的第二导电垫510。相同地，在其他实施例中，第四导电垫410也可通过T型接触或环型接触的方式电性连接至第二导电结构450及第二导电垫510。另外，当第二基底400为中介层或电路板时，第二基底400内可包括由介电层、介电层内的金属接触窗(contact)及介层插塞(via)所构成的内连接结构(未绘示)，且第四导电垫410可通过内连接结构以及第二导电结构450电性连接至第二导电垫510。
虽然图9中的第三基底500的尺寸大于第二基底400的尺寸，然而第三基底500的尺寸也可等于第二基底400的尺寸。再者，第三基底500可具有足够大的尺寸，以将一个以上的第二基底400接合至第三基底500。
请参照图3至6，其绘示出本发明各种实施例的晶片堆叠封装体的第一基底100的平面示意图，其中相同于前述图7及8的实施例的部件使用相同的标号并省略其说明。图3中的第一基底100的结构类似于图7中的第一基底100的结构，差异在于图3中的第一基底100仅具有一个凹口200，邻接于第一基底100的侧边101。再者，从俯视方向来看，各个重布线层220具有相同的宽度及长度，且不具有图7中的扩大部220a。
图4中的第一基底100的结构类似于图3中的第一基底100的结构，差异在于图4中的第一基底100的凹口200横跨侧边101的全部长度而延伸至第一基底100的角落。再者，第一基底100具有邻近于侧边102、103及104的第三导电垫140。对应地电性连接至邻近于侧边102、103及104的第三导电垫140的重布线层220的长度大于对应地电性连接至邻近于侧边101的第三导电垫140的重布线层220的长度。另外，重布线层220从第三导电垫140延伸至凹口200底部的延伸路径可为直线或曲折的。
在图4的实施例中，由于凹口200横跨侧边101的全部长度而延伸至第一基底100的角落，因此可减少应力而避免第一基底100破裂，且使得与距离第一基底100的角落较近的第三导电垫140电性连接的重布线层220可直接延伸至凹口200内，进而有效缩短重布线层220的导电路径，增加信号传递速度，且可节省重布线层220所占用的第一基底100的表面面积。
图5中的第一基底100的结构类似于图4中的第一基底100的结构，差异在于图5中的第一基底100的凹口200除了横跨侧边101的全部长度之外，还进一步横跨相邻于侧边101的侧边102的全部长度。
图6中的第一基底100的结构类似于图3中的第一基底100的结构，差异在于图6中的第一基底100内除了具有邻接于侧边101的凹口200之外，还具有另一凹口200，与相邻于侧边101的侧边102邻接。再者，从俯视方向来看，图3中的重布线层220的宽度皆小于第三导电垫140的宽度，且各个重布线层220的长度皆相同，然而图6中的重布线层220的宽度可小于、等于或大于第三导电垫140的宽度，且各个重布线层220的长度可相同或不同。
在上述实施例中，由于凹口200同时横跨侧边101及102的全部长度(如图5所示)或第一基底100内同时具有邻接于侧边101及102两个凹口200(如图6所示)，使得与邻近于侧边102的第三导电垫140电性连接的重布线层220可直接延伸至横跨侧边102的凹口200，而无需延伸至距离较远的侧边101，因此可有效缩短导电路径，增加信号传递速度，且可节省重布线层220所占用的第一基底100的表面面积，进而增加晶片堆叠封装体的输出信号的布局弹性。另外，上述图3至6中的第一基底100的各种实施例可应用于图8及9的各种实施例的晶片堆叠封装体中的第一基底100。
根据上述实施例，晶片堆叠封装体具有凹口200位于第一基底100内且邻接于其侧边101，使得重布线层220可延伸至凹口200的底部，因此当第二基底400接合于第一基底100的第二侧时，能够通过焊线360将凹口200底部上的重布线层220电性连接至第二基底400的第四导电垫410上，且焊线360位于第一基底100的上表面100a与第二基底400之间，而未突出于第一基底100的上表面100a，进而可有效降低晶片堆叠封装体的整体尺寸。
以下配合图1A至1C说明本发明一实施例的晶片堆叠封装体的第一基底的制造方法，其中图1A至1C是绘示出根据本发明一实施例的晶片堆叠封装体的第一基底的制造方法的剖面示意图。
请参照图1A，提供一第一基底100，其具有一第一侧(如第一基底100的底侧)及相对的一第二侧(如第一基底100的顶侧)，且包括多个晶片区110及分离晶片区110的一切割道区120。在本实施例中，第一基底100可为晶片或中介层。在一实施例中，半导体基底100为一硅晶圆，以利于进行晶圆级封装。
可通过微影制程及蚀刻制程，去除位于切割道区120内一部分的第一基底100，以于第一基底100内形成凹口200。在一实施例中，凹口200位于切割道区120内。在另一实施例中，凹口200可延伸至晶片区110内。在一实施例中，凹口200的侧壁倾斜于第一基底100的上表面100a，且凹口200的底部平行于第一基底100的上表面100a。在另一实施例中，凹口200的侧壁倾斜于第一基底100的上表面100a，且凹口200的底部可非平行于第一基底100的上表面100a。在其他实施例中，凹口200的侧壁可垂直于第一基底100的上表面100a，且凹口200的底部可平行或非平行于第一基底100的上表面100a。另外，凹口200的侧壁及底部可能凹凸不平而呈现锯齿状轮廓。在其他实施例中，可通过进行多次蚀刻制程，在第一基底100内形成由多个连续凹口所构成的多阶凹口(未绘示)。
接着，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)，在第一基底100的上表面100a上形成一钝化护层150，并延伸至凹口200的侧壁及底部上。在本实施例中，钝化护层150可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的介电材料。
请参照图1B，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)及图案化制程(例如，微影及蚀刻制程)，在第一基底100的上表面100a上形成多个重布线层220，并延伸至凹口200的侧壁及底部。在本实施例中，重布线层220可包括铜、铝、金、铂、镍、锡、前述的组合或其他适合的导电材料。
请参照图1C，沿着切割道区120进行切割制程，且从凹口200切割钝化保护层150及第一基底100，以形成彼此分离的多个第一基底100。在另一实施例中，可在进行切割制程之前，先在第一基底100的上表面100a上形成一暂时基底(未绘示，例如玻璃基底或硅晶圆)，且以暂时基底为支撑，对第一基底100的下表面进行薄化制程(例如，机械研磨制程或化学机械研磨制程)，以减少第一基底100的厚度，并有利于后续进行切割制程。
以下配合图2及8说明本发明一实施例的晶片堆叠封装体的制造方法，其中图2是绘示出根据本发明一实施例的具有导电垫的第一基底的剖面示意图，且图8是绘示出根据本发明一实施例的晶片堆叠封装体的剖面示意图。再者，图2及8中相同于前述图1A至1C的实施例的部件使用相同的标号并省略其说明。
图2中的第一基底100的结构类似于图1C中的第一基底100的结构，差异在于图2中的第一基底100内具有多个第三导电垫140，邻近于其上表面100a。在本实施例中，第三导电垫140可为单层导电层或具有多层的导电层结构。再者，在形成钝化护层150之后，可通过微影制程及蚀刻制程，去除位于第三导电垫140上方的钝化护层150的一部分，以暴露出部分的第三导电垫140。再者，重布线层220设置于暴露出的第三导电垫140上，且局部覆盖第三导电垫140。另外，重布线层220也可完全覆盖第三导电垫140。
接着，请参照图8，在对具有第三导电垫140的第一基底100进行切割制程之后，在第一基底100的第一侧提供一第二基底400。在本实施例中，第二基底400可为晶片、中介层或电路板。第二基底400内可具有多个第四导电垫410，邻近于其上表面400a。在本实施例中，第四导电垫410可为单层导电层或具有多层的导电层结构。此处，仅以单层导电层作为范例说明。
接着，可通过打线接合(wire bonding)制程，在第一基底100的凹口200内重布线层220上对应形成多个焊线360，并延伸至第二基底400的第四导电垫410上，以将重布线层220电性连接至对应的第四导电垫410。在本实施例中，焊线360位于第一基底100的上表面100a与第二基底400的上表面400a之间，且焊线360的最高高度H低于第一基底100的上表面100a。
接着，在第一基底100的第二侧提供一装置基底300。在本实施例中，装置基底300可为晶片，且可具有感测装置(未绘示)位于其上表面300a上。在一实施例中，上述感测装置可包括生物特征感测元件(例如，指纹辨识元件)、影像感测元件或其他适合的感测元件。在本实施例中，装置基底300内具有多个第一导电垫310，邻近于其上表面300a。在本实施例中，第一导电垫310可为单层导电层或具有多层的导电层结构，且可通过内连线结构(未绘示)而与装置基底300上的感测装置(未绘示)电性连接。此处，仅以单层导电层作为范例说明。
再者，在将装置基底300接合至第一基底100之前，可先通过微影制程及蚀刻制程(例如，干蚀刻制程、湿蚀刻制程、等离子蚀刻制程、反应性离子蚀刻制程或其他适合的制程)，在装置基底300内形成多个开口，自装置基底300的下表面300b朝上表面300a延伸，以分别暴露出邻近于上表面300a的每一第一导电垫310。
接着，可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程)，在装置基底300的下表面300b上形成一绝缘层320，并延伸至装置基底300的开口内。在本实施例中，绝缘层320可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。
接着，可通过微影制程及蚀刻制程，去除装置基底300的开口底部上的绝缘层320，以暴露出第一导电垫310的表面。可通过沉积制程(例如，涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程)、微影制程及蚀刻制程，在绝缘层320上形成图案化的导电层330。图案化的导电层330延伸进入装置基底300的开口内，以电性接触暴露出的第一导电垫310，且通过绝缘层320与装置基底300电性隔离。因此，装置基底300的开口内的导电层330为硅通孔电极。在本实施例中，导电层330可包括铜、铝、金、铂、镍、锡、前述的组合或其他适合的导电材料。
接着，可通过沉积制程，在图案化的导电层330上形成一钝化保护层340，且填入装置基底300的开口内，以覆盖导电层330。可通过微影制程及蚀刻制程，在钝化保护层340内形成多个开口，以暴露出位于装置基底300的下表面300b上的导电层330的一部分。在本实施例中，钝化保护层340可包括环氧树脂、绿漆、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的绝缘材料。在另一实施例中，钝化保护层340可包括光阻材料，且可通过曝光及显影制程，于其中形成开口。
接着，在钝化保护层340的开口内形成第一导电结构350，以直接接触暴露出的导电层330，而与图案化的导电层330电性连接。举例来说，可通过电镀制程、网版印刷制程或其他适合的制程，在钝化保护层340的开口内形成焊料(solder)，且进行回焊(reflow)制程，以形成第一导电结构350。在本实施例中，第一导电结构350可为焊球、凸块或导电柱，且可包括锡、铅、铜、金、镍、前述的组合或其他适合的导电材料。
接着，装置基底300通过第一导电结构350接合至第一基底100上，且第一导电结构350电性接触第一基底100上对应的重布线层220，如图8所示。
在另一实施例中，如图9所示，在将第二基底400接合至第一基底100之前，可通过类似于上述装置基底300的开口、绝缘层320、图案化的导电层330、钝化保护层340、第一导电结构350的制程，在第二基底400内形成开口，且在第二基底400上依序形成一绝缘层420、一图案化的导电层430、一钝化保护层440、多个第二导电结构450。
接着，在第一基底100的第一侧提供一第三基底500，且第二基底400位于第一基底100与第三基底500之间。在本实施例中，第三基底500可为晶片、中介层或电路板。第三基底500内具有多个第二导电垫510，邻近于其上表面500a，且可为单层导电层或具有多层的导电层结构。此处，仅以单层导电层作为范例说明。
第二导电垫510通过第二导电结构450及第二基底400内的硅通孔电极(即，导电层430)电性连接至第四导电垫410。另外，第二导电垫510也可通过其他导电层与第二导电结构450电性连接，而未直接接触第二导电结构450。在其他实施例中，当第二基底400为中介层或电路板时，第二基底400内可包括由介电层、介电层内的金属接触窗及介层插塞所构成的内连接结构(未绘示)，且第二导电垫510可通过第二导电结构450及内连接结构而电性连接至第四导电垫410。
相较于使用焊球作为第一基底与第二基底之间的导电结构，或将焊线形成于第一基底的上表面而延伸至第二基底上，本发明的实施例通过在第一基底100内形成凹口200，且将重布线层220延伸至凹口200的底部。如此一来，第一基底100的上表面100a与第二基底400之间能够提供足够的空间来形成焊线360，并使得焊线360不会突出于第一基底100的上表面100a，因此可有效降低晶片堆叠封装体的整体尺寸。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (18)

1.一种晶片堆叠封装体，其特征在于，包括：
至少一第一基底，其具有一第一侧及相对的一第二侧，且包括：
一凹口，位于该至少一第一基底内且邻接该至少一第一基底的一侧边；以及
多个重布线层，设置于该至少一第一基底上且延伸至该凹口的一底部；
至少一第二基底，设置于该至少一第一基底的该第一侧；
多个焊线，对应设置于该凹口内的所述重布线层上，且延伸至该至少一第二基底上；
至少一装置基底，设置于该至少一第一基底的该第二侧；以及
一第三基底，设置于该至少一第一基底的该第一侧，且该至少一第二基底位于该至少一第一基底与该第三基底之间。
2.根据权利要求1所述的晶片堆叠封装体，其特征在于，该至少一装置基底内具有多个第一导电垫，所述第一导电垫通过多个第一导电结构电性连接至所述重布线层。
3.根据权利要求1所述的晶片堆叠封装体，其特征在于，该至少一装置基底为晶片。
4.根据权利要求1所述的晶片堆叠封装体，其特征在于，该至少一第一基底为晶片或中介层。
5.根据权利要求1所述的晶片堆叠封装体，其特征在于，该至少一第二基底为晶片、中介层或电路板。
6.根据权利要求1所述的晶片堆叠封装体，其特征在于，该第三基底具有多个第二导电垫，所述第二导电垫通过多个第二导电结构电性连接至所述焊线。
7.根据权利要求1所述的晶片堆叠封装体，其特征在于，该第三基底为晶片、中介层或电路板。
8.根据权利要求1所述的晶片堆叠封装体，其特征在于，从俯视方向来看，所述重布线层中的至少两个具有相同或不同的宽度及/或长度。
9.根据权利要求1所述的晶片堆叠封装体，其特征在于，所述重布线层中的至少两个延伸至该凹口内的一端具有一扩大部，且所述扩大部具有相同或不同的尺寸及/或形状。
10.一种晶片堆叠封装体的制造方法，其特征在于，包括：
提供至少一第一基底，该至少一第一基底具有一第一侧及相对的一第二侧，且包括：
一凹口，位于该至少一第一基底内且邻接该至少一第一基底的一侧边；以及
多个重布线层，设置于该至少一第一基底上且延伸至该凹口的一底部；
在该至少一第一基底的该第一侧提供至少一第二基底；
在该凹口内的所述重布线层上对应形成多个焊线，并延伸至该至少一第二基底上；
在该至少一第一基底的该第二侧提供至少一装置基底；以及
在该至少一第一基底的该第一侧提供一第三基底，其中该至少一第二基底位于该至少一第一基底与该第三基底之间。
11.根据权利要求10所述的晶片堆叠封装体的制造方法，其特征在于，该至少一装置基底内具有多个第一导电垫，且该晶片堆叠封装体的制造方法还包括在该至少一第一基底与该至少一装置基底之间形成多个第一导电结构，以将所述第一导电垫电性连接至所述重布线层。
12.根据权利要求10所述的晶片堆叠封装体的制造方法，其特征在于，该至少一装置基底为晶片。
13.根据权利要求10所述的晶片堆叠封装体的制造方法，其特征在于，该至少一第一基底为晶片或中介层。
14.根据权利要求10所述的晶片堆叠封装体的制造方法，其特征在于，该至少一第二基底为晶片、中介层或电路板。
15.根据权利要求10所述的晶片堆叠封装体的制造方法，其特征在于，该第三基底具有多个第二导电垫，且该晶片堆叠封装体的制造方法还包括在该至少一第二基底与该第三基底之间形成多个第二导电结构，以将所述第二导电垫电性连接至所述焊线。
16.根据权利要求10所述的晶片堆叠封装体的制造方法，其特征在于，该第三基底为晶片、中介层或电路板。
17.根据权利要求10所述的晶片堆叠封装体的制造方法，其特征在于，从俯视方向来看，所述重布线层中的至少两个具有相同或不同的宽度及/或长度。
18.根据权利要求10所述的晶片堆叠封装体的制造方法，其特征在于，所述重布线层中的至少两个延伸至该凹口内的一端具有一扩大部，且所述扩大部具有相同或不同的尺寸及/或形状。
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9633960B2 (en) * 2015-06-30 2017-04-25 Sunasic Technologies Inc. Chip with I/O pads on peripheries and method making the same
US9898645B2 (en) 2015-11-17 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor device and method
US10347605B2 (en) 2017-11-28 2019-07-09 International Business Machines Corporation System and method for routing signals in complex quantum systems
KR102435517B1 (ko) * 2018-04-12 2022-08-22 에스케이하이닉스 주식회사 칩 스택 패키지
US11174157B2 (en) * 2018-06-27 2021-11-16 Advanced Semiconductor Engineering Inc. Semiconductor device packages and methods of manufacturing the same
US10985134B2 (en) * 2018-11-09 2021-04-20 Nanya Technology Corporation Method and system of manufacturing stacked wafers
US20200176418A1 (en) * 2018-12-04 2020-06-04 Nanya Technology Corporation Dual-die memory package
US11195809B2 (en) 2018-12-28 2021-12-07 Stmicroelectronics Ltd Semiconductor package having a sidewall connection
US11437337B2 (en) 2020-04-13 2022-09-06 Alibaba Group Holding Limited Using electrical connections that traverse scribe lines to connect devices on a chip
CN114188311A (zh) * 2020-09-15 2022-03-15 联华电子股份有限公司 半导体结构

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7199345B1 (en) * 2004-03-26 2007-04-03 Itt Manufacturing Enterprises Inc. Low profile wire bond for an electron sensing device in an image intensifier tube
CN103715166A (zh) * 2012-10-02 2014-04-09 台湾积体电路制造股份有限公司 用于部件封装件的装置和方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7456088B2 (en) * 2006-01-04 2008-11-25 Stats Chippac Ltd. Integrated circuit package system including stacked die
US8143102B2 (en) * 2007-10-04 2012-03-27 Stats Chippac Ltd. Integrated circuit package system including die having relieved active region
US7985980B2 (en) * 2007-10-31 2011-07-26 Sharp Kabushiki Kaisha Chip-type LED and method for manufacturing the same
US8597963B2 (en) * 2009-05-19 2013-12-03 Intematix Corporation Manufacture of light emitting devices with phosphor wavelength conversion
US8227269B2 (en) * 2009-05-19 2012-07-24 Intematix Corporation Manufacture of light emitting devices with phosphor wavelength conversion
US9437478B2 (en) * 2010-05-11 2016-09-06 Xintec Inc. Chip package and method for forming the same
US8963312B2 (en) * 2010-05-11 2015-02-24 Xintec, Inc. Stacked chip package and method for forming the same
TWI416637B (zh) * 2010-10-15 2013-11-21 Chipmos Technologies Inc 晶片封裝結構及晶片封裝方法
CN102774805B (zh) * 2011-05-13 2015-10-28 精材科技股份有限公司 晶片封装体及其形成方法
US9147670B2 (en) * 2012-02-24 2015-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Functional spacer for SIP and methods for forming the same
US8736080B2 (en) * 2012-04-30 2014-05-27 Apple Inc. Sensor array package
US9153707B2 (en) * 2012-06-11 2015-10-06 Xintec Inc. Chip package and method for forming the same
CN103985683B (zh) * 2013-02-08 2017-04-12 精材科技股份有限公司 晶片封装体
TWI560828B (en) * 2014-02-11 2016-12-01 Xintex Inc Chip package and method for forming the same
TWI575779B (zh) * 2014-03-31 2017-03-21 精材科技股份有限公司 晶片封裝體及其製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7199345B1 (en) * 2004-03-26 2007-04-03 Itt Manufacturing Enterprises Inc. Low profile wire bond for an electron sensing device in an image intensifier tube
CN103715166A (zh) * 2012-10-02 2014-04-09 台湾积体电路制造股份有限公司 用于部件封装件的装置和方法

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