CN104835792B - 晶片封装体及其制造方法 - Google Patents
晶片封装体及其制造方法 Download PDFInfo
- Publication number
- CN104835792B CN104835792B CN201510060529.7A CN201510060529A CN104835792B CN 104835792 B CN104835792 B CN 104835792B CN 201510060529 A CN201510060529 A CN 201510060529A CN 104835792 B CN104835792 B CN 104835792B
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- Prior art keywords
- recess
- conducting wire
- encapsulation body
- wafer encapsulation
- distance
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- 238000000034 method Methods 0.000 title claims abstract description 81
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 claims abstract description 132
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000005538 encapsulation Methods 0.000 claims description 110
- 125000006850 spacer group Chemical group 0.000 claims description 82
- 238000005520 cutting process Methods 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 7
- 238000004806 packaging method and process Methods 0.000 abstract description 12
- 235000012431 wafers Nutrition 0.000 description 101
- 238000002161 passivation Methods 0.000 description 29
- 239000004020 conductor Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- UFWIBTONFRDIAS-UHFFFAOYSA-N Naphthalene Chemical compound C1=CC=CC2=CC=CC=C21 UFWIBTONFRDIAS-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000010897 surface acoustic wave method Methods 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 239000011135 tin Substances 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
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Abstract
本发明提供一种晶片封装体及其制造方法,该晶片封装体包括:一半导体基底;一凹口,位于半导体基底内且邻接半导体基底的一侧边,其中半导体基底具有至少一间隔部,该至少一间隔部突出于凹口的一底部;一导线,设置于半导体基底上,且延伸至凹口内。本发明不仅能够降低与导线电性连接的导电结构的高度,还可减少应力而避免半导体基底破裂,且有效缩短导线的导电路径,进而增加输出信号的布局弹性。另外,由于半导体基底具有突出于凹口的底部的间隔部,因此可避免导线发生短路的问题,进而提升晶片封装体的可靠度。
Description
技术领域
本发明有关于一种晶片封装体及其制造方法,特别为有关于以晶圆级封装制程所形成的晶片封装体。
背景技术
晶片封装制程是形成电子产品过程中的重要步骤。晶片封装体除了将晶片保护于其中,使免受外界环境污染外,还提供晶片内部电子元件与外界的电性连接通路。
制作晶片封装体的过程包括将在基底上形成与导电垫电性连接的多个导线,以及与导线电性连接的外部导电结构(例如,焊线或焊球)。
然而,形成于基底上的外部导电结构使得晶片封装体的整体尺寸增加,而无法进一步缩小晶片封装体的尺寸。
因此,有必要寻求一种新颖的晶片封装体及其制造方法,其能够解决或改善上述的问题。
发明内容
本发明提供一种晶片封装体,包括:一半导体基底;一凹口,位于半导体基底内且邻接半导体基底的一侧边,其中半导体基底具有至少一间隔部,至少一间隔部突出于凹口的一底部;一导线,设置于半导体基底上,且延伸至凹口内。
本发明还提供另一种晶片封装体,包括:一半导体基底;一凹口,位于半导体基底内且邻接半导体基底的一侧边并横跨该侧边,其中凹口的一侧壁具有一第一部分及与第一部分邻接的一第二部分,且从俯视方向来看,第一部分与该侧边之间的一第一距离大于第二部分与该侧边之间的一第二距离;一导线,设置于半导体基底上,且延伸至凹口内。
本发明还提供一种晶片封装体的制造方法,包括:提供一半导体基底;去除半导体基底的一部分,以在半导体基底内形成一凹口且在凹口内形成至少一间隔部,其中间隔部突出于凹口的一底部;在半导体基底上形成一导线,该导线延伸至凹口内。
本发明还提供另一种晶片封装体的制造方法,包括:提供一半导体基底;去除半导体基底的一部分,以在半导体基底内形成一第一凹口,其中第一凹口具有一第一部分及与第一部分邻接的一第二部分,且从俯视方向来看,第一部分的两相对侧壁之间的一第一距离大于第二部分的两相对侧壁之间的一第二距离;在半导体基底上形成一导线,该导线延伸至第一凹口内。
本发明不仅能够降低与导线电性连接的导电结构的高度,还可减少应力而避免半导体基底破裂,且有效缩短导线的导电路径,进而增加输出信号的布局弹性。另外,由于半导体基底具有突出于凹口的底部的间隔部,因此可避免导线发生短路的问题,进而提升晶片封装体的可靠度。
附图说明
图1A至1E绘示出根据本发明一实施例的晶片封装体的制造方法的剖面示意图。
图2绘示出本发明一实施例的晶片封装体的局部立体示意图。
图3及4绘示出本发明各种实施例的晶片封装体的平面示意图。
图5绘示出本发明另一实施例的晶片封装体的制造方法的平面示意图。
图6至10绘示出根据本发明各种实施例的晶片封装体的平面示意图。
其中,附图中符号的简单说明如下:
100 半导体基底;
100a 第一表面;
100b 第二表面;
101、102、103 侧边;
110 晶片区;
115 装置区;
120 切割道区;
130 介电层;
140 开口;
150 导电垫;
160 钝化护层;
200、220 凹口;
200a、200b、200c、200d、200e、200f、200g、200h、220a、220b、220c侧壁部分;
210 底部;
300、310、320 导线;
400、400’ 间隔部;
P1、P2、P3 间距。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是,本发明提供许多可供应用的发明概念,其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式,非用以限制本发明的范围。此外,在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明,不代表所讨论的不同实施例及/或结构之间具有任何关连性。再者,当述及一第一材料层位于一第二材料层上或之上时,包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装微机电系统晶片。然其应用不限于此,例如在本发明的晶片封装体的实施例中,其可应用于各种包含有源元件或无源元件(active or passive elements)、数字电路或模拟电路(digital or analog circuits)等集成电路的电子元件(electronic components),例如是有关于光电元件(optoelectronic devices)、微机电系统(Micro Electro Mechanical System;MEMS)、微流体系统(micro fluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package;WSP)制程对影像感测元件、发光二极管(light-emitting diodes;LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(microactuators)、表面声波元件(surface acoustic wave devices)、压力感测器(processsensors)或喷墨头(ink printer heads)等半导体晶片进行封装。
其中上述晶圆级封装制程主要是指在晶圆阶段完成封装步骤后,再予以切割成独立的封装体,然而,在一特定实施例中,例如将已分离的半导体晶片重新分布在一承载晶圆上,再进行封装制程,亦可称之为晶圆级封装制程。另外,上述晶圆级封装制程亦适用于通过堆叠(stack)方式安排具有集成电路的多片晶圆,以形成多层集成电路(multi-layerintegrated circuit devices)的晶片封装体。
请参照图1E及2,其分别绘示出根据本发明一实施例的晶片封装体的剖面示意图及局部立体示意图。为了清楚显示相对位置关系,图2中并未绘示出图1E中的介电层130及钝化护(passivation)层160。
在本实施例中,晶片封装体包括一半导体基底100、一凹口200、一间隔部400及多个导线300及310。半导体基底100具有一第一表面100a及与其相对的一第二表面100b,且包括多个晶片区110及分离晶片区110的一切割道区120。每一晶片区110内包括一装置区115,装置区115内可包括感测元件(未绘示),例如影像感测元件。切割道区120用以分离出多个晶片封装体。在一实施例中,半导体基底100为一硅晶圆,以利于进行晶圆级封装。
在本实施例中,半导体基底100的每一晶片区110中具有多个导电垫150,设置于第一表面100a上。导电垫150可为单层导电层或具有多层的导电层结构,且通过内连线结构(未绘示)而与装置区115内的感测元件电性连接。
在本实施例中,晶片封装体还包括一介电层130,设置于半导体基底100的第一表面100a上。介电层130覆盖导电垫150,且具有露出导电垫150的开口。介电层130可包括单层介电层或具有多层的介电层结构。在本实施例中,介电层130可包括氧化物、氮化物或其他适合的介电材料。
凹口200位于半导体基底100内且邻接于晶片封装体的半导体基底100的一侧边101(如图2所示),并自第一表面100a朝第二表面100b延伸。在本实施例中,凹口200的侧壁可垂直或倾斜于半导体基底100的第一表面100a,且凹口200的底部可平行或非平行于半导体基底100的第一表面100a。在一实施例中,凹口200的侧壁及底部210可能凹凸不平而呈现锯齿状轮廓。在其他实施例中,半导体基底100内可具有由多个连续凹口所构成的多阶凹口(未绘示)。
间隔部400突出于凹口200的底部210,如图2所示。间隔部400为半导体基底100的一部分,因此间隔部400的高度等于或小于凹口200的深度。另外,可以理解的是,图式中间隔部400的数量及外型仅作为范例说明,并不限定于此,其实际数量及外型取决于设计需求。
在本实施例中,晶片封装体还包括一钝化护层160,设置于介电层130上,且延伸至介电层130的开口内而覆盖导电垫150的一部分。钝化护层160更进一步延伸至凹口200的侧壁及底部210及凹口200内的间隔部400上。在一实施例中,钝化护层160未覆盖间隔部400的顶部。在本实施例中,钝化护层160可包括环氧树脂、无机材料(例如,氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如,聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的介电材料。
导线300及导线310(绘示于图2)设置于钝化护层160上,且延伸至从钝化护层160露出的导电垫150上而与其电性连接。导线300及310更进一步延伸至凹口200的侧壁及底部210上。在一实施例中,导线300及310可仅延伸至凹口200的侧壁上。在本实施例中,导线300及310可包括铜、铝、金、铂、镍、锡、前述的组合或其他适合的导电材料。
在一实施例中,间隔部400沿着导线300及310的延伸方向而延伸至侧边101,且间隔部400位于导线300及310之间,如图2所示。在另一实施例中,晶片封装体的半导体基底100可具有间隔排列的多个间隔部400,间隔部400之间可具有相同的间距P1及P2(如图3所示),也可具有不同的间距P1及P3(如图4所示)。在一实施例中,导线300及310可分别延伸至间隔部400中的任两者之间,且导线300及310之间具有一间隔部400,如图3所示。又另一实施例中,导线300及310之间可具有多个间隔部400,如图4所示。在一实施例中,如图10所示,导线300可延伸至两间隔部400’之间,且两间隔部400’之间的间距不大于导线300的宽度,使得导线300与两间隔部400’相连。再者,导线320可延伸至间隔部400与间隔部400’之间,且间隔部400与间隔部400’之间的间距大于导线320的宽度,而导线320具有与间隔部400’邻接的一侧边。
在本实施例中,晶片封装体可进一步设置于一电路板(未绘示)上,且通过导电结构(未绘示,例如焊线或焊球),将延伸至凹口200内的导线300及310电性连接至电路板。
根据上述实施例,晶片封装体具有凹口位于半导体基底内,使得导线可延伸至凹口内,因此当晶片封装体的导线通过导电结构与电路板电性连接时,能够降低导电结构的高度,进而有效降低晶片封装体的整体尺寸。另外,由于半导体基底具有间隔部突出于凹口的底部且位于两导线之间,因此可避免导线发生短路的问题,进而提升晶片封装体的可靠度。
请参照图1E及6,其分别绘示出根据本发明另一实施例的晶片封装体的剖面示意图及平面示意图,其中相同于前述图1E及2的实施例的部件使用相同的标号并省略其说明。为了清楚显示相对位置关系,图6中并未绘示出图1E中的介电层130及钝化护层160。
在本实施例中,晶片封装体包括一半导体基底100、一凹口200及多个导线300。半导体基底100具有一第一表面100a及与其相对的一第二表面100b,且包括一装置区115。装置区115内可包括感测元件(未绘示),例如影像感测元件。在一实施例中,半导体基底100为一硅晶圆,以利于进行晶圆级封装。
在本实施例中,半导体基底100的每一晶片区110中具有多个导电垫150,设置于第一表面100a上。导电垫150可通过内连线结构(未绘示)而与装置区115内的感测元件电性连接。在本实施例中,晶片封装体还包括一介电层130,设置于半导体基底100的第一表面100a上。介电层130覆盖导电垫150,且具有露出导电垫150的开口。
凹口200位于半导体基底100内且自第一表面100a朝第二表面100b延伸。凹口200邻接于晶片封装体的半导体基底100的一侧边101,且横跨侧边101的全部长度(如图6所示)。凹口200具有一侧壁部分200a及与其邻接的另一侧壁部分200b,且从俯视方向来看,侧壁部分200a与侧边101之间的距离大于侧壁部分200b与侧边101之间的距离。在另一实施例中,侧壁部分200a与侧边101之间的距离可小于侧壁部分200b与侧边101之间的距离。另外,可以理解的是,图式中侧壁部分的数量、侧壁部分与侧边之间的距离、导线的延伸方向及导电垫的位置仅作为范例说明,并不限定于此。
在本实施例中,晶片封装体还包括一钝化护层160,设置于介电层130上,且延伸至介电层130的开口内而覆盖导电垫150的一部分。钝化护层160更进一步延伸至凹口200的侧壁及底部210上。
导线300设置于钝化护层160上,且延伸至从钝化护层160露出的导电垫150而与其电性连接。导线300更进一步延伸至凹口200的侧壁及底部210上。在一实施例中,导线300可仅延伸至凹口200的侧壁上。在本实施例中,导线300可延伸至凹口200的第一部分200a或第二部分200b。
根据上述实施例,由于凹口200横跨侧边101的全部长度而延伸至半导体基底100的角落,因此可减少应力而避免半导体基底破裂,且使得距离凹口200的侧壁部分200a较远的导线可直接延伸至凹口200的侧壁部分200b,进而有效缩短导线的导电路径,增加信号传递速度,且可节省导线所占用的半导体基底100的表面面积。
请参照图7至10,其绘示出根据本发明各种实施例的晶片封装体的平面示意图,其中相同于图6中的部件使用相同的标号并省略其说明。为了清楚显示相对位置关系,图7至10中并未绘示出图1E中的介电层130及钝化护层160。
图7中的晶片封装体的结构类似于图6中的晶片封装体的结构,差异在于图7中的凹口200又具有另一侧壁部分200c,邻接于侧壁部分200b,且从俯视方向来看,侧壁部分200c与侧边101之间的距离大于侧壁部分200a与侧边101之间的距离且大于侧壁部分200b与侧边101之间的距离。
在另一实施例中,侧壁部分200c与侧边101之间的距离可大于侧壁部分200b与侧边101之间的距离且小于或等于侧壁部分200a与侧边101之间的距离。又另一实施例中,侧壁部分200c与侧边101之间的距离可小于侧壁部分200b与侧边101之间的距离且相同或不同于侧壁部分200a与侧边101之间的距离。
图8中的晶片封装体的结构类似于图7中的晶片封装体的结构,差异在于凹口200更横跨半导体基底100中与侧边101相邻的一侧边102。在另一实施例中,凹口200可横跨半导体基底100中与侧边101相邻的两侧边。在本实施例中,凹口200具有横跨至侧边102的侧壁部分200d、200e、200f、200g及200h。从俯视方向来看,侧壁部分200d与侧边102之间的距离大于邻接的侧壁部分200e与侧边101之间的距离。侧壁部分200d与侧边102之间的距离等于侧壁部分200a与侧边101之间的距离,且侧壁部分200e与侧边102之间的距离等于侧壁部分200b与侧边101之间的距离。
再者,侧壁部分200f与侧边102之间的距离大于邻接的侧壁部分200g与侧边102之间的距离。侧壁部分200f及200g与侧边102之间的距离大于侧壁部分200a及200b与侧边101之间的距离。在另一实施例中,侧壁部分200f与侧边102之间的距离可等于或小于侧壁部分200a与侧边101之间的距离且相同或不同于侧壁部分200b与侧边101之间的距离。在另一实施例中,侧壁部分200g与侧边102之间的距离可等于或小于侧壁部分200a与侧边101之间的距离且相同或不同于侧壁部分200b与侧边101之间的距离。
再者,侧壁部分200h与侧边102之间的距离大于邻接的侧壁部分200g与侧边102之间的距离且小于侧壁部分200f与侧边102之间的距离。在另一实施例中,侧壁部分200h与侧边102之间的距离可大于侧壁部分200g与侧边102之间的距离且大于或等于侧壁部分200f与侧边102之间的距离。又另一实施例中,侧壁部分200h与侧边102之间的距离可小于侧壁部分200g与侧边102之间的距离且相同或不同于侧壁部分200f与侧边102之间的距离。
在一实施例中,导线(例如,导线300)可直接延伸至凹口200的侧壁部分200a,且导线(例如,导线320)可延伸至凹口200的侧壁部分200d。
根据上述实施例,由于凹口200更横跨半导体基底100的侧边102,使得邻近于侧边102的导线可直接延伸至凹口200的侧壁部分200d、200e、200f、200g或200h,而无需延伸至距离较远的侧边101,因此可有效缩短导线的导电路径,增加信号传递速度,且可节省导线所占用的半导体基底100的表面面积。
图9中的晶片封装体的结构类似于图7中的晶片封装体的结构,差异在于晶片封装体还包括另一凹口220,位于半导体基底100内且自第一表面100a朝第二表面100b延伸。凹口220与相对于且平行侧边101的一侧边103邻接,且横跨侧边103的全部长度。
凹口220具有一侧壁部分220a及与其邻接的一侧壁部分220b,且从俯视方向来看,侧壁部分220a与侧边103之间的距离大于侧壁部分220b与侧边103之间的距离。侧壁部分220a及220b与侧边103之间的距离大于侧壁部分200a及200b与侧边101之间的距离。在另一实施例中,侧壁部分220a与侧边103之间的距离可等于或小于侧壁部分200a与侧边101之间的距离且相同或不同于侧壁部分200b与侧边101之间的距离。在另一实施例中,侧壁部分220b与侧边103之间的距离可等于或小于侧壁部分200a与侧边101之间的距离且相同或不同于侧壁部分200b与侧边101之间的距离。
在本实施例中,凹口220又具有另一侧壁部分220c,邻接于侧壁部分220b,且从俯视方向来看,侧壁部分220c与侧边103之间的距离大于侧壁部分220b与侧边103之间的距离且小于侧壁部分220a与侧边103之间的距离。在另一实施例中,侧壁部分220c与侧边103之间的距离可大于侧壁部分220b与侧边103之间的距离且大于或等于侧壁部分220a与侧边103之间的距离。又另一实施例中,侧壁部分220c与侧边103之间的距离可小于侧壁部分220b与侧边103之间的距离且相同或不同于侧壁部分220a与侧边103之间的距离。
虽然未绘示于图式中,只要凹口横跨半导体基底的一侧边且具有多个侧壁部分与对应的侧边之间的距离不同,侧壁部分的数量、侧壁部分与对应的侧边之间的距离大小、导线的延伸方向及导电垫的位置皆可具有其他的配置方式。另外,由于凹口横跨半导体基底的侧边的全部长度或宽度,因此可增加晶片封装体的输出信号的布局弹性。
上述图2至4中的晶片封装体的各种实施例可应用于图6至10的各种实施例的晶片封装体。举例来说,图10中的晶片封装体的结构类似于图9中的晶片封装体的结构,差异在于晶片封装体的半导体基底100具有多个间隔部400及400’,突出于凹口200及220的底部。间隔部之间可具有相同或不同的间距,且可从凹口200及220的任一侧壁部分沿着导线300的延伸方向而延伸至侧边101或103。
在一实施例中,导线300可延伸至两间隔部400’之间,且两间隔部400’之间的间距不大于导线300的宽度,使得导线300与两间隔部400’相连。再者,导线320可延伸至间隔部400与间隔部400’之间,且间隔部400与间隔部400’之间的间距大于导线320的宽度,而导线320具有与间隔部400’邻接的一侧边。
以下配合图1A至1E及图2至4说明本发明各种实施例的晶片封装体的制造方法,其中图1A至1E绘示出根据本发明一实施例的晶片封装体的制造方法的剖面示意图,图2绘示出根据本发明一实施例的晶片封装体的局部立体示意图,且图3及4绘示出根据本发明不同实施例的晶片封装体的平面示意图。为了清楚显示相对位置关系,图2至4中并未绘示出介电层130及钝化护层160。
请参照图1A,提供一半导体基底100,其具有一第一表面100a及与其相对的一第二表面100b,且包括多个晶片区110及分离晶片区110的一切割道区120。每一晶片区110内包括一装置区115,装置区115内可包括感测元件(未绘示),例如影像感测元件。切割道区120于后续制程中用以分离出多个晶片封装体。在一实施例中,半导体基底100为一硅晶圆,以利于进行晶圆级封装。
在本实施例中,多个导电垫150及一介电层130依序设置于晶片区110内的半导体基底100的第一表面100a上。导电垫150可为单层导电层或具有多层的导电层结构,且通过内连线结构(未绘示)而与装置区115内的感测元件电性连接。介电层130覆盖导电垫150,且具有露出导电垫150的开口。介电层130可包括单层介电层或具有多层的介电层结构。在本实施例中,介电层130可包括氧化物或其他适合的介电材料。
请参照图1B,可通过微影制程及蚀刻制程,去除位于切割道区120内一部分的介电层130,以于介电层130内形成开口140,其露出位于切割道区120内的半导体基底100。
请参照图1C,可通过微影制程及蚀刻制程,去除开口140内的半导体基底100的一部分,以于半导体基底100内形成一凹口200,自第一表面100a朝第二表面100b延伸。在一实施例中,凹口200位于切割道区120内。在另一实施例中,凹口200可延伸至晶片区110内。在本实施例中,凹口200的侧壁可垂直或倾斜于半导体基底100的第一表面100a,且凹口200的底部可平行或非平行于半导体基底100的第一表面100a。在一实施例中,凹口200的侧壁及底部210可能凹凸不平而呈现锯齿状轮廓。在其他实施例中,可通过进行多次蚀刻制程,在半导体基底100内形成由多个连续凹口所构成的多阶凹口(未绘示)。
在本实施例中,在进行上述蚀刻制程之后,一部分的半导体基底100未被去除而保留于凹口200内,使得半导体基底100具有一间隔部400,突出于凹口200的底部210,如图2所示。由于间隔部400为半导体基底100的一部分,因此间隔部400的高度等于或小于凹口200的深度。在另一实施例中,半导体基底100可具有间隔排列的多个间隔部400,间隔部400之间可具有相同的间距P1及P2(如图3所示),也可具有不同的间距P1及P3(如图4所示)。
请参照图1D,可通过沉积制程(例如,涂布制程、物理气相沉积制程、化学气相沉积制程或其他适合的制程),在介电层130上形成一钝化护层160。钝化护层160延伸至介电层130的开口内而覆盖导电垫150,且进一步延伸至凹口200的侧壁及底部210及凹口200内的间隔部400上。在一实施例中,可通过回蚀制程,选择性去除形成于间隔部400的顶部的钝化护层160。
在本实施例中,钝化护层160可包括环氧树脂、无机材料(例如,氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如,聚酰亚胺树脂、苯环丁烯、聚对二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他适合的介电材料。接着,可通过微影制程及蚀刻制程,去除位于导电垫150上方的钝化护层160的一部分,以露出部分的导电垫150。
请参照图1E,可通过沉积制程(例如,涂布制程、物理气相沉积制程、化学气相沉积制程、电镀制程、无电镀制程或其他适合的制程),在钝化护层160上形成多个导线300及导线310(绘示于图2)。导线300延伸至露出的导电垫150而与其电性连接,并进一步延伸至凹口200的侧壁及底部210上。在另一实施例中,导线300可仅延伸至凹口200的侧壁上。在本实施例中,导线300可包括铜、铝、金、铂、镍、锡、前述的组合或其他适合的导电材料。
请再参照图2,导线300及导线310的延伸方向相同于间隔部400的延伸方向,且间隔部400位于导线300及导线310之间。在另一实施例中,导线300及导线310分别延伸至多个间隔部400中的两者之间,如图3所示。又另一实施例中,导线300及导线310之间可具有多个间隔部400,如图4所示。
接着,沿着切割道区120进行切割制程,且从凹口200切割钝化护层160、间隔部400及半导体基底100,以形成彼此分离的多个晶片封装体。在另一实施例中,可在进行切割制程之前,先在半导体基底100的第一表面100a上形成一暂时基底(未绘示,例如玻璃基底或硅晶圆),且以暂时基底为支撑,对半导体基底100的第二表面100b进行薄化制程(例如,机械研磨制程或化学机械研磨制程),以减少半导体基底100的厚度,并有利于后续进行切割制程。
在本实施例中,晶片封装体可进一步设置于一电路板(未绘示)上,且通过导电结构(未绘示,例如焊线或焊球),将延伸至凹口200内的导线300电性连接至电路板。
以下配合图1A至1E及图5至10说明本发明各种实施例的晶片封装体的制造方法,其中图5绘示出根据本发明另一实施例的晶片封装体的制造方法的平面示意图,且图6至10绘示出根据本发明不同实施例的晶片封装体的平面示意图。为了清楚显示相对位置关系,图5至10中并未绘示出介电层130及钝化护层160。
请参照图1A,在一半导体基底100的第一表面100a上设置多个导电垫150且于其上形成一介电层130。接着,请参照图1B,对切割道区120内的介电层130进行蚀刻制程,以于介电层130内形成一开口140,且露出一部分的半导体基底100。接着,请参照图1C,对开口140内的半导体基底100进行蚀刻制程,以于半导体基底100内形成一凹口200,自第一表面100a朝相对的第二表面100b延伸。
在本实施例中,凹口200具有一第一部分及与其邻接的一第二部分,且从俯视方向来看,第一部分的两相对侧壁之间的第一距离大于第二部分的两相对侧壁之间的第二距离,如图5所示。
接着,请参照图1D,可通过沉积、微影及蚀刻制程,在介电层130上形成图案化的一钝化护层160。钝化护层160延伸至介电层130的开口内且覆盖一部分的导电垫150,而露出导电垫150。钝化护层160更进一步延伸至凹口200的侧壁及底部210。
请参照图1E,可通过沉积制程,在钝化护层160上形成多个导线300。导线300延伸至露出的导电垫150而与其电性连接,并进一步延伸至凹口200的侧壁及底部210上。
接着,沿着切割道区120进行切割制程,且从凹口200切割钝化护层160及半导体基底100,以形成彼此分离的多个晶片封装体。图6绘示出对图5中的半导体基底100进行切割制程后所形成的晶片封装体。
在另一实施例中,在进行切割制程之前,半导体基底100内的凹口200还包括一第三部分,邻接于第二部分,且从俯视方向来看,第三部分的两相对侧壁之间的第三距离相同或不同于第一距离且不同于第二距离。图7绘示出对上述半导体基底100(其凹口200具有第一、第二及第三部分)进行切割制程后所形成的晶片封装体。
又另一实施例中,对开口140内的半导体基底100进行蚀刻制程的步骤包括在半导体基底100内形成一第一凹口及与其垂直及邻接的一第二凹口。第一凹口具有一第一部分及与其邻接的一第二部分,且从俯视方向来看,第一部分的两相对侧壁之间的第一距离大于第二部分的两相对侧壁之间的第二距离。第二凹口具有一第一部分及与其邻接的一第二部分,且从俯视方向来看,第二凹口的第一部分的两相对侧壁之间的第三距离不同于第二凹口的第二部分的两相对侧壁之间的第四距离。在一实施例中,第三距离或第四距离相同或不同于第二距离。在另一实施例中,第三距离或第四距离相同或不同于第一距离。图8绘示出对上述半导体基底100进行切割制程后所形成的晶片封装体。在此实施例中,第一凹口及第二凹口构成凹口200。
又另一实施例中,对开口140内的半导体基底100进行蚀刻制程的步骤还包括在半导体基底100内形成一第一凹口200及与其平行的一第二凹口220。第一凹口200具有一第一部分及与其邻接的一第二部分,且从俯视方向来看,第一凹口200的第一部分的两相对侧壁之间的第一距离大于第一凹口200的第二部分的两相对侧壁之间的第二距离。第二凹口220具有一第一部分及与其邻接的一第二部分,且从俯视方向来看,第二凹口220的第一部分的两相对侧壁之间的第三距离不同于第二凹口220的第二部分的两相对侧壁之间的第四距离。在一实施例中,第三距离或第四距离相同或不同于第二距离。在另一实施例中,第三距离或第四距离相同或不同于第一距离。图9绘示出对上述半导体基底100进行切割制程后所形成的晶片封装体。
在其他实施例中,对开口140内的半导体基底100进行蚀刻制程而形成凹口200或220的步骤可包括在凹口200或220内保留一部分的半导体基底100,使得半导体基底100具有至少一间隔部400,突出于凹口200或220的底部。再者,在后续的切割制程中,从凹口200或220切割钝化护层160、间隔部400及半导体基底100,以形成彼此分离的多个晶片封装体,如图10所示。
根据上述实施例,晶片封装体具有凹口位于半导体基底内,使得导线可延伸至凹口内,因此能够降低与导线电性连接的导电结构的高度,进而有效降低晶片封装体的整体尺寸。再者,由于凹口横跨半导体基底的侧边而延伸至半导体基底的角落,因此可减少应力而避免半导体基底破裂,且有效缩短导线的导电路径,进而增加输出信号的布局弹性。再者,由于半导体基底具有间隔部突出于凹口的底部且位于两导线之间,因此可避免导线发生短路的问题,进而提升晶片封装体的可靠度。
以上所述仅为本发明较佳实施例,然其并非用以限定本发明的范围,任何熟悉本项技术的人员,在不脱离本发明的精神和范围内,可在此基础上做进一步的改进和变化,因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
Claims (40)
1.一种晶片封装体,其特征在于,包括:
一半导体基底;
一凹口,位于该半导体基底内且邻接该半导体基底的一侧边,其中该半导体基底具有至少一间隔部,该至少一间隔部突出于该凹口的一底部,且该至少一间隔部与该半导体基底由相同的材料所形成;以及
一导线,设置于该半导体基底上,且延伸至该凹口内。
2.根据权利要求1所述的晶片封装体,其特征在于,该至少一间隔部的高度等于或小于该凹口的深度。
3.根据权利要求1所述的晶片封装体,其特征在于,该至少一间隔部沿着该导线的延伸方向而延伸至该侧边。
4.根据权利要求1所述的晶片封装体,其特征在于,还包括另一导线,该另一导线延伸至该凹口内,其中该至少一间隔部位于该导线与该另一导线之间。
5.根据权利要求1所述的晶片封装体,其特征在于,该半导体基底包括间隔排列的多个间隔部,且该导线延伸至所述间隔部中的两者之间。
6.根据权利要求5所述的晶片封装体,其特征在于,还包括另一导线,该另一导线延伸至该凹口内,其中所述间隔部中的至少一个位于该导线与该另一导线之间。
7.根据权利要求5所述的晶片封装体,其特征在于,所述间隔部之间具有相同或不同的间距。
8.一种晶片封装体,其特征在于,包括:
一半导体基底;
一凹口,位于该半导体基底内且邻接该半导体基底的一侧边并横跨该侧边,其中从俯视方向来看,该凹口的一侧壁具有一第一部分及沿着该半导体基底的该侧边的方向与该第一部分邻接的一第二部分,且从该俯视方向来看,该第一部分与该侧边之间的一第一距离大于该第二部分与该侧边之间的一第二距离;以及
一导线,设置于该半导体基底上,且延伸至该凹口内。
9.根据权利要求8所述的晶片封装体,其特征在于,该凹口的该侧壁还包括一第三部分,该第三部分邻接于该第二部分,且从俯视方向来看,该第三部分与该侧边之间的一第三距离相同或不同于该第一距离。
10.根据权利要求8所述的晶片封装体,其特征在于,该凹口还横跨该半导体基底中与该侧边相邻的至少一侧边。
11.根据权利要求10所述的晶片封装体,其特征在于,该凹口具有横跨该至少一侧边的另一侧壁,且该另一侧壁具有一第一部分及与该第一部分邻接的一第二部分,且从俯视方向来看,该另一侧壁的该第一部分与该至少一侧边之间的一第三距离不同于该另一侧壁的该第二部分与该至少一侧边之间的一第四距离。
12.根据权利要求11所述的晶片封装体,其特征在于,该第三距离或该第四距离相同或不同于该第二距离。
13.根据权利要求8所述的晶片封装体,其特征在于,还包括另一凹口,该另一凹口位于该半导体基底内且与相对于该侧边的另一侧边邻接并横跨该另一侧边。
14.根据权利要求13所述的晶片封装体,其特征在于,该另一凹口的一侧壁具有一第一部分及与该第一部分邻接的一第二部分,且从俯视方向来看,该另一凹口的该侧壁的该第一部分与该另一侧边之间的一第三距离不同于该另一凹口的该侧壁的该第二部分与该另一侧边之间的一第四距离。
15.根据权利要求14所述的晶片封装体,其特征在于,该第三距离或该第四距离相同或不同于该第二距离。
16.根据权利要求8所述的晶片封装体,其特征在于,该半导体基底包括至少一间隔部,该至少一间隔部突出于该凹口的一底部。
17.根据权利要求16所述的晶片封装体,其特征在于,还包括另一导线,该另一导线延伸至该凹口内,其中该至少一间隔部位于该导线与该另一导线之间。
18.根据权利要求16所述的晶片封装体,其特征在于,该半导体基底包括间隔排列的多个间隔部,且该导线延伸至所述间隔部中的两者之间。
19.根据权利要求16所述的晶片封装体,其特征在于,还包括另一导线,该另一导线延伸至该凹口内,其中所述间隔部中的至少一个位于该导线与该另一导线之间。
20.一种晶片封装体的制造方法,其特征在于,包括:
提供一半导体基底;
去除该半导体基底的一部分,以在该半导体基底内形成一凹口且在该凹口内形成至少一间隔部,其中该至少一间隔部突出于该凹口的一底部,且该至少一间隔部与该半导体基底由相同的材料所形成;以及
在该半导体基底上形成一导线,该导线延伸至该凹口内。
21.根据权利要求20所述的晶片封装体的制造方法,其特征在于,还包括切割该至少一间隔部及该半导体基底。
22.根据权利要求20所述的晶片封装体的制造方法,其特征在于,该至少一间隔部的高度等于或小于该凹口的深度。
23.根据权利要求20所述的晶片封装体的制造方法,其特征在于,该至少一间隔部沿着该导线的延伸方向而延伸至该半导体基底的一侧边。
24.根据权利要求20所述的晶片封装体的制造方法,其特征在于,还包括在该半导体基底上形成另一导线,该另一导线延伸至该凹口内,其中该至少一间隔部位于该导线与该另一导线之间。
25.根据权利要求20所述的晶片封装体的制造方法,其特征在于,去除该半导体基底的一部分的步骤包括在该凹口内形成间隔排列的多个间隔部,且该导线延伸至所述间隔部中的两者之间。
26.根据权利要求25所述的晶片封装体的制造方法,其特征在于,还包括在该半导体基底上形成另一导线,该另一导线延伸至该凹口内,其中所述间隔部中的至少一个位于该导线与该另一导线之间。
27.根据权利要求20所述的晶片封装体的制造方法,其特征在于,所述间隔部之间具有相同或不同的间距。
28.一种晶片封装体的制造方法,其特征在于,包括:
提供一半导体基底;
去除该半导体基底的一部分,以在该半导体基底内形成一第一凹口,其中该第一凹口具有一第一部分及与该第一部分邻接的一第二部分,且从俯视方向来看,该第一部分的两相对侧壁之间的一第一距离大于该第二部分的两相对侧壁之间的一第二距离,其中从该俯视方向来看,该第二部分沿着平行于该第一部分的两相对侧壁和该第二部分的两相对侧壁的方向邻接该第一部分;以及
在该半导体基底上形成一导线,该导线延伸至该第一凹口内。
29.根据权利要求28所述的晶片封装体的制造方法,其特征在于,还包括从该第一凹口切割该半导体基底。
30.根据权利要求28所述的晶片封装体的制造方法,其特征在于,该第一凹口还包括一第三部分,该第三部分邻接于该第二部分,且从俯视方向来看,该第三部分的两相对侧壁之间的一第三距离相同或不同于该第一距离。
31.根据权利要求28所述的晶片封装体的制造方法,其特征在于,去除该半导体基底的一部分的步骤还包括在该半导体基底内形成一第二凹口,该第二凹口垂直于该第一凹口且与该第一凹口邻接。
32.根据权利要求31所述的晶片封装体的制造方法,其特征在于,该第二凹口具有一第一部分及与该第一部分邻接的一第二部分,且从俯视方向来看,该第二凹口的该第一部分的两相对侧壁之间的一第三距离不同于该第二凹口的该第二部分的两相对侧壁之间的一第四距离。
33.根据权利要求32所述的晶片封装体的制造方法,其特征在于,该第三距离或该第四距离相同或不同于该第二距离。
34.根据权利要求28所述的晶片封装体的制造方法,其特征在于,去除该半导体基底的一部分的步骤还包括在该半导体基底内形成一第二凹口,该第二凹口平行于该第一凹口。
35.根据权利要求34所述的晶片封装体的制造方法,其特征在于,该第二凹口具有一第一部分及与该第一部分邻接的一第二部分,且从俯视方向来看,该第二凹口的该第一部分的两相对侧壁之间的一第三距离不同于该第二凹口的该第二部分的两相对侧壁之间的一第四距离。
36.根据权利要求35所述的晶片封装体的制造方法,其特征在于,该第三距离或该第四距离相同或不同于该第二距离。
37.根据权利要求28所述的晶片封装体的制造方法,其特征在于,去除该半导体基底的一部分的步骤还包括在该第一凹口内形成至少一间隔部,该至少一间隔部突出于该第一凹口的一底部。
38.根据权利要求37所述的晶片封装体的制造方法,其特征在于,还包括在该半导体基底上形成另一导线,该另一导线延伸至该第一凹口内,其中该至少一间隔部位于该导线与该另一导线之间。
39.根据权利要求38所述的晶片封装体的制造方法,其特征在于,去除该半导体基底的一部分的步骤包括在该第一凹口内形成间隔排列的多个间隔部,且该导线延伸至所述间隔部中的两者之间。
40.根据权利要求39所述的晶片封装体的制造方法,其特征在于,还包括在该半导体基底上形成另一导线,该另一导线延伸至该第一凹口内,其中所述间隔部中的至少一个位于该导线与该另一导线之间。
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CN102774805A (zh) * | 2011-05-13 | 2012-11-14 | 精材科技股份有限公司 | 晶片封装体及其形成方法 |
CN103533751A (zh) * | 2012-04-30 | 2014-01-22 | 苹果公司 | 传感器阵列包装 |
CN204441275U (zh) * | 2014-02-11 | 2015-07-01 | 精材科技股份有限公司 | 晶片封装体 |
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