CN105226035B - 晶片封装体 - Google Patents

晶片封装体 Download PDF

Info

Publication number
CN105226035B
CN105226035B CN201510535157.9A CN201510535157A CN105226035B CN 105226035 B CN105226035 B CN 105226035B CN 201510535157 A CN201510535157 A CN 201510535157A CN 105226035 B CN105226035 B CN 105226035B
Authority
CN
China
Prior art keywords
substrate
encapsulation body
wafer encapsulation
body according
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201510535157.9A
Other languages
English (en)
Other versions
CN105226035A (zh
Inventor
林超彦
林义航
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
XinTec Inc
Original Assignee
XinTec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by XinTec Inc filed Critical XinTec Inc
Publication of CN105226035A publication Critical patent/CN105226035A/zh
Application granted granted Critical
Publication of CN105226035B publication Critical patent/CN105226035B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02375—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0616—Random array, i.e. array with no symmetry
    • H01L2224/06164—Random array, i.e. array with no symmetry covering only portions of the surface to be connected
    • H01L2224/06165—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0616—Random array, i.e. array with no symmetry
    • H01L2224/06167—Random array, i.e. array with no symmetry with specially adapted redistribution layers [RDL]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0801—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16105—Disposition relative to the bonding area, e.g. bond pad the bump connector connecting bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10156—Shape being other than a cuboid at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/3701—Effects of the manufacturing process increased through put
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09418—Special orientation of pads, lands or terminals of component, e.g. radial or polygonal orientation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09445—Pads for connections not located at the edge of the PCB, e.g. for flexible circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Human Computer Interaction (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Pressure Sensors (AREA)
  • Micromachines (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供一种晶片封装体，该晶片封装体包括：一下基底；一上基底，具有一上表面及一下表面，且设置于下基底上方；一凹口，邻近于上基底的一侧壁，其中凹口沿着自上基底的上表面朝下表面的一方向而形成；一元件区或感测区，位于上基底的上表面；一导电垫，位于上基底的上表面；以及一导电层电性连接导电垫，且沿着上基底的侧壁延伸至凹口。本发明可大幅缩减晶片封装制程所需的图案化制程，且可显著缩减制程时间与成本。

Description

晶片封装体
本申请是申请日为2011年5月11日、申请号为201110122210.4、发明名称为“晶片封装体及其形成方法”的申请的分案申请。
技术领域
本发明有关于晶片封装体及其形成方法，且特别有关于感测晶片的晶片封装体。
背景技术
传统晶片封装体的制程涉及多道图案化制程与材料沉积制程，不仅耗费生产成本，还需较长的制程时间，因此，业界亟需更为简化与快速的晶片封装技术。
发明内容
本发明提供一种晶片封装体，包括：一下基底；一上基底，具有一上表面及一下表面，且设置于下基底上方；一凹口，邻近于上基底的一侧壁，其中凹口沿着自上基底的上表面朝下表面的一方向而形成；一元件区或感测区，位于上基底的上表面。一导电垫位于上基底的上表面；以及一导电层，电性连接导电垫，且沿着上基底的侧壁延伸至凹口。
本发明提供一种晶片封装体，包括：一承载基底；一半导体基底，具有一上表面及一下表面，且设置于承载基底上方；一元件区或感测区，位于半导体基底内；一导电垫，位于半导体基底的上表面；以及一导电层，电性连接导电垫，且自半导体基底的上表面延伸至半导体基底的一侧壁上，其中半导体基底的侧壁倾斜于半导体基底的上表面。
本发明提供一种晶片封装体，包括：一晶片，该晶片包括一承载基底以及位于承载基底上的一半导体基底；一指纹辨识区以及一导电垫，位于晶片的一前表面；一凹口，形成于晶片的前表面；一导电层，电性连接导电垫，其中导电层沿着凹口的一侧壁而形成；以及一电路板具有一接垫，其中导电层通过一导电结构而与电路板上的接垫电性连接。
本发明提供一种晶片封装体，包括：一承载基底；一半导体基底，具有一上表面及一下表面，且设置于该承载基底之上；一元件区或感测区，位于该半导体基底的该上表面；一导电垫，位于该半导体基底的该上表面；一导电层，电性连接该导电垫，且自该半导体基底的该上表面延伸至该半导体基底的一侧壁上；以及一绝缘层，位于该导电层与该半导体基底之间。
本发明所述的晶片封装体，该半导体基底的该侧壁倾斜于该半导体基底的该上表面。
本发明所述的晶片封装体，该元件区或感测区于该上表面直接露出。
本发明所述的晶片封装体，该导电层延伸进入该承载基底中。
本发明所述的晶片封装体，延伸进入该承载基底中的该导电层包括平行于该半导体基底的该上表面的部分。
本发明所述的晶片封装体，该绝缘层延伸进入该承载基底中。
本发明所述的晶片封装体，还包括一电路板，其中该承载基底设置于该电路板之上，且该导电层通过一导电结构而与该电路板上的一接垫电性连接。
本发明所述的晶片封装体，该导电结构包括一焊球或一焊线。
本发明所述的晶片封装体，该导电结构为一焊球，且该焊球位于该承载基底与该电路板之间的一转角处。
本发明所述的晶片封装体，该元件区或感测区包括一指纹辨识区。
本发明提供一种晶片封装体的形成方法，包括：提供一半导体基底，具有一上表面及一下表面，该半导体基底的该上表面处包括至少一元件区或感测区以及至少一导电垫；提供一承载基底，并将该半导体基底设置于该承载基底之上；自该半导体基底的该上表面形成一凹口；于该半导体基底的该上表面上与该凹口之中形成一绝缘层；于该绝缘层上形成一导电层，该导电层电性连接该导电垫，且自该半导体基底的该上表面延伸至该半导体基底的一侧壁上；以及自该凹口的一底部切断该承载基底以形成多个分离的晶片封装体。
本发明所述的晶片封装体的形成方法，该凹口延伸进入该承载基底之中。
本发明所述的晶片封装体的形成方法，该导电层延伸在该凹口的该底部上。
本发明所述的晶片封装体的形成方法，还包括在形成该凹口之前将该半导体基底薄化。
本发明所述的晶片封装体的形成方法，该半导体基底的薄化包括：在将该半导体基底设置于该承载基底之前，于该半导体基底的该上表面上设置一暂时性承载基底；以及以该暂时性承载基底为支撑，自该半导体基底的该下表面薄化该半导体基底。
本发明所述的晶片封装体的形成方法，还包括在形成该凹口之前，移除该暂时性承载基底。
本发明所述的晶片封装体的形成方法，还包括：提供一电路板，具有一接垫；将该承载基底设置于该电路板之上；以及形成一导电结构，该导电结构电性连接该接垫与该导电层。
本发明所述的晶片封装体的形成方法，该导电结构包括一焊球或一焊线。
本发明所述的晶片封装体的形成方法，该导电结构为一焊球，且该焊球位于该承载基底与该电路板之间的一转角处。
本发明所述的晶片封装体的形成方法，该元件区或感测区于该上表面直接露出。
本发明可大幅缩减晶片封装制程所需的图案化制程，且可显著缩减制程时间与成本。
附图说明
图1A至1D显示根据本发明一实施例的晶片封装体的一系列制程剖面图。
图2显示本发明一实施例的晶片封装体的剖面图。
附图中符号的简单说明如下：
10：晶片封装体；100：半导体基底；100a、100b：表面；102：元件区或感测区；104：导电垫；106：暂时性承载基板；108、112：粘着层；110：承载基底；114：凹口；116：绝缘层；118：导电层；120：电路板；122：接垫；124：焊球；126：焊线。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定形式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关连性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装感测晶片。然其应用不限于此，例如在本发明的晶片封装体的实施例中，其可应用于各种包含有源元件或无源元件(active orpassive elements)、数字电路或模拟电路(digital or analog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(opto electronicdevices)、微机电系统(Micro Electro Mechanical System；MEMS)、微流体系统(microfluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(PhysicalSensor)。特别是可选择使用晶圆级封装(wafer scale package；WSP)制程对影像感测元件、发光二极管(light-emitting diodes；LEDs)、太阳能电池(solar cells)、射频元件(RFcircuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件(surface acoustic wave devices)、压力感测器(process sensors)、喷墨头(ink printer heads)、或功率模组(power IC modules)等半导体晶片进行封装。
其中，上述晶圆级封装制程主要是指，在晶圆阶段完成封装步骤后再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于借堆叠(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layerintegrated circuit devices)的晶片封装体。
图1A至1D显示根据本发明一实施例的晶片封装体的一系列制程剖面图。如图1A所示，提供半导体基底100，其具有上表面100a及下表面100b。半导体基底100例如为硅基底。在一实施例中，半导体基底100为一硅晶圆以利于进行晶圆级封装。
如图1A所示，元件区或感测区102形成于半导体基底100之中。在一实施例中，半导体基底100之中包括多个元件区或感测区102。在一实施例中，元件区或感测区102例如为一感测区，如指纹辨识区等。元件区或感测区102位于半导体基底100的上表面100a。在一实施例中，元件区或感测区102可能部分形成于半导体基底100的上表面100a之上。或者，在另一实施例中，元件区或感测区102完全形成于半导体基底100之中而于上表面100a露出。
如图1A所示，半导体基底100上还包括导电垫104。一般，导电垫104通过内部线路(未显示)而与元件区或感测区102电性连接。
接着，可选择性将半导体基底100薄化以利后续制程的进行。例如如图1B所示，在一实施例中，可将暂时性承载基板106设置于半导体基底100的上表面100a上。例如，可通过粘着层108而将暂时性承载基板106固定于半导体基底100的上表面100a上。接着，可以暂时性承载基板106为支撑，自半导体基底100的下表面100b进行薄化制程，如包括机械研磨或化学机械研磨等。在一实施例中，暂时性承载基板106可为玻璃基底或硅晶圆。
如图1B所示，在选择性设置暂时性承载基板106与选择性进行半导体基底100的薄化制程之后，于半导体基底100的下表面100b上设置承载基底110。可于承载基底110与半导体基底100之间形成粘着层112以接合承载基底110与半导体基底100。在一实施例中，承载基底110可为半导体基底或玻璃基底。
接着，如图1C所示，移除暂时性承载基板106。在一实施例中，暂时性承载基板106下方的粘着层108完全自半导体基底100的上表面100a移除。在此情形下，元件区或感测区102大抵直接露出而不具有其他材料层于其上。
接着，自半导体基底100的上表面100a朝下表面100b的方向形成凹口(notch)114。在一实施例中，凹口114完全贯穿半导体基底100并延伸进入承载基底110中。接着，于半导体基底100的上表面100a上及凹口114的侧壁与底部上沉积绝缘材料，并将之图案化以形成绝缘层116。接着，于绝缘层116上形成图案化的导电层118。
如图1C所示，导电层118与导电垫104电性连接，并自半导体基底100的上表面100a延伸至凹口114的侧壁与底部上。当凹口114贯穿半导体基底100而延伸进入承载基底110时，导电层118与绝缘层116还延伸进入承载基底110中。此外，在一实施例中，在承载基底110中，部分的导电层118与绝缘层116大抵水平设置，即大抵平行于半导体基底100的上表面100a。这是因为在一实施例中，所形成的凹口114的底部大抵平行于半导体基底100的上表面100a。
接着，如图1C所示，在一实施例中，自凹口114的底部切断承载基底110以分离出多个晶片封装体10。由于电性连接导电垫104的导电层118延伸在晶片封装体10的侧壁上(即自半导体基底100的上表面100a延伸至半导体基底100的侧壁上)，可将导电通路自半导体基底100的上表面100a经由侧壁而向下导引。在一实施例中，晶片封装体10的封装过程中仅需经历两道图案化制程(即，绝缘层116的图案化与导电层118的图案化)，可使晶片的封装制程大幅简化，且可节省制程时间与成本。此外，由于晶片的封装制程大幅简化，亦可使所形成的晶片封装体的可靠度提升。
如图1D所示，在一实施例中，可进一步将所形成的晶片封装体10设置于电路板120上。在一实施例中，电路板120上包括接垫122，其与电路板120中的线路相连，并作为与晶片封装体中的元件区或感测区102电性连接的接触点。如图1D的实施例所示，可于承载基底110与电路板120之间的转角处形成焊球124。焊球124同时电性接触导电层118与接垫122，形成导电层118与接垫122之间的导电通路。
应注意的是，本发明实施例不限于采用焊球124来形成元件区或感测区102与电路板120之间的导电通路。在其他实施例中，可采用导电层、导电块或焊线等其他的导电结构来取代焊球124。例如，在图2的实施例中，改使用焊线126取代焊球124。因此，举凡适于形成接垫122与导电层118之间的导电通路的导电结构，皆在本发明实施例所涵盖的范围之内。
本发明实施例通过于晶片的正面(即与元件区或感测区同一侧处)形成凹口及沿着凹口侧壁形成与元件区或感测区电性连接的导电层，可顺利形成所需的导电线路，并可大幅缩减晶片封装制程所需的图案化制程，且可显著缩减制程时间与成本。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (21)

1.一种晶片封装体，其特征在于，包括：
一下基底；
一上基底，具有一上表面及一下表面，且设置于该下基底上方；
一凹口，邻近于该上基底的一侧壁，其中该凹口沿着自该上基底的该上表面朝该下表面的一方向而形成；
一元件区或感测区，位于该上基底的该上表面；
一导电垫，位于该上基底的该上表面；以及
一导电层，电性连接该导电垫，且自该上基底的该上表面沿着该上基底的该侧壁延伸至该凹口。
2.根据权利要求1所述的晶片封装体，其特征在于，该上基底的该侧壁倾斜于该上基底的该上表面。
3.根据权利要求1所述的晶片封装体，其特征在于，该导电垫位于该凹口与该元件区或感测区之间。
4.根据权利要求1所述的晶片封装体，其特征在于，该导电层还延伸至该凹口的一底部上。
5.根据权利要求4所述的晶片封装体，其特征在于，该凹口的该底部位于该下基底的一表面上方且平行于该上基底的该上表面。
6.根据权利要求5所述的晶片封装体，其特征在于，还包括一绝缘层，该绝缘层位于该导电层与该上基底之间及/或位于该导电层与该下基底之间。
7.根据权利要求5所述的晶片封装体，其特征在于，还包括一电路板，其中该导电层通过一导电结构而与该电路板上的一接垫电性连接。
8.根据权利要求7所述的晶片封装体，其特征在于，该导电结构包括一焊球或一焊线。
9.根据权利要求8所述的晶片封装体，其特征在于，该导电结构位于该电路板的该接垫与该上基底的该上表面之间。
10.根据权利要求8所述的晶片封装体，其特征在于，该元件区或感测区的一表面位于该上基底的该上表面，且该导电结构的一部分位于该元件区或感测区的该表面上方。
11.一种晶片封装体，其特征在于，包括：
一承载基底；
一半导体基底，具有一上表面及一下表面，且设置于该承载基底上方；
一元件区或感测区，位于该半导体基底内；
一导电垫，位于该半导体基底的该上表面；以及
一导电层，电性连接该导电垫，且自该半导体基底的该上表面延伸至该半导体基底的一侧壁上，其中该半导体基底的该侧壁倾斜于该半导体基底的该上表面。
12.根据权利要求11所述的晶片封装体，其特征在于，该元件区或感测区包括一指纹辨识区。
13.根据权利要求11所述的晶片封装体，其特征在于，该导电层还延伸至该承载基底的一表面上，且该承载基底的该表面平行于该半导体基底的该上表面。
14.根据权利要求13所述的晶片封装体，其特征在于，还包括一电路板，其中该承载基底设置于该电路板上，且该导电层通过一导电结构而与该电路板上的一接垫电性连接。
15.根据权利要求14所述的晶片封装体，其特征在于，该导电结构包括一焊球或一焊线。
16.根据权利要求14所述的晶片封装体，其特征在于，该导电结构为一焊线，且该焊线的一部分位于该半导体基底的该上表面上方。
17.根据权利要求14所述的晶片封装体，其特征在于，该导电结构位于该电路板的该接垫与该半导体基底的该上表面之间。
18.一种晶片封装体，其特征在于，包括：
一晶片，该晶片包括一承载基底以及位于该承载基底上的一半导体基底；
一指纹辨识区以及一导电垫，位于该晶片的一前表面；
一凹口，形成于该晶片的该前表面；
一导电层，电性连接该导电垫，其中该导电层自该晶片的该前表面沿着该凹口的一侧壁延伸至该凹口而形成；以及
一电路板，具有一接垫，其中该导电层通过一导电结构而与该电路板上的该接垫电性连接。
19.根据权利要求18所述的晶片封装体，其特征在于，该导电结构位于该电路板的该接垫与该晶片的该前表面之间。
20.根据权利要求19所述的晶片封装体，其特征在于，该导电结构包括一焊球或一焊线。
21.根据权利要求20所述的晶片封装体，其特征在于，该导电垫位于该指纹辨识区与该凹口之间。
CN201510535157.9A 2010-05-11 2011-05-11 晶片封装体 Expired - Fee Related CN105226035B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US33345910P 2010-05-11 2010-05-11
US61/333,459 2010-05-11
CN201110122210.4A CN102244047B (zh) 2010-05-11 2011-05-11 晶片封装体及其形成方法

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201110122210.4A Division CN102244047B (zh) 2010-05-11 2011-05-11 晶片封装体及其形成方法

Publications (2)

Publication Number Publication Date
CN105226035A CN105226035A (zh) 2016-01-06
CN105226035B true CN105226035B (zh) 2018-06-05

Family

ID=44911033

Family Applications (3)

Application Number Title Priority Date Filing Date
CN201510535128.2A Active CN105244330B (zh) 2010-05-11 2011-05-11 晶片封装体
CN201110122210.4A Active CN102244047B (zh) 2010-05-11 2011-05-11 晶片封装体及其形成方法
CN201510535157.9A Expired - Fee Related CN105226035B (zh) 2010-05-11 2011-05-11 晶片封装体

Family Applications Before (2)

Application Number Title Priority Date Filing Date
CN201510535128.2A Active CN105244330B (zh) 2010-05-11 2011-05-11 晶片封装体
CN201110122210.4A Active CN102244047B (zh) 2010-05-11 2011-05-11 晶片封装体及其形成方法

Country Status (3)

Country Link
US (3) US8507321B2 (zh)
CN (3) CN105244330B (zh)
TW (3) TWI619218B (zh)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8952501B2 (en) 2010-05-11 2015-02-10 Xintec, Inc. Chip package and method for forming the same
US9437478B2 (en) 2010-05-11 2016-09-06 Xintec Inc. Chip package and method for forming the same
US9209124B2 (en) 2010-05-11 2015-12-08 Xintec Inc. Chip package
US8507321B2 (en) 2010-05-11 2013-08-13 Chao-Yen Lin Chip package and method for forming the same
US9355975B2 (en) 2010-05-11 2016-05-31 Xintec Inc. Chip package and method for forming the same
US9425134B2 (en) 2010-05-11 2016-08-23 Xintec Inc. Chip package
US9334158B2 (en) * 2012-05-22 2016-05-10 Xintec Inc. Chip package and method for forming the same
TWI553841B (zh) * 2013-01-31 2016-10-11 原相科技股份有限公司 晶片封裝及其製造方法
CN103985683B (zh) * 2013-02-08 2017-04-12 精材科技股份有限公司 晶片封装体
TWI549243B (zh) * 2013-03-07 2016-09-11 精材科技股份有限公司 半導體結構及其製造方法
TWI546921B (zh) * 2013-03-14 2016-08-21 精材科技股份有限公司 晶片封裝體及其形成方法
CN104241213B (zh) * 2013-06-21 2016-12-28 茂丞科技股份有限公司 超薄型全平面式感测装置及其制造方法
TWI576973B (zh) * 2013-07-24 2017-04-01 精材科技股份有限公司 晶片封裝體及其製造方法
TWI523171B (zh) * 2013-07-24 2016-02-21 精材科技股份有限公司 晶片封裝體及其製造方法
EP2838114A3 (en) * 2013-08-12 2015-04-08 Xintec Inc. Chip package
JP6654566B2 (ja) * 2013-08-23 2020-02-26 フィンガープリント カーズ アーベー 指紋検知システムの接続パッド
DE112013007584T5 (de) 2013-11-27 2016-08-18 Hewlett-Packard Development Company, L.P. Druckkopf mit von einer Abtrennung umgebenes Bondpad
US20150187728A1 (en) * 2013-12-27 2015-07-02 Kesvakumar V.C. Muniandy Emiconductor device with die top power connections
TWI575779B (zh) 2014-03-31 2017-03-21 精材科技股份有限公司 晶片封裝體及其製造方法
CN104051367A (zh) * 2014-07-01 2014-09-17 苏州晶方半导体科技股份有限公司 指纹识别芯片封装结构和封装方法
CN104051366B (zh) * 2014-07-01 2017-06-20 苏州晶方半导体科技股份有限公司 指纹识别芯片封装结构和封装方法
CN104051368A (zh) 2014-07-01 2014-09-17 苏州晶方半导体科技股份有限公司 指纹识别芯片封装结构和封装方法
CN104332452B (zh) * 2014-08-20 2017-04-19 深圳市汇顶科技股份有限公司 芯片封装模组
US9576177B2 (en) * 2014-12-11 2017-02-21 Fingerprint Cards Ab Fingerprint sensing device
TWI582677B (zh) * 2014-12-15 2017-05-11 精材科技股份有限公司 晶片封裝體及其製造方法
CN105181230A (zh) * 2015-08-06 2015-12-23 苏州敏芯微电子技术有限公司 压力传感器及其封装方法
CN107134435A (zh) * 2016-02-29 2017-09-05 茂丞科技股份有限公司 指纹感测封装模组及其制造方法
SG10201702885PA (en) 2016-04-20 2017-11-29 Lam Res Corp Apparatus for measuring condition of electroplating cell components and associated methods
TWI617992B (zh) * 2016-06-29 2018-03-11 關鍵禾芯科技股份有限公司 指紋辨識裝置及其製造方法
CN106206423B (zh) * 2016-09-08 2019-01-04 华进半导体封装先导技术研发中心有限公司 芯片封装侧壁植球工艺
CN108121933B (zh) * 2016-11-28 2022-02-25 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法、电子装置
KR102435517B1 (ko) * 2018-04-12 2022-08-22 에스케이하이닉스 주식회사 칩 스택 패키지
TWI701745B (zh) * 2018-08-28 2020-08-11 財團法人工業技術研究院 異質整合組裝結構及其製造方法
CN111146083B (zh) 2018-11-01 2022-08-19 精材科技股份有限公司 晶片封装体的制造方法及晶片封装体
TWI739697B (zh) * 2020-01-02 2021-09-11 精材科技股份有限公司 晶片封裝體及其製造方法
US11437337B2 (en) 2020-04-13 2022-09-06 Alibaba Group Holding Limited Using electrical connections that traverse scribe lines to connect devices on a chip

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101246893A (zh) * 2007-02-13 2008-08-20 精材科技股份有限公司 具有高传导面积的集成电路封装体及其制作方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2118994A1 (en) 1993-06-21 1994-12-22 Claude L. Bertin Polyimide-insulated cube package of stacked semiconductor device chips
JP2002151546A (ja) 2000-11-08 2002-05-24 Mitsubishi Heavy Ind Ltd Ｉｃチップの電極構造、信号取出構造及び電極形成方法
WO2003019653A2 (de) * 2001-08-24 2003-03-06 Schott Glas Verfahren zum kontaktieren und gehäusen von integrierten schaltungen
TWI232560B (en) * 2002-04-23 2005-05-11 Sanyo Electric Co Semiconductor device and its manufacture
JP2004363400A (ja) 2003-06-05 2004-12-24 Sanyo Electric Co Ltd 半導体装置およびその製造方法
SG120123A1 (en) * 2003-09-30 2006-03-28 Micron Technology Inc Castellated chip-scale packages and methods for fabricating the same
US7199345B1 (en) 2004-03-26 2007-04-03 Itt Manufacturing Enterprises Inc. Low profile wire bond for an electron sensing device in an image intensifier tube
TWI264807B (en) * 2005-03-02 2006-10-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
TW200642015A (en) * 2005-05-25 2006-12-01 Siliconware Precision Industries Co Ltd Sensor semiconductor device and fabrication method thereof
US7894643B2 (en) * 2005-10-18 2011-02-22 Authentec, Inc. Finger sensor including flexible circuit and associated methods
US20080002460A1 (en) * 2006-03-01 2008-01-03 Tessera, Inc. Structure and method of making lidded chips
TWI313050B (en) 2006-10-18 2009-08-01 Advanced Semiconductor Eng Semiconductor chip package manufacturing method and structure thereof
EP2135280A2 (en) * 2007-03-05 2009-12-23 Tessera, Inc. Chips having rear contacts connected by through vias to front contacts
TW200839982A (en) * 2007-03-19 2008-10-01 Xintec Inc Integrated circuit package and method for fabricating thereof
CN100552963C (zh) * 2007-03-28 2009-10-21 精材科技股份有限公司 集成电路封装体及其制作方法
US20080315407A1 (en) 2007-06-20 2008-12-25 Vertical Circuits, Inc. Three-dimensional circuitry formed on integrated circuit device using two-dimensional fabrication
US8097929B2 (en) * 2008-05-23 2012-01-17 Chia-Sheng Lin Electronics device package and fabrication method thereof
JP5486376B2 (ja) 2010-03-31 2014-05-07 ルネサスエレクトロニクス株式会社 半導体装置
US8507321B2 (en) 2010-05-11 2013-08-13 Chao-Yen Lin Chip package and method for forming the same
US8952501B2 (en) * 2010-05-11 2015-02-10 Xintec, Inc. Chip package and method for forming the same
US8803326B2 (en) 2011-11-15 2014-08-12 Xintec Inc. Chip package
US8981578B2 (en) 2012-04-30 2015-03-17 Apple Inc. Sensor array package
US9281292B2 (en) 2012-06-25 2016-03-08 Intel Corporation Single layer low cost wafer level packaging for SFF SiP

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101246893A (zh) * 2007-02-13 2008-08-20 精材科技股份有限公司 具有高传导面积的集成电路封装体及其制作方法

Also Published As

Publication number Publication date
US20140328523A1 (en) 2014-11-06
CN102244047B (zh) 2015-09-23
TW201545297A (zh) 2015-12-01
CN102244047A (zh) 2011-11-16
US9196594B2 (en) 2015-11-24
TWI536525B (zh) 2016-06-01
US9030011B2 (en) 2015-05-12
CN105244330B (zh) 2019-01-22
CN105226035A (zh) 2016-01-06
TWI541968B (zh) 2016-07-11
US8507321B2 (en) 2013-08-13
TW201140779A (en) 2011-11-16
TWI619218B (zh) 2018-03-21
US20130320532A1 (en) 2013-12-05
US20110278724A1 (en) 2011-11-17
TW201545298A (zh) 2015-12-01
CN105244330A (zh) 2016-01-13

Similar Documents

Publication Publication Date Title
CN105226035B (zh) 晶片封装体
CN104347576B (zh) 晶片封装体及其制造方法
US8952501B2 (en) Chip package and method for forming the same
US9425134B2 (en) Chip package
US8294275B2 (en) Chip package and method for forming the same
US9761510B2 (en) Chip package and method for forming the same
CN103985683B (zh) 晶片封装体
CN104979301B (zh) 晶片封装体及其制造方法
CN104835793B (zh) 晶片封装体及其制造方法
CN103390601B (zh) 晶片封装体及其形成方法
US20140332908A1 (en) Chip package and method for forming the same
CN104952812A (zh) 晶片封装体及其制造方法
CN104051359B (zh) 晶片封装体及其形成方法
CN104979426A (zh) 晶片封装体的制造方法
CN104347560B (zh) 晶片封装体及其制造方法
US20120104445A1 (en) Chip package and method for forming the same
TWI593069B (zh) 晶片封裝體及其製造方法
CN104835792B (zh) 晶片封装体及其制造方法
CN106558525A (zh) 晶片封装体及其制造方法
US20200235009A1 (en) Method for manufacturing a chip package

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20180605

Termination date: 20190511