TWI503937B - 晶片封裝體及其形成方法 - Google Patents

晶片封裝體及其形成方法 Download PDF

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TWI503937B
TWI503937B TW102118001A TW102118001A TWI503937B TW I503937 B TWI503937 B TW I503937B TW 102118001 A TW102118001 A TW 102118001A TW 102118001 A TW102118001 A TW 102118001A TW I503937 B TWI503937 B TW I503937B
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semiconductor substrate
layer
semiconductor
chip package
forming
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TW102118001A
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TW201349413A (zh
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Yu Ting Huang
Shu Ming Chang
Yen Shih Ho
Tsang Yu Liu
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Xintex Inc
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Description

晶片封裝體及其形成方法
本發明係有關於晶片封裝體，且特別是有關於微機電系統晶片封裝體(MEMS chip packages)。
隨著電子產品朝向輕、薄、短、小發展的趨勢，半導體晶片的封裝結構也朝向多晶片封裝(multi-chip package,MCP)結構發展，以達到多功能和高性能要求。多晶片封裝結構係將不同類型的半導體晶片，例如邏輯晶片、類比晶片、控制晶片、記憶體晶片、微機電系統晶片，整合在單一封裝基底之上。
隨著元件密度的提升，晶片封裝體底部上之導電凸塊的密度亦隨之提升。如何在有限空間中設置所需的導電凸塊已成為重要課題。
本發明一實施例提供一種晶片封裝體，包括：一第一半導體基底；一第二半導體基底，設置於該第一半導體基底之上，其中該第二半導體基底包括一下半導體層、一上半導體層、及位於該下半導體層與該上半導體層之間的一絕緣層，且部分的該下半導體層電性接觸該第一半導體基底上之至少一接墊；一信號導電結構，設置於該第一半導體基底之一下表面之上，該信號導電結構電性連接該第一半導體基底上之一信 號接墊；以及一導電層，設置於該第二半導體基底之該上半導體層之上，且電性連接該下半導體層之與該第一半導體基底上之該至少一接墊電性接觸的該部分。
本發明一實施例提供一種晶片封裝體的形成方 法，包括：提供一第一半導體基底；提供一第二半導體基底，包括一下半導體層、一上半導體層、及位於該下半導體層與該上半導體層之間的一絕緣層；將該第二半導體基底接合於該第一半導體基底之上而使部分的該下半導體層電性接觸該第一半導體基底上之至少一接墊；於該第二半導體基底之該上半導體層之上形成一導電層，其中該導電層電性連接該下半導體層之與該第一半導體基底上之該至少一接墊電性接觸的該部分；以及於該第一半導體基底之一下表面之上形成一信號導電結構，其中該信號導電結構電性連接該第一半導體基底上之一信號接墊。
10、20‧‧‧半導體基底
100‧‧‧上半導體層
100a、100b‧‧‧表面
102‧‧‧絕緣層
104‧‧‧下半導體層
106‧‧‧孔洞
108‧‧‧導電層
110‧‧‧承載基底
112‧‧‧黏著層
200‧‧‧半導體基底
200a、200b‧‧‧表面
202‧‧‧介電層
204‧‧‧接墊
206‧‧‧孔洞
208‧‧‧絕緣層
210a‧‧‧晶種層
210b‧‧‧導電層
212‧‧‧保護層
214‧‧‧導電結構
第1A-1J圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。
第2圖顯示根據本發明一實施例之晶片封裝體的剖面圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此技 藝人士自本揭露書之申請專利範圍中所能推及的所有實施方式皆屬本揭露書所欲揭露之內容。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝各種晶片及/或多晶片之堆疊。例如，其可用於封裝各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System；MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package；WSP)製程對影像感測元件、發光二極體(light-emitting diodes；LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)噴墨頭(ink printer heads)、或功率晶片(power IC)等半導體晶片進行封裝。
上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施 例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(rnulti-layer integrated circuit devices)之晶片封裝體。在一實施中，上述切割後的封裝體係為一晶片尺寸封裝體(CSP；chip scale package)。晶片尺寸封裝體(CSP)之尺寸可僅略大於所封裝之晶片。例如，晶片尺寸封裝體之尺寸不大於所封裝晶片之尺寸的120%。
第1A-1J圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。如第1A圖所示，提供半導體基底10及20。在一實施例中，半導體基底10及20可皆為半導體晶圓，其例如分別為(但不限於)包含微機電系統之晶圓及包含互補式金氧半場效電晶體之晶圓。
在一實施例中，半導體基底10包括下半導體層104、上半導體層100、及位於下半導體層104與上半導體層100之間的絕緣層102。上半導體層100可具有表面100a及表面100b，且可以表面100b下之絕緣層102而與下半導體層104電性絕緣。在一實施例中，下半導體層104中可定義有數個間隙，其可將下半導體層104劃分為複數個彼此分離之部分。
在一實施例中，半導體基底20(例如為半導體晶圓)包括半導體基底200、設置於半導體基底200之表面200a上之接墊204及介電層202。接墊204可包含信號接墊或接地接墊。
在一實施例中，可將半導體基底10接合於半導體基底20之上，使得部分的下半導體層104接合並電性接觸至少 一接墊204。在一實施例中，部分的下半導體層104所接觸之接墊204可為(但不限於)接地接墊。
接著，如第1B圖所示，可選擇性薄化上半導體層100。適合的薄化製程例如包括機械研磨製程、化學機械研磨製程、蝕刻製程、或前述之組合。
接著，可於上半導體層100之表面100a上形成與部分的下半導體層104及接墊204(例如是接地接墊)電性連接之導電層。導電層可透過穿孔及/或經由基底之側邊而與接墊204(例如是接地接墊)電性連接。然而，為簡化說明，以下僅以透過穿孔而與接墊204(例如是接地接墊)電性連接之實施方式為例。
如第1C圖所示，可自上半導體層100之表面100a移除部分的上半導體層100以形成朝下半導體層104延伸之孔洞106。在一實施例中，孔洞106可對齊於接墊204(例如是接地接墊)及與接墊204連接之部分的下半導體層104。在另一實施例中，孔洞106可對齊於接墊204，但所對齊之接墊204不與下半導體層104接觸。在又一實施例中，孔洞106不與接墊204對齊。
接著，如第1D圖所示，可於上半導體層100之表面100a上形成導電層108。在一實施例中，導電層108可延伸進入孔洞106而電性接觸所露出之下半導體層104。下半導體層104之由孔洞106所露出之部分可電性連接半導體基底200上之接墊204(其例如為接地接墊)。因此，導電層108可與接墊204電性連接而可作為接地用途。在一實施例中，導電層108可大抵及/或完全覆蓋上半導體層100之表面100a及孔洞106之側壁及底部。在一實施例中，導電層108可直接接觸上半導體層100。在 一實施例中，孔洞106可位於預定切割道(未顯示)之中。
此外，導電層108除了可用作接地外，在其他實施例中，導電層108可作為電磁干擾防護(EMI shielding)層、導熱層、或反射層。
如第1E圖所示，可選擇性於上半導體層100上設置承載基底110。例如，可採用黏著層112而將承載基底110接合於上半導體層100之上。
接著，如第1F圖所示，可選擇性薄化半導體基底200。例如，可以承載基底110為支撐，自半導體基底200之表面200b薄化半導體基底200。
如第1G圖所示，可接著自表面200b移除部分的半導體基底200以形成朝接墊204(其例如是信號接墊)延伸之孔洞206。
接著，如第1H圖所示，可於半導體基底200之表面200b上形成絕緣層208。絕緣層208可延伸於孔洞206之側壁與底部上。在一實施例中，可進一步透過圖案化製程移除孔洞206底部上之部分的絕緣層208而使接墊204(例如，信號接墊)露出。
如第1I圖所示，可接著於絕緣層208上形成電信連接接墊204(例如，信號接墊)之導電層。例如，可先形成晶種層210a，並接著透過電鍍製程形成導電層210b。
接著，如第1J圖所示，可於導電層210b及絕緣層208上形成保護層212，其具有露出部分的導電層210b之至少一開口。接著，可於開口中形成信號導電結構214，其例如為導電凸塊或銲球。在所接合之兩半導體基底為半導體晶圓之實施例 中，可接著沿著預定切割道(未顯示)進行切割製程以將兩半導體基底切割為複數個彼此分離之晶片封裝體。
第2圖顯示根據本發明一實施例之晶片封裝體的剖面圖，其中相同或相似之標號用以標示相同或相似之元件。第2圖之實施例大抵相同於第1圖所示之實施例。主要區別在於所使用之黏著層112可為易於移除之黏著膠。因此，可例如透過照光、加熱、及/或使用溶劑之方式移除黏著層112及承載基底110而進一步縮減晶片封裝體之尺寸。
在本發明實施例中，晶片封裝體之信號導電結構214可設於晶片封裝體之下表面，而(接地)接墊204可透過下半導體層104而與設置在晶片封裝體之上側的導電層108電性連接。因此，晶片封裝體之下表面上之導電凸塊的分佈密度可獲舒緩。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧上半導體層
100a、100b‧‧‧表面
102‧‧‧絕緣層
104‧‧‧下半導體層
106‧‧‧孔洞
108‧‧‧導電層
110‧‧‧承載基底
112‧‧‧黏著層
200‧‧‧半導體基底
200a、200b‧‧‧表面
202‧‧‧介電層
204‧‧‧接墊
206‧‧‧孔洞
208‧‧‧絕緣層
210a‧‧‧晶種層
210b‧‧‧導電層
212‧‧‧保護層
214‧‧‧導電結構

Claims (20)

  1. 一種晶片封裝體，包括：一第一半導體基底；一第二半導體基底，設置於該第一半導體基底之上，其中該第二半導體基底包括一下半導體層、一上半導體層、及位於該下半導體層與該上半導體層之間的一絕緣層，且部分的該下半導體層電性接觸該第一半導體基底上之至少一接墊；一信號導電結構，設置於該第一半導體基底之一下表面之上，該信號導電結構電性連接該第一半導體基底上之一信號接墊；以及一導電層，設置於該第二半導體基底之該上半導體層之上，且電性連接該下半導體層之與該第一半導體基底上之該至少一接墊電性接觸的該部分。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該導電層大抵完全覆蓋該第二半導體基底之該上半導體層之一上表面。
  3. 如申請專利範圍第1項所述之晶片封裝體，更包括一孔洞，自該第二半導體基底之該上半導體層之一上表面朝該第二半導體基底之該下半導體層延伸，其中該導電層延伸進入該孔洞而電性接觸部分的該下半導體層。
  4. 如申請專利範圍第3項所述之晶片封裝體，其中該孔洞對齊於其中一該至少一接墊。
  5. 如申請專利範圍第1項所述之晶片封裝體，更包括一第二 導電層，電性連接該信號導電結構及該信號接墊。
  6. 如申請專利範圍第5項所述之晶片封裝體，更包括一第二孔洞，自該第一半導體基底之一下表面朝該信號接墊延伸，其中該第二導電層延伸進入該第二孔洞而電性接觸該信號接墊，且該第二導電層與該第一半導體基底之間隔有一第二絕緣層。
  7. 如申請專利範圍第1項所述之晶片封裝體，其中該導電層直接接觸該第二半導體基底。
  8. 如申請專利範圍第1項所述之晶片封裝體，更包括一承載基底，設置於該第二半導體基底之上。
  9. 如申請專利範圍第8項所述之晶片封裝體，更包括一黏著層，設置於該承載基底與該第二半導體基底之上。
  10. 如申請專利範圍第1項所述之晶片封裝體，其中該第一半導體基底包括一互補式金氧半(CMOS)場效電晶體晶片，而該第二半導體基底包括一微機電系統(MEMS)晶片。
  11. 一種晶片封裝體的形成方法，包括：提供一第一半導體基底；提供一第二半導體基底，該第二半導體基底包括一下半導體層、一上半導體層、及位於該下半導體層與該上半導體層之間的一絕緣層；將該第二半導體基底接合於該第一半導體基底之上而使部分的該下半導體層電性接觸該第一半導體基底上之至少一接墊；於該第二半導體基底之該上半導體層之上形成一導電 層，其中該導電層電性連接該下半導體層之與該第一半導體基底上之該至少一接墊電性接觸的該部分；以及於該第一半導體基底之一下表面之上形成一信號導電結構，其中該信號導電結構電性連接該第一半導體基底上之一信號接墊。
  12. 如申請專利範圍第11項所述之晶片封裝體的形成方法，更包括於形成該導電層之前，薄化該上半導體層。
  13. 如申請專利範圍第11項所述之晶片封裝體的形成方法，更包括於形成該導電層之前，移除部分的該上半導體層以形成朝該下半導體層延伸之一孔洞，接著形成該導電層而使該導電層延伸進入該孔洞而電性接觸部分的該下半導體層。
  14. 如申請專利範圍第13項所述之晶片封裝體的形成方法，其中該導電層大抵完全覆蓋該上半導體層之一上表面及該孔洞之一側壁及一底部。
  15. 如申請專利範圍第11項所述之晶片封裝體的形成方法，更包括在形成該信號導電結構之前，薄化該第一半導體基底。
  16. 如申請專利範圍第15項所述之晶片封裝體的形成方法，更包括：於該第二半導體基底之上接合一承載基底；以及以該承載基底為支撐，自該第一半導體基底之該下表面薄化該第一半導體基底。
  17. 如申請專利範圍第16項所述之晶片封裝體的形成方法，更 包括：自該第一半導體基底之該下表面移除部分的該第一半導體基底以形成露出該信號接墊之一第二孔洞；於該第一半導體基底之該下表面上及該第二孔洞之一側壁上形成一第二絕緣層；於該第一半導體基底之該下表面上形成一第二導電層，該第二導電層延伸進入該第二孔洞而電性連接該信號接墊；以及於該第一半導體基底之該下表面上之該第二導電層上形成該信號導電結構。
  18. 如申請專利範圍第17項所述之晶片封裝體的形成方法，更包括於該第一半導體基底之該下表面上形成一保護層，其中該保護層具有露出該信號導電結構之至少一開口。
  19. 如申請專利範圍第18項所述之晶片封裝體的形成方法，更包括移除該承載基底。
  20. 如申請專利範圍第11項所述之晶片封裝體的形成方法，更包括對該第一半導體基底及該第二半導體基底進行一切割製程以形成彼此分離之複數個晶片封裝體。
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US20080099862A1 (en) * 2006-10-30 2008-05-01 Denso Corporation Physical quantity sensor and method for manufacturing the same
TW201203479A (en) * 2010-07-09 2012-01-16 Xintec Inc Chip package and method for forming the same

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TW201349413A (zh) 2013-12-01

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