TWI619218B - 晶片封裝體及其形成方法 - Google Patents

晶片封裝體及其形成方法 Download PDF

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Publication number
TWI619218B
TWI619218B TW100116445A TW100116445A TWI619218B TW I619218 B TWI619218 B TW I619218B TW 100116445 A TW100116445 A TW 100116445A TW 100116445 A TW100116445 A TW 100116445A TW I619218 B TWI619218 B TW I619218B
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Taiwan
Prior art keywords
semiconductor substrate
chip package
carrier substrate
substrate
conductive
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TW100116445A
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English (en)
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TW201140779A (en
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林超彥
林義航
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精材科技股份有限公司
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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
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Abstract

本發明實施例提供一種晶片封裝體，包括：一承載基底；一半導體基底，具有一上表面及一下表面，且設置於該承載基底之上；一元件區或感測區，位於該半導體基底之該上表面；一導電墊，位於該半導體基底之該上表面；一導電層，電性連接該導電墊，且自該半導體基底之該上表面延伸至該半導體基底之一側壁上；以及一絕緣層，位於該導電層與該半導體基底之間。

Description

晶片封裝體及其形成方法
本發明係有關於晶片封裝體及其形成方法，且特別是有關於感測晶片之晶片封裝體。
傳統晶片封裝體的製程涉及多道的圖案化製程與材料沉積製程，不僅耗費生產成本，亦需較長的製程時間。
因此，業界亟需更為簡化與快速的晶片封裝技術。
本發明實施例提供一種晶片封裝體，包括：一承載基底；一半導體基底，具有一上表面及一下表面，且設置於該承載基底之上；一元件區或感測區，位於該半導體基底之該上表面；一導電墊，位於該半導體基底之該上表面；一導電層，電性連接該導電墊，且自該半導體基底之該上表面延伸至該半導體基底之一側壁上；以及一絕緣層，位於該導電層與該半導體基底之間。
本發明一實施例提供一種晶片封裝體的形成方法，包括：提供一半導體基底，具有一上表面及一下表面，該半導體基底之該上表面處包括至少一元件區或感測區以及至少一導電墊；提供一承載基底，並將該半導體基底設置於該承載基底之上；自該半導體基底之該上表面形成一凹口；於該半導體基底之該上表面上與該凹口之中形成一絕緣層；於該絕緣層上形成一導電層，該導電層電性連接該導電墊，且自該半導體基底之該上表面延伸至該半導體基底之一側壁上；以及自該凹口之一底部切斷該承載基底以形成複數個分離的晶片封裝體。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝感測晶片。然其應用不限於此，例如在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System;MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package;WSP)製程對影像感測元件、發光二極體(light-emitting diodes;LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)、噴墨頭(ink printer heads)、或功率模組(power IC modules)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。
第1A-1D圖顯示根據本發明一實施例之晶片封裝體的一系列製程剖面圖。如第1A圖所示，提供半導體基底100，其具有上表面100a及下表面100b。半導體基底100例如為矽基底。在一實施例中，半導體基底100為一矽晶圓以利於進行晶圓級封裝。
如第1A圖所示，元件區或感測區102係形成於半導體基底100之中。在一實施例中，半導體基底100之中包括複數個元件區或感測區102。在一實施例中，元件區或感測區102例如為一感測區，如指紋辨識區等。元件區或感測區102係位於半導體基底100之上表面100a。在一實施例中，元件區或感測區102可能部分形成於半導體基底100之上表面100a之上。或者，在另一實施例中，元件區或感測區102完全形成於半導體基底100之中而於上表面100a露出。
如第1A圖所示，半導體基底100上還包括導電墊104。一般，導電墊104係透過內部線路(未顯示)而與元件區或感測區102電性連接。
接著，可選擇性將半導體基底100薄化以利後續製程之進行。例如，如第1B圖所示，在一實施例中，可將暫時性承載基板106設置於半導體基底100之上表面100a上。例如，可透過黏著層108而將暫時性承載基板106固定於半導體基底100之上表面100a上。接著，可以暫時性承載基板106為支撐，自半導體基底100之下表面100b進行薄化製程，如包括機械研磨或化學機械研磨等。在一實施例中，暫時性承載基板106可為玻璃基底或矽晶圓。
如第1B圖所示，在選擇性設置暫時性承載基板106與選擇性進行半導體基底100之薄化製程之後，於半導體基底100之下表面100b上設置承載基底110。可於承載基底110與半導體基底100之間形成黏著層112以接合承載基底110與半導體基底100。在一實施例中，承載基底110可為半導體基底或玻璃基底。
接著，如第1C圖所示，移除置暫時性承載基板106。在一實施例中，暫時性承載基板106下方之黏著層108完全自半導體基底100之上表面100a移除。在此情形下，元件區或感測區102大抵直接露出而不具有其他材料層於其上。
接著，自半導體基底100之上表面100a朝下表面100b之方向形成凹口(notch)114。在一實施例中，凹口114完全貫穿半導體基底100並延伸進入承載基底110之中。接著，於半導體基底100之上表面100a上及凹口114之側壁與底部上沉積絕緣材料，並將之圖案化以形成絕緣層116。接著，於絕緣層116之上形成圖案化的導電層118。
如第1C圖所示，導電層118係與導電墊104電性連接，並自半導體基底100之上表面100a延伸至凹口114之側壁與底部上。當凹口114貫穿半導體基底100而延伸進入承載基底110時，導電層118與絕緣層116還延伸進入承載基底110之中。此外，在一實施例中，在承載基底110之中，部分的導電層118與絕緣層116係大抵水平設置，即大抵平行於半導體基底100之上表面100a。這是因為在一實施例中，所形成之凹口114之底部係大抵平行於半導體基底100之上表面100a。
接著，如第1C圖所示，在一實施例中，自凹口114之底部切斷承載基底110以分離出複數個晶片封裝體10。由於電性連接導電墊104之導電層118延伸在晶片封裝體10之側壁上(即自半導體基底100之上表面100a延伸至半導體基底100之側壁上)，可將導電通路自半導體基底100之上表面100a經由側壁而向下導引。在一實施例中，晶片封裝體10的封裝過程中僅需經歷兩道圖案化製程(即，絕緣層116之圖案化與導電層118之圖案化)，可使晶片之封裝製程大幅簡化，可節省製程時間與成本。此外，由於晶片之封裝製程大幅簡化，亦可使所形成之晶片封裝體的可靠度提升。
如第1D圖所示，在一實施例中，可進一步將所形成之晶片封裝體10設置於電路板120上。在一實施例中，電路板120上包括接墊122，其與電路板120中之線路相連，並作為與晶片封裝體中之元件區或感測區102電性連接之接觸點。如第1D圖之實施例所示，可於承載基底110與電路板120之間的轉角處形成焊球124。焊球124同時電性接觸導電層118與接墊122，形成導電層118與接墊122之間的導電通路。
應注意的是，本發明實施例不限於採用焊球124來形成元件區或感測區102與電路板120之間的導電通路。在其他實施例中，可採用導電層、導電塊、或焊線等其他的導電結構來取代焊球124。例如，在第2圖之實施例中，係改使用焊線126取代焊球124。因此，舉凡適於形成接墊122與導電層118之間的導電通路之導電結構，皆在本發明實施例所涵蓋之範圍之內。
本發明實施例透過於晶片之正面(即與元件區或感測區同一側處)形成凹口及沿著凹口側壁形成與元件區或感測區電性連接之導電層，可順利形成所需之導電線路，並可大幅縮減晶片封裝製程所需之圖案化製程，可顯著地縮減製程時間與成本。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．封裝體
100．．．基底
100a、100b．．．表面
102．．．元件區或感測區
104．．．導電墊
106．．．暫時性承載基板
108、112．．．黏著層
110．．．承載基底
114．．．凹口
116．．．絕緣層
118．．．導電層
120．．．電路板
122．．．接墊
124．．．焊球
126．．．焊線
第1A-1D圖顯示根據本發明一實施例之晶片封裝體的一系列製程剖面圖。
第2圖顯示本發明一實施例之晶片封裝體的剖面圖。

Claims (19)

  1. 一種晶片封裝體，包括：一承載基底；一半導體基底，具有一上表面及一下表面，且設置於該承載基底之上；一元件區或感測區，位於該半導體基底之該上表面；一導電墊，位於該半導體基底之該上表面；一凹口，自該半導體基底之該上表面朝該下表面延伸，且自該半導體基底之一側壁延伸至該承載基底之一邊緣側壁，該凹口之一側壁構成該晶片封裝體之一外側邊緣；一導電層，電性連接該導電墊，且自該半導體基底之該上表面延伸至該半導體基底之該側壁上；以及一絕緣層，位於該導電層與該半導體基底之間，其中該絕緣層延伸進入該承載基底之中。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該半導體基底之該側壁傾斜於該半導體基底之該上表面。
  3. 如申請專利範圍第1項所述之晶片封裝體，其中該元件區或感測區大抵直接露出。
  4. 一種晶片封裝體，包括：一承載基底；一半導體基底，具有一上表面及一下表面，且設置於該承載基底之上；一元件區或感測區，位於該半導體基底之該上表面； 一導電墊，位於該半導體基底之該上表面；一凹口，自該半導體基底之該上表面朝該下表面延伸，且自該半導體基底之一側壁延伸至該承載基底之一邊緣側壁，該凹口之一側壁構成該晶片封裝體之一外側邊緣；一導電層，電性連接該導電墊，且自該半導體基底之該上表面延伸至該半導體基底之該側壁上，其中該導電層延伸進入該承載基底之中；以及一絕緣層，位於該導電層與該半導體基底之間。
  5. 如申請專利範圍第4項所述之晶片封裝體，其中延伸進入該承載基底中的該導電層包括一部分，該部分大抵平行於該半導體基底之該上表面。
  6. 如申請專利範圍第1項所述之晶片封裝體，更包括一電路板，其中該承載基底設置於該電路板之上，且該導電層透過一導電結構而與該電路板上之一接墊電性連接。
  7. 如申請專利範圍第6項所述之晶片封裝體，其中該導電結構包括一焊球或一焊線。
  8. 如申請專利範圍第7項所述之晶片封裝體，其中該導電結構為一焊球，且該焊球位於該承載基底與該電路板之間的一轉角處。
  9. 如申請專利範圍第1項所述之晶片封裝體，其中該元件區或感測區包括一指紋辨識區。
  10. 一種晶片封裝體的形成方法，包括：提供一半導體基底，具有一上表面及一下表面，該 半導體基底之該上表面處包括至少一元件區或感測區以及至少一導電墊；提供一承載基底，並將該半導體基底設置於該承載基底之上；自該半導體基底之該上表面形成一凹口；於該半導體基底之該上表面上與該凹口之中形成一絕緣層；於該絕緣層上形成一導電層，該導電層電性連接該導電墊，且自該半導體基底之該上表面延伸至該半導體基底之一側壁上；以及自該凹口之一底部切斷該承載基底以形成複數個分離的晶片封裝體。
  11. 如申請專利範圍第10項所述之晶片封裝體的形成方法，其中該凹口延伸進入該承載基底之中。
  12. 如申請專利範圍第10項所述之晶片封裝體的形成方法，其中該導電層延伸在該凹口之該底部上。
  13. 如申請專利範圍第10項所述之晶片封裝體的形成方法，更包括在形成該凹口之前將該半導體基底薄化。
  14. 如申請專利範圍第13項所述之晶片封裝體的形成方法，其中該半導體基底之薄化包括：在將該半導體基底設置於該承載基底之前，於該半導體基底之該上表面上設置一暫時性承載基底；以及以該暫時性承載基底為支撐，自該半導體基底之該下表面薄化該半導體基底。
  15. 如申請專利範圍第14項所述之晶片封裝體的形 成方法，更包括在形成該凹口之前，移除該暫時性承載基底。
  16. 如申請專利範圍第10項所述之晶片封裝體的形成方法，更包括：提供一電路板，具有一接墊；將該承載基底設置於該電路板之上；以及形成一導電結構，該導電結構電性連接該接墊與該導電層。
  17. 如申請專利範圍第16項所述之晶片封裝體的形成方法，其中該導電結構包括一焊球或一焊線。
  18. 如申請專利範圍第17項所述之晶片封裝體的形成方法，其中該導電結構為一焊球，且該焊球位於該承載基底與該電路板之間的一轉角處。
  19. 如申請專利範圍第10項所述之晶片封裝體的形成方法，其中該元件區或感測區大抵直接露出。
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Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9425134B2 (en) 2010-05-11 2016-08-23 Xintec Inc. Chip package
US9209124B2 (en) 2010-05-11 2015-12-08 Xintec Inc. Chip package
US8952501B2 (en) 2010-05-11 2015-02-10 Xintec, Inc. Chip package and method for forming the same
US9355975B2 (en) 2010-05-11 2016-05-31 Xintec Inc. Chip package and method for forming the same
CN102244047B (zh) 2010-05-11 2015-09-23 精材科技股份有限公司 晶片封装体及其形成方法
US9437478B2 (en) 2010-05-11 2016-09-06 Xintec Inc. Chip package and method for forming the same
TWI503937B (zh) * 2012-05-22 2015-10-11 Xintex Inc 晶片封裝體及其形成方法
TWI553841B (zh) * 2013-01-31 2016-10-11 原相科技股份有限公司 晶片封裝及其製造方法
CN103985683B (zh) * 2013-02-08 2017-04-12 精材科技股份有限公司 晶片封装体
TWI549243B (zh) * 2013-03-07 2016-09-11 精材科技股份有限公司 半導體結構及其製造方法
TWI546921B (zh) * 2013-03-14 2016-08-21 精材科技股份有限公司 晶片封裝體及其形成方法
CN104241213B (zh) * 2013-06-21 2016-12-28 茂丞科技股份有限公司 超薄型全平面式感测装置及其制造方法
CN104347576B (zh) * 2013-07-24 2017-06-09 精材科技股份有限公司 晶片封装体及其制造方法
TWI576973B (zh) * 2013-07-24 2017-04-01 精材科技股份有限公司 晶片封裝體及其製造方法
EP2838114A3 (en) * 2013-08-12 2015-04-08 Xintec Inc. Chip package
EP3036688A4 (en) * 2013-08-23 2017-05-17 Fingerprint Cards AB Connection pads for a fingerprint sensing device
CN105793044B (zh) 2013-11-27 2017-10-10 惠普发展公司，有限责任合伙企业 具有由坝状物围绕的接合焊盘的打印头
US20150187728A1 (en) * 2013-12-27 2015-07-02 Kesvakumar V.C. Muniandy Emiconductor device with die top power connections
TWI575779B (zh) * 2014-03-31 2017-03-21 精材科技股份有限公司 晶片封裝體及其製造方法
CN104051368A (zh) * 2014-07-01 2014-09-17 苏州晶方半导体科技股份有限公司 指纹识别芯片封装结构和封装方法
CN104051366B (zh) * 2014-07-01 2017-06-20 苏州晶方半导体科技股份有限公司 指纹识别芯片封装结构和封装方法
CN104051367A (zh) 2014-07-01 2014-09-17 苏州晶方半导体科技股份有限公司 指纹识别芯片封装结构和封装方法
CN104332452B (zh) 2014-08-20 2017-04-19 深圳市汇顶科技股份有限公司 芯片封装模组
US9576177B2 (en) * 2014-12-11 2017-02-21 Fingerprint Cards Ab Fingerprint sensing device
TWI582677B (zh) * 2014-12-15 2017-05-11 精材科技股份有限公司 晶片封裝體及其製造方法
CN105181230A (zh) * 2015-08-06 2015-12-23 苏州敏芯微电子技术有限公司 压力传感器及其封装方法
CN107134435A (zh) * 2016-02-29 2017-09-05 茂丞科技股份有限公司 指纹感测封装模组及其制造方法
SG10201702885PA (en) * 2016-04-20 2017-11-29 Lam Res Corp Apparatus for measuring condition of electroplating cell components and associated methods
TWI617992B (zh) * 2016-06-29 2018-03-11 關鍵禾芯科技股份有限公司 指紋辨識裝置及其製造方法
CN106206423B (zh) * 2016-09-08 2019-01-04 华进半导体封装先导技术研发中心有限公司 芯片封装侧壁植球工艺
CN108121933B (zh) * 2016-11-28 2022-02-25 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法、电子装置
KR102435517B1 (ko) * 2018-04-12 2022-08-22 에스케이하이닉스 주식회사 칩 스택 패키지
TWI701745B (zh) 2018-08-28 2020-08-11 財團法人工業技術研究院 異質整合組裝結構及其製造方法
CN111146083B (zh) 2018-11-01 2022-08-19 精材科技股份有限公司 晶片封装体的制造方法及晶片封装体
US20210210538A1 (en) * 2020-01-02 2021-07-08 Xintec Inc. Chip package and method for forming the same
US11437337B2 (en) 2020-04-13 2022-09-06 Alibaba Group Holding Limited Using electrical connections that traverse scribe lines to connect devices on a chip

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030230805A1 (en) * 2002-04-23 2003-12-18 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US20060197217A1 (en) * 2005-03-02 2006-09-07 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US20080150063A1 (en) * 2001-08-24 2008-06-26 Florian Bieck Process for making contact with and housing integrated circuits
CN101675516A (zh) * 2007-03-05 2010-03-17 泰塞拉公司 具有通过过孔连接到前侧触头的后侧触头的芯片

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2118994A1 (en) 1993-06-21 1994-12-22 Claude L. Bertin Polyimide-insulated cube package of stacked semiconductor device chips
JP2002151546A (ja) 2000-11-08 2002-05-24 Mitsubishi Heavy Ind Ltd Ｉｃチップの電極構造、信号取出構造及び電極形成方法
JP2004363400A (ja) 2003-06-05 2004-12-24 Sanyo Electric Co Ltd 半導体装置およびその製造方法
SG120123A1 (en) * 2003-09-30 2006-03-28 Micron Technology Inc Castellated chip-scale packages and methods for fabricating the same
US7199345B1 (en) 2004-03-26 2007-04-03 Itt Manufacturing Enterprises Inc. Low profile wire bond for an electron sensing device in an image intensifier tube
TW200642015A (en) * 2005-05-25 2006-12-01 Siliconware Precision Industries Co Ltd Sensor semiconductor device and fabrication method thereof
WO2007047823A1 (en) * 2005-10-18 2007-04-26 Authentec, Inc. Finger sensing with enhanced mounting and associated methods
US20080002460A1 (en) * 2006-03-01 2008-01-03 Tessera, Inc. Structure and method of making lidded chips
TWI313050B (en) 2006-10-18 2009-08-01 Advanced Semiconductor Eng Semiconductor chip package manufacturing method and structure thereof
CN101246893A (zh) * 2007-02-13 2008-08-20 精材科技股份有限公司 具有高传导面积的集成电路封装体及其制作方法
TW200839982A (en) * 2007-03-19 2008-10-01 Xintec Inc Integrated circuit package and method for fabricating thereof
CN100552963C (zh) * 2007-03-28 2009-10-21 精材科技股份有限公司 集成电路封装体及其制作方法
WO2008157779A2 (en) 2007-06-20 2008-12-24 Vertical Circuits, Inc. Three-dimensional circuitry formed on integrated circuit device using two- dimensional fabrication
US8097929B2 (en) * 2008-05-23 2012-01-17 Chia-Sheng Lin Electronics device package and fabrication method thereof
JP5486376B2 (ja) 2010-03-31 2014-05-07 ルネサスエレクトロニクス株式会社 半導体装置
US8952501B2 (en) * 2010-05-11 2015-02-10 Xintec, Inc. Chip package and method for forming the same
CN102244047B (zh) 2010-05-11 2015-09-23 精材科技股份有限公司 晶片封装体及其形成方法
TWI479622B (zh) 2011-11-15 2015-04-01 Xintec Inc 晶片封裝體及其形成方法
US8981578B2 (en) 2012-04-30 2015-03-17 Apple Inc. Sensor array package
US9281292B2 (en) 2012-06-25 2016-03-08 Intel Corporation Single layer low cost wafer level packaging for SFF SiP

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080150063A1 (en) * 2001-08-24 2008-06-26 Florian Bieck Process for making contact with and housing integrated circuits
US20030230805A1 (en) * 2002-04-23 2003-12-18 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US20060197217A1 (en) * 2005-03-02 2006-09-07 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
CN101675516A (zh) * 2007-03-05 2010-03-17 泰塞拉公司 具有通过过孔连接到前侧触头的后侧触头的芯片

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US20130320532A1 (en) 2013-12-05
US9030011B2 (en) 2015-05-12
CN105244330B (zh) 2019-01-22
US9196594B2 (en) 2015-11-24
CN105226035A (zh) 2016-01-06
TW201545297A (zh) 2015-12-01
TWI541968B (zh) 2016-07-11
CN102244047A (zh) 2011-11-16
TWI536525B (zh) 2016-06-01
CN105244330A (zh) 2016-01-13
US20110278724A1 (en) 2011-11-17
TW201140779A (en) 2011-11-16
US20140328523A1 (en) 2014-11-06

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