CN101675516A - 具有通过过孔连接到前侧触头的后侧触头的芯片 - Google Patents

具有通过过孔连接到前侧触头的后侧触头的芯片 Download PDF

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CN101675516A
CN101675516A CN200880014764A CN200880014764A CN101675516A CN 101675516 A CN101675516 A CN 101675516A CN 200880014764 A CN200880014764 A CN 200880014764A CN 200880014764 A CN200880014764 A CN 200880014764A CN 101675516 A CN101675516 A CN 101675516A
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conductive
front surface
microelectronic unit
semiconductor element
contact
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CN101675516B (zh
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B·哈巴
K·A·霍纳
D·B·塔克曼
V·奥加涅相
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Adeia Semiconductor Solutions LLC
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Tessera LLC
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Abstract

一种微电子单元被提供，其中半导体元件(100)的前表面(102)和后表面(114)可以限定出具有第一厚度的薄区(105)和具有至少为第一厚度二倍的厚度的厚区。半导体器件(112)可以设置在前表面，位于前表面的多个第一导电触头(116)连接着所述器件。多个导电过孔(125)可以从后表面延伸穿过半导体元件的薄区(105)到达第一导电触头(116)。多个第二导电触头(134)可以暴露在半导体元件(100)的外部。多个导电迹线(126)可以将第二导电触头(134)连接至导电过孔(125)。

Description

具有通过过孔连接到前侧触头的后侧触头的芯片
相关申请的交叉引用
[0001]本申请要求享有2007年3月5日提交的美国临时申请No.60/905,096的申请日，该申请的公开内容以引用方式并入本申请。
背景技术
[0002]本发明涉及微电子器件的封装，尤其是半导体器件的封装。
[0003]某些类型的微电子器件和半导体芯片包括各种器件，例如声换能器、射频发射器、射频检测器或光电子器件或这些器件的组合。这样的器件典型地要求被封装以便实现在半导体芯片的表面向或者从这些器件传输能量，例如音频、射频或光频波长的能量。
[0004]由于这样的微电子器件经常在器件前侧面暴露，因此它们通常要求被保护而避免各种因素例如尘土、其它颗粒、污物或水分。出于这个原因，有益的是在加工的早期阶段在微电子器件上组装盖子或其它元件，以便罩盖这种微电子器件的前侧面。
[0005]在某些类型的微电子系统中希望在电路板上安装芯片以及具有非常小的即芯片级封装体的封装芯片。在一下情况下，希望将芯片彼此上下叠置地层叠和互联，以增大组件的电路密度。
[0006]一些类型的批量制造的芯片还要求严格控制封装成本。用于封装这种半导体芯片的过程同能同时实施于许多芯片，而此时这些芯片以晶片或部分晶片的形式保持附连于彼此。这种″晶片级″加工典型地是在整个晶片上以一系列过程实施的，之后，晶片被切块为单个芯片。有利地，晶片级封装过程所产生的封装芯片具有与原始半导体芯片相同的面积尺寸，从而使得它们在电路板和类似物上的互联较为紧凑。
发明内容
[0007]根据本发明的一个方面，一种微电子单元被提供，其中半导体元件具有前表面和远离前表面的后表面。前表面和后表面可以限定出具有第一厚度的薄区和具有至少为第一厚度二倍的第二厚度的厚区。在这样的微电子单元中，半导体元件可以包括位于前表面的半导体器件和位于前表面的连接着所述器件的多个第一导电触头。多个导电过孔可以从后表面延伸穿过半导体元件的薄区到达第一导电触头。多个第二导电触头可以暴露在半导体元件的外部，并且多个导电迹线可以将第二导电触头连接至导电过孔。
[0008]根据本发明的另一方面，一种微电子单元被提供。在这样的微电子单元中，半导体元件具有前表面、位于前表面的半导体器件和远离前表面的后表面。第一导电触头可以设置在前表面。半导体元件可以还包含的第一孔，其具有第一深度且从后表面且部分地穿过半导体元件朝向前表面延伸。这样的第二孔可以具有第二深度且从第一孔延伸至第一导电触头。多个第一导电过孔可以沿着第二孔的壁延伸至接触第一导电触头。多个导电互联部可以连接到第一导电过孔。在一个实施方式中，这样的导电互联部可以沿着第一孔的壁延伸。多个第二导电触头可以连接到导电互联部。在一个例子中，第二触头可以暴露在半导体元件的外部。
[0009]根据本发明的一个方面，一种微电子单元被提供，其可以包括半导体元件，所述半导体元件具有前表面、位于前表面的半导体器件和位于前表面的连接着所述器件的多个第一导电触头。盖子可以被提供，其具有面对着半导体元件前表面的内表面和远离内表面的外表面。具有第一深度的第一孔可以从外表面至少部分地穿过盖子朝向内表面延伸。支撑结构可以被提供，其在半导体元件的前表面上方支撑着盖子的内表面。在一个例子中，支撑结构具有与第一孔对正的第二孔。第二孔可以延伸穿过支撑结构到达第一导电触头。多个第一导电过孔可以沿着第二孔的壁延伸至接触第一导电触头。多个第二导电过孔可以沿着第一孔的壁延伸。多个第二导电触头可以暴露在盖子的外部。在一个例子中，多个导电迹线将这样的第二导电触头连接至导电过孔。
[0010]根据本发明的一个方面，一种微电子单元被提供，其包括半导体元件，所述半导体元件具有前表面和位于半导体元件前表面的半导体器件。多个第一导电触头可以设置在前表面，它们连接着所述器件。微电子单元可以额外地包括盖子，其具有面对着半导体元件前表面的内表面和远离内表面的外表面。盖子的内表面和外表面可以限定出具有第一厚度的薄区和具有至少为第一厚度二倍的第二厚度的厚区。这样的盖子可以还包括从外表面延伸穿过盖子的薄区而连接至第一导电触头的多个导电过孔。这样的微电子单元可以还包括多个第二导电触头。多个导电迹线也可以将第二导电触头连接至导电过孔。
[0011]根据本发明的一个方面，一种微电子单元被提供，其可以包括盖子，所述盖子具有面对着半导体元件前表面的内表面和远离前表面的外表面。多个导电过孔可以延伸穿过盖子而接触第一导电触头。这样的微电子单元可以额外地包括叠加于盖子外表面上的多个第二导电触头。多个导电迹线可以将第二导电触头连接至导电过孔。
[0012]根据本发明的一个方面，一种微电子单元被提供，其包括半导体元件，所述半导体元件具有前表面、位于前表面的半导体器件和远离前表面的后表面。前导电触头可以暴露在前表面。后导电触头可以暴露在后表面。多个导电过孔可以连接到前导电触头，所述导电过孔从前表面向下延伸。开口可以以与导电过孔中的至少一个对准(嵌套)的方式从后表面向下延伸。导电迹线可以从导电过孔中的至少一个沿着开口的壁向上延伸。这样的导电迹线可以连接到后导电触头中的至少一个。
[0013]根据本发明的一个方面，一种微电子单元被提供，其包括半导体元件，所述半导体元件具有前表面、位于前表面的半导体器件和远离前表面的后表面。后导电触头可以暴露在后表面。在这样的微电子单元中，多个导电过孔可以从前表面向下延伸。开口可以以与导电过孔中的至少一个对准(嵌套)的方式从后表面向下延伸。导电凸块可以结合至该开口中的导电过孔之一。在这种情况下，导电凸块可以从导电过孔延伸至由后表面限定的平面上方的位置。
[0014]根据本发明的一个方面，一种微电子单元被提供，其包括半导体元件，所述半导体元件具有前表面、位于前表面的半导体器件和远离前表面的后表面。后导电触头可以暴露在后表面。多个导电过孔可以从前表面向下延伸。开口可以以与导电过孔中的至少一个对准(嵌套)的方式从后表面向下延伸。导电凸块可以在前表面结合至导电过孔之一。例如，导电凸块可以从前表面向上延伸。
[0015]根据本发明的另一方面，一种制造微电子单元的方法被提供。这种方法可以包括提供半导体元件，其具有前表面、远离前表面的后表面和位于前表面的半导体器件。第一导电触头可以设置在半导体元件的前表面，它们连接着所述器件。多个导电过孔可以从后表面延伸穿过半导体元件到达第一导电触头。这种方法可以还包括形成叠加于后表面上的多个第二导电触头以及多个导电迹线，所述导电迹线将第二导电触头连接至导电过孔。
[0016]根据本发明的另一方面，一种制造微电子单元的方法被提供，其中半导体元件被提供，其包括前表面和位于前表面的半导体器件。位于前表面的第一导电触头可以连接到半导体器件。半导体元件可以还包括远离前表面的后表面和暴露在后表面的半导体材料。多个通孔可以从后表面延伸穿过半导体元件到达第一导电触头。后介电层可以在后表面、沿着通孔的壁或同时以这两种方式被电沉积到暴露的半导体材料上。第二导电触头可以叠加于后表面上。多个导电过孔可以形成在通孔中以接触第一导电触头。多个导电迹线可以被形成，用于将第二导电触头连接至导电过孔。
[0017]根据本发明的另一实施方式，一种制造微电子单元的方法被提供。这种方法可以包括将半导体元件与罩盖元件组装在一起，所述罩盖元件叠加于半导体元件的前表面上，由此形成一个单元。半导体元件可以在前表面具有第一导电触头，它们连接着半导体器件。后表面可以被提供，其远离前表面。多个通孔可以从后表面延伸穿过半导体元件到达第一导电触头。在一个实施方式中，半导体材料暴露在后表面和暴露在通孔的壁处。
[0018]介电层可以被电沉积以便在后表面以及沿着通孔的壁叠加于暴露的半导体材料上。介电层还可以被电沉积到介电层上，以使得导电过孔被形成在通孔内以接触第一导电触头。多个第二导电触头可以叠加于后表面上，并且多个导电迹线可以将导电过孔连接至第二导电触头。
附图说明
[0019]图1是剖视图，示出了根据本发明的一个实施方式的封装半导体芯片。
[0020]图2是剖视图，示出了根据本发明的一个实施方式的同时制造多个封装半导体芯片的方法中的一个阶段。
[0021]图3A和3B是剖视图和相应的俯视图，示出了根据本发明的一个实施方式的一个制造阶段。
[0022]图3C和3D是剖视图和相应的俯视图，示出了根据本发明的一个实施方式的制造方法中的制备盖子件的阶段。
[0023]图4是剖视图，示出了根据本发明的一个实施方式的制造方法中的一个阶段。
[0024]图5A和5B是剖视图和相应的俯视图，示出了根据本发明的一个实施方式中的一个制造阶段。
[0025]图6A是俯视图，示出了根据本发明的一个实施方式中的一个制造阶段。
[0026]图6B是俯视图，示出了根据本发明的备选实施方式中的一个制造阶段。
[0027]图7A、7B和7C是剖视图、相应的俯视图和放大图，示出了根据本发明的一个实施方式中的一个制造阶段。
[0028]图8A和8B是剖视图和相应的俯视图，示出了根据本发明的一个实施方式中的一个制造阶段。
[0029]图9A和9B是剖视图和相应的俯视图，示出了根据本发明的一个实施方式中的一个制造阶段。
[0030]图10A和10B是剖视图和相应的俯视图，示出了根据本发明的一个实施方式中的一个制造阶段。
[0031]图11是剖视图，示出了根据本发明的一个实施方式的光电子器件模块，例如照相机或摄像机模块。
[0032]图12和13是剖视图和相应的透视图，示出了根据本发明的一个实施方式的备选光电子器件模块，例如照相机或摄像机模块。
[0033]图14是剖视图，示出了根据本发明的一个实施方式的另一备选光电子器件模块，例如照相机或摄像机模块。
[0034]图15是剖视图，示出了一种组件，其包括根据本发明的一个实施方式的封装半导体芯片。
[0035]图16A是剖视图，示出了根据本发明的另一实施方式的封装芯片。
[0036]图16B是俯视图进一步示出了图16A中所示的封装芯片。
[0037]图17是剖视图，示出了根据本发明的另一实施方式的封装芯片。
[0038]图18是剖视图，示出了根据本发明的另一实施方式的封装芯片。
[0039]图19A是局部剖视图，示出了根据本发明的另一实施方式的封装芯片。
[0040]图19B是相应的俯视图，进一步示出了图19A中所示的根据本发明实施方式的封装芯片。
[0041]图19C是相应的俯视图，进一步示出了根据图19A中所示的本发明实施方式的一种改型的封装芯片。
[0042]图19D是剖视图，示出了一种叠层式组件，其包括多个示于图19A的封装芯片。
[0043]图19E是局部剖视图，示出了图19A中所示的根据本发明实施方式的一种改型的封装芯片。
[0044]图19F是剖视图，示出了叠层式组件，其包括多个示于图19E的封装芯片。
[0045]图20A是剖视图，示出了根据示于图19A的实施方式的一种改型的封装芯片。
[0046]图20B是剖视图，示出了叠层式组件，其包括多个示于图20A封装芯片。
[0047]图21A是剖视图，进一步示出了根据本发明的一个实施方式的封装芯片。
[0048]图21B是局部放大图，进一步示出了图21A中所示的封装芯片。
[0049]图22A是剖视图，进一步示出了根据本发明的一个实施方式的封装芯片。
[0050]图22B是局部放大图，进一步示出了图22A中所示的封装芯片。
[0051]图23A、23B和23C是剖视图，示出了根据本发明各实施方式的改型的封装芯片。
[0052]图23D、23E和23F是剖视图，示出了根据本发明各实施方式的改型的封装芯片。
[0053]图24A是剖视图，进一步示出了根据本发明的一个实施方式的封装芯片。
[0054]图24B是局部放大图，进一步示出了图24A中所示的封装芯片。
[0055]图25A是剖视图，示出了根据本发明的一个实施方式的封装芯片。
[0056]图25B是剖视图，示出了叠层式组件，其包括多个封装芯片示于图25A。
[0057]图26A是剖视图，示出了根据本发明的一个实施方式的封装芯片。
[0058]图26B是剖视图，示出了叠层式组件，其包括多个示于图26A的封装芯片。
[0059]图27A是剖视图，示出了根据本发明的一个实施方式的封装芯片。
[0060]图27B是剖视图，示出了叠层式组件，其包括多个示于图27A的封装芯片。
[0061]图28A是剖视图，示出了根据本发明的一个实施方式的封装芯片。
[0062]图28B是剖视图，示出了叠层式组件，其包括多个示于图28A的封装芯片。
具体实施方式
[0063]图1是根据本发明的一个实施方式的封装半导体芯片10的剖视图。如示于图1，封装芯片被显示在这样的定向，其中半导体芯片的前侧面102面向向下。如示于图1，封装芯片包括半导体芯片100，其具有前侧面102和远离前侧面的后侧面114。芯片100的前侧面被盖子或罩盖104覆盖，所述盖子或罩盖与半导体芯片100组装在一起以形成封装芯片10。如示于图1，半导体芯片100的前侧面102被定向为向下面对着盖子104的朝向上方的内表面105。半导体芯片100典型地包括半导体基底，在其中一个或多个半导体器件112在前侧面102下方被布置在器件区中。半导体芯片100还包括叠加于基底上的多个介电层，在其中导电金属布线层和过孔(未示出)被布置。半导体器件112被布置在芯片的前侧面和/或芯片的前后侧面之间。封装芯片可以称作芯片级封装(″CSP″)，这是因为封装芯片10的外部横向尺寸(例如，沿箭头102的方向)几乎与裸芯片的那些尺寸相同。
[0064]半导体芯片100典型地4通过一个或多个支座结构124连接着盖子10，所述支座结构可以包括粘合剂，无机或有机材料和/或结合金属。用于以距离芯片的恒定间隔支撑盖子的结构描述于共同拥有的2006年1月23日提交的美国临时申请No.60/761,171和2006年2月21日提交的美国临时申请No.60/775,086中，所述申请的公开内容以引用方式并入本申请。封装芯片可以包括位于芯片的前侧面102和盖子104的内表面105之间的内部空腔106，如示于图1。或者，封装芯片10可以被构造成不带内部空腔。当空腔存在时，空腔的高度108和各种横向尺寸，包括横向尺寸110，被典型地基于例如用于将盖子104与半导体芯片100相组装的结构124的高度和尺寸来确定。在特定的实施方式中，盖子104主要由玻璃或聚合材料构成，并且至少部分地对于感兴趣频率的电磁频谱是透过性的。盖子104可以仅仅是部分地透过性的以提供过滤器功能，或者可以对于一定范围的感兴趣频率是基本上透过性的。
[0065]半导体芯片100中的半导体器件112典型地包括电磁换能器件例如电磁或光电器件，其检测或输出电磁辐射。半导体器件可以被设计成发射或接收射频和/或光学波长的红外线、可见光和/或紫外线或更大波长的频谱，包括但不局限于x射线波长。或者，半导体器件112可以包括音频换能器件，这样的器件被设计成将通过介质例如空气和/或其它流体介质(气体或液体)接收的声压波转换成一个或多个电信号，或将一个或多个电信号转换为声压波。
[0066]在特定的实施方式中，封装芯片是传感器单元，在其中芯片100的半导体器件112包括成像区域107，用于俘获图像。芯片100中的电路(未示出)连接着成像区域107中的半导体器件，用于产生代表由成像区域107拍摄的图像的一个或多个电信号。用于此目的的数字电路在成像领域中是公知的。例如，半导体芯片100可以是普通的传统电荷耦合器件(CCD)成像芯片，带有传统电路例如时钟和电荷至电压转换电路。
[0067]如见于图1，半导体芯片在半导体芯片的前侧面包括多个前触点垫116。虽然未在图1中专门示出，位于器件区中的半导体器件112导电连接着前触点垫116。因此，半导体器件可通过所采用的在半导体芯片100的一个或多个介电层之内或上方延伸的布线而被导电地触及。
[0068]半导体芯片具有表面120，其以一定角度离开后表面设置。如示于图1，表面120可以从后侧面以不是直角的角度倾斜离开，其斜坡既可以是缓坡，例如，相对于后表面法向的角度小于45度，或者斜坡可以更为陡峭，其中相对于所述法向的角度大于45度。或者，表面120可以与后侧面成直角。表面120终止于下部后表面115。下部后表面115背对着前侧面102并且与之相隔着半导体芯片100的减薄区105。
[0069]导电过孔125延伸在芯片100的前侧面102和下部后表面115之间。导电过孔提供了前触点垫116和导电迹线126之间的导电互联部，其叠加于下部后表面115和表面120上。导电过孔125包括叠加于介电层122上的导电层，其布置在延伸于前侧面和下部后表面之间的孔127中。在前侧面102和下部后表面之间，孔127的壁可以竖直延伸，即，相对于前侧面成直角。或者，孔127可以沿着从下部后表面朝向前侧面的方向呈锥形，以使得孔随着与下部后表面相隔的距离的增加而缩小。在又一替代方案中，孔127可以沿着从前侧面朝向下部后表面方向呈锥形，以使得孔随着距离前侧面的深度的增加而缩小。下面描述的每个实施方式可以包括具有任何一种可供使用的孔几何形状的孔。
[0070]在图1中所示的实施例中，导电过孔125的形式为从芯片的触点垫116沿着孔127的壁向上延伸的导电迹线，所述迹线沿着壁120向上延展并且到达后侧面114。或者，导电过孔125的形式可以为孔127充填有导电材料例如金属。在这种情况下，迹线126可以从各个过孔沿着壁120延伸并且到达后侧面114。
[0071]介电层122优选包括共形涂覆的介电材料。优选地，在共形涂层中没有裂纹并且介电层122提供了相对于半导体芯片100的良好的介电隔离。理想地，介电层122是顺应层，具有充分低的弹性模量和足够的厚度，以使得弹性模量和厚度的乘积确保提供顺应性。具体地讲，这样的顺应层可以允许触头128和其上附连的迹线126在一定程度上挠曲。以这种方式，封装芯片10的外部导电凸块134和电路板(未示出)的端子之间的结合部可以更好地抵抗由于封装芯片10和电路板(未示出)的热膨胀系数(″CTE″)之间的失配而导致的热应变。理想地，提供由介电层122的厚度及其弹性模量的乘积提供的顺应度足以补偿由于芯片100和电路板之间的热膨胀失配导致的施加于导电凸块的应变。底部填充剂(未示出)可以提供在介电层130的暴露表面和这样的电路板之间以增强对由于CTE失配导致的热应变的抵抗力。
[0072]进一步参看图1，导电迹线126将导电过孔125导电连接至叠加于封装芯片10的外表面上的相应的封装触点垫128。如图1中具体所示，封装触点垫128叠加于半导体芯片100的后侧面114上。导电迹线126叠加于第二介电层122上并且延伸越过半导体芯片的表面120和后侧面114的一些部分。理想地，导电迹线126将芯片100的各个前触点垫116与相应的各封装触点垫128连接。导电凸块134可以被提供在触点垫128上。微电子元件100在前后侧面之间的厚度160典型地小于200μm，并且可以显著更小，例如、130nm、70nm甚至更小。微电子元件在下表面115和前侧面102之间的厚度162通常为厚度160的一半或小于其一半。理想地，微电子元件在下表面处的厚度162显著小于厚度160的一半。在一个例子中，厚度162约为10微米。
[0073]如图1中进一步所示，第二介电层130叠加于导电迹线126上并且为其提供外部隔离。这个层可以被称作封装体10的″外部钝化层″130。第二介电层可以包括无机或有机介电材料或二者。第二介电可以包括电沉积的共形涂层或其它介电材料，例如，可光成像的聚合材料，例如，焊料掩膜材料。可光成像的焊料掩膜材料可以从多个制造商获得，包括Shipley和Toyo等等。
[0074]在特定的实施方式中，包括由可润湿金属层形成的金属层或金属层层叠体的金属结构132叠加于封装触点垫128上，并且导电凸块134叠加于金属结构132上。典型地，导电凸块134包括具有相对低熔点的可熔性金属例如焊料、锡或包含多种金属的低共熔混合物。或者，凸块134包括可润湿金属，例如，铜或其它贵金属或非贵金属，其熔点高于焊料或其它可熔性金属。这样的可润湿金属可以组合相应的特征，例如，互联元件例如电路板的可熔性金属特征，以将封装芯片10从外部互联至这样的互联元件。在另一备选方案中，凸块134包括内置于介质中的导电材料，所述介质可以是例如导电膏，例如金属充填膏，焊料充填膏或各项同性导电粘合剂或各项异性导电粘合剂。
[0075]参看图2，半导体芯片100优选通过晶片级过程同时封装，即，通过对多个半导体芯片100同时执行的过程，这些半导体芯片保持结合在一起作为晶片的一部分或作为整块半导体器件晶片101。在达到图2所示的一个制造阶段后，晶片与附连的盖子104的组件被沿着切线12和图2中的视图中不可见的其它切线切断成单个的封装半导体芯片。
[0076]下面参看图3A至10B描述一种方法，其同时制造多个封装芯片10(图1)。如示于图3A，包含多个芯片100的半导体器件晶片或器件晶片部分被安装至盖子件111，以使得芯片100的前侧面102上具有器件区112和前触头116，面对着盖子件111。理想地，盖子件111的沿横向(在内表面105限定的平面中延伸的各个方向)的尺寸优选与半导体器件晶片101的横向尺寸相同。附图标记12表示各芯片100之间边界处的切线的位置。晶片的切线12不需要太宽。芯片100的结合垫116的位置不需要专门定位成使得结合垫像通常那样远离切线。切线的代表性宽度约为40μm(微米)。如示于图3B中的俯视图，所述器件晶片的后侧面101A叠加于芯片的前侧面102上。理想地，在这一制造阶段，后侧面101A与芯片的前侧面102均匀地相隔所述器件晶片的初始厚度272。结合垫116位于所述器件晶片和切线12下方的位置显示在朝向所述器件晶片的后侧面101A所作的相应俯视图(图3B)中。
[0077]如进一步示于图3A，支座结构206将所述器件晶片101支撑在盖子件111的内表面105上方的距离108处。图3C示出了制造过程的初级阶段，其中多个支座结构206可以形成为从盖子件111的包含在切线12处附连在一起的各盖子元件104的主表面向外延伸。如最佳见于图3D，每个支座结构206典型地具有矩形形状，与竖直定向的切线12的对正并且与位于将被从原始盖子件111切下的各个盖子的边界之间的水平定向的切线14对正。如示于图3D，支座结构206具有这样的形式，其可以描述为″相框状环形″。如前所述，支座结构可以包括一或多种无机介电材料、有机介电材料、半导体、导体例如一或多种金属、金属化合物或这些材料的组合。支座结构可以通过添加材料型工艺或去除材料型工艺或二者制作，如描述于，例如，2004年9月24日提交的美国专利申请No.10/949,674，或美国临时申请No.60/761,171，所述申请的公开内容以引用方式并入本申请。当支座结构包括金属时，其可以通过下述步骤的组合制作，其中包括溅镀薄金属层，然后通过去除材料来图案化，然后在保留结构上电镀最终的金属。或者，支座结构可以这样形成，即通过无电镀，然后通过去除材料来图案化，以及电镀。在特定的实施方式中，支座结构206是这样的制造的，即在预先存在的溅镀或电镀导电层上电泳沉积聚合物，其方式可以采用例如以引入方式并入本申请的美国临时申请No.60/775,086中描述的。
[0078]在如图3A所示将所述器件晶片101结合至盖子元件111后，所述器件晶片的厚度可以从后侧面101A消减。从后侧面进行研磨、打磨或抛光或它们的组合可以用于减小厚度。在被执行以减小厚度的过程中，盖子元件104叠加于半导体芯片的前侧面上有助于向半导体芯片提供结构支撑，提高其刚度，以允许封装芯片的厚度被尽可能理想地减小到至更小的厚度。在这个步骤中，举例来说，所述器件晶片的厚度可以从大约700nm减小至大约130nm或甚至更小。
[0079]之后，所产生的器件晶片具有示于图4的减小的厚度274，并且后侧面114与每个芯片100的前侧面102分隔厚度274。接下来，如示于图5A，凹陷276形成在所述器件晶片中，其从后侧面114朝向所述器件晶片的前侧面102向下延伸。凹陷可以这样形成例如，在需要保存芯片后侧面114的保留部分的地方形成掩膜层，之后选择性蚀刻所述器件晶片。例如，可光成像的层例如光阻层可以沉积和图案化以便只罩盖后侧面的各部分，然后定时蚀刻过程可以执行，以形成凹陷276。凹陷可以形成为条278，其沿着直线方向280在所述器件晶片上方与切线12对正地延伸。如最佳见于图6A，细长的凹陷276理想地被同时形成，其沿着所述器件晶片的竖直配置方向280与竖直延伸的切线对正地延伸。竖直延伸凹陷276可以形成为只沿着各对芯片的切块线延伸。在这种情况下，凹陷可以不叠加于芯片100的位于竖直切线12和沿所述器件晶片的水平配置方向延伸的水平切线14之间的交点处的角部部分上。在另一例子中，水平延伸凹陷284可以形成为邻近于每个芯片的水平切线14叠加于结合垫上。竖直延伸凹陷276和水平延伸凹陷284都可以形成在所述器件晶片中。在特定的例子中，凹陷可以被形成为邻近于仅仅一条界定芯片的切线叠加于结合垫上。在另一例子中，凹陷可以形成为叠加于芯片的仅仅两条切线上或叠加于仅仅三条切线或更多界定芯片的切线上。在一个例子中，凹陷可以制作得小于图6A所示的，以使得凹陷叠加于邻近于所述器件晶片101的切线12安置的成排的结合垫中的仅仅一些结合垫上。在又一例子中，如示于图6B，与切线12对正的凹陷286可以以条的形式延伸在所述器件晶片101的相应边缘288、290之间。
[0080]如图5A中特别显示，每个凹陷276理想地具有下表面502，其为平坦的并且与前侧面102等距。凹陷的从后侧面114朝向下表面向下延伸的壁504可以是倾斜的，即，可以以除垂直角度(直角)之外的角度延伸至后表面114，如特别示于图5A。湿式蚀刻过程例如各项同性蚀刻过程和利用斜边锯片的锯切等等，可以用于形成如图5A所示具有倾斜壁504的凹陷。激光切块、机械磨削、等等，也可以用于形成具有倾斜壁的凹陷。或者，不是采用倾斜形状，壁可以相对于后侧面114成直角从后侧面114竖直向下延伸。各项异性蚀刻过程，激光切块，激光钻销，机械去除过程例如锯切、磨削、超声加工，等等，可以用于形成具有基本竖直壁的凹陷。在所述器件晶片重形成凹陷之后，可光成像的层例如光阻层被沉积在所述器件晶片的后部并且被图案化，以形成叠加于下表面502上的与结合垫116对准的掩膜开口506。
[0081]之后，如示于图7A，蚀刻过程被应用于下表面502的暴露在掩膜开口中的部分以便去除位于掩膜开口下面的半导体材料。结果，过孔708被形成，其延伸在下表面间，与前触头116接触。蚀刻过程理想地被以这样的方式执行，其选择性蚀刻半导体材料例如硅，但保留氧化物材料。典型地，前触头例如芯片的结合垫116叠加于一或多层的氧化物材料或其它介电材料上，该材料被用于钝化，作为级间介电层，或用于其它目的，以提供芯片上的绝缘或隔离。通过以选择方式蚀刻半导体材料，其保留介电层，包覆蚀刻可以根据需要被执行，以便在所述器件晶片的所有位置蚀透半导体材料的厚度，同时在整个所述器件晶片上维持足够的工艺窗口。当选择性蚀刻过程被使用时，优选地，如见于图7B中的局部放大图，介电层710例如氧化物层在形成过孔708之后保留在其位之上。或者，激光钻销或机械磨削可以用于形成过孔708，在这种情况下，前触点垫的表面可以暴露在过孔中。
[0082]之后，在示于图8A的制造阶段，介电层820形成在过孔的壁806以及壁504和芯片后表面114。各种方法可以用于形成这样的介电层。在一个例子中，可流动的介电材料被施加于包含芯片100的晶片101的后表面114上，然后，在″旋涂″操作中，可流动的材料被更均匀地分布在晶片的整个后表面上，然后，执行干燥周期，其可以包括加热。在另一例子中，介电材料的热塑性薄膜可以施加于所述器件晶片101的后表面，然后包括晶片和盖子元件的组件被加热，引起薄膜向下流动到下表面115上并且进入过孔708。在另一例子中，气相沉积可以用于形成介电层。
[0083]在又一例子中，包括所述器件晶片与附着于其上的盖子元件的组件浸入介电沉积浴槽中，以形成共形介电涂层或层820。优选地，电泳沉积技术被用于形成共形介电涂层，以使得共形介电涂层只沉积在组件的暴露的导电和半导电表面上。在沉积过程中，半导体器件晶片被保持在期望的电势，并且电极浸入浴槽中，以将浴槽保持在不同的期望的电势。组件然后被以适宜的条件保持在浴槽中充足的时间以在所述器件晶片的导电或半导电的暴露表面上形成电沉积的共形介电涂层820，包括但不局限于沿着后侧面114、凹陷壁504、下表面502和过孔708的壁806形成。只要充分强的电池被维持在将被如此涂覆的表面和浴槽之间，就会发生电泳沉积。电泳沉积涂层是自我限制的，即在基于其沉积时的参数例如电压、浓度等而达到一定的厚度后，沉积就会停止。电泳沉积在组件的导电和/或半导电外表面上形成连续和均匀厚度的共形涂层。此外，电泳沉积涂层优选不形成在叠加于触头116上的剩下的介电层710上，这是因为其具有介电(不导电)特性。换言之，电泳沉积的特点是，只要介电材料层具有足够的厚度，则由于其介电特性，不会在其上形成只能叠加于导体上的介电材料层。典型地，电泳沉积不会发生在厚度大于大约10微米至几十微米的介电层上。
[0084]优选地，共形介电层820由阴极环氧树脂沉积前体形成。或者，聚氨酯或丙烯酸酯沉积前体可被使用。各种电泳涂层前体成分和供应源列举在下面的表1中。
表1
Figure A20088001476400261
表1续
Figure A20088001476400272
[0085]图8B示出了位于结合垫上方的过孔710在电泳沉积之后保持敞开。在电泳沉积了共形介电涂层后，加工过程开始形成导电迹线，其将半导体芯片的前触点垫连接至封装芯片的外触头。
[0086]接下来，参看图9A和9B，基底现在已经准备好进行形成导电迹线126和凸台128的过程。如果在先的过程导致了阻挡住芯片前触点垫116的介电层820，则激光钻销、机械磨削或其它适宜的技术可以用于在这个阶段中打开邻近于前触点垫的过孔底部。此外，如果预先存在的芯片介电层710(图8A)的任何部分保持与触头116对正，则这个层可以在这个步骤中去除。这样的去除可以通过例如激光钻销、机械磨削或其它适宜的技术实现。其它可行的去除技术包括各种选择性蚀刻技术，其可以在本质上是各项同性或各项异性的。各项异性蚀刻过程包括反应性离子蚀刻过程，其中离子流被朝向将被蚀刻的表面引导。为了使得离子以高入射角撞击的表面被蚀刻的程度高于沿着离子流定向的表面，反应性离子蚀刻过程的可选择性通常低于各项同性蚀刻过程。当反应性离子蚀刻过程被使用时，理想地，掩膜层优选沉积成叠加于共形介电涂层820上，并且与过孔708对正的开口被形成在其中。通过这种方式，蚀刻过程避免了去除介电涂层820的除了位于过孔708内的部分之外的部分。
[0087]导电迹线126和凸台128现在被形成为叠加于共形介电涂层820上。形成迹线和凸台的代表性方法涉及沉积金属层，以叠加于共形介电涂层220上。或者，可以在这些表面的各部分被掩膜层保护的情况下进行沉积。金属层优选通过在组件的暴露表面上溅镀初级金属层或通过无电沉积而被沉积。例如，这个步骤可以通过在所述器件晶片的后侧面、壁和下表面上进行均厚沉积而实现。在一个实施方式中，初级金属层包括铝或主要由铝构成。在另一特定实施方式中，初级金属层包括铜或主要由铜构成。在又一实施方式中，初级金属层包括钛或主要由钛构成。一或多种代表性金属可以用在形成初级金属层的过程中。
[0088]然后，可光成像的层被沉积成叠加于初级金属层上，并且三维光刻图案化过程被用于图案化初级金属层，例如描述于Badehi的美国专利No.5,716,759中的过程，所述申请的公开内容以引用方式并入本申请。之后，可光成像的层的保留部分被去除。结果，各导电图案被形成，其对应于将被形成于其上的导电迹线的尺寸。在将初级金属层图案化为各个线后，可光成像的层被从所述器件晶片去除，并且电镀过程被用于将第二金属层电镀到初级金属层上，以形成从前触点垫116沿着壁120延伸并且到达半导体芯片的后侧面114的各导电迹线126。第二金属可以包括镍或其它贵金属。在一个实施方式中，电镀在初级金属层上的第二金属完成了导电迹线。或者，可选的第三金属层例如金、铂或钯可以被镀到第二金属上，用于为完成的导电迹线提供腐蚀抵抗力。
[0089]接下来，作为代表性过程，附加的介电层230被沉积成叠加于沿着后表面114和壁120延伸的每个导电迹线226上。理想地，附加的介电层230通过电泳沉积过程例如参照图8A-B所描述的过程被沉积。包括光阻、氧化物掩膜等等的图案化的掩膜层形成在触头128上。之后，在电泳沉积过程中，通过图案化的掩膜层，避免所产生的介电层230形成在触头128上。图案化掩膜层然后被去除，以将触头128暴露在介电层230中的开口中。
[0090]或者，不是通过电泳沉积来沉积介电层230，介电层可以这样形成，即通过朝向所述器件晶片的后侧面114和壁120旋涂或喷涂可光成像的介电材料例如密封材料或焊料掩膜材料，以形成相对均匀厚度的涂层。之后，通过光刻过程，开口可以形成在共形介电层230中以与触头128对准。在初始沉积可光成像的材料之后，一个或多个过程，例如，加热等可以被执行，以引起介电层230固化。
[0091]接下来，可润湿金属层132，例如，″凸块下金属化″(UBM)层，在介电层230中被形成在开口中，可润湿层与每个触头128接触。在一个代表性过程中，扩散屏蔽层，例如，包含钛、钨、钽或其它类似金属的导电层被形成为与触头128接触。之后，包括第一可润湿金属的层可以沉积成叠加于屏蔽层上，这个层包括金属例如镍、铜或其它金属，其理想地包括贵金属。为了提高抗蚀性，金层，通常非常薄，例如，0.1微米，可以沉积为最终的可润湿金属层。在形成可润湿金属层后，导电凸块134可以形成为与每个触头上的可润湿金属层接触。导电凸块可以形成，其包括可熔性金属例如焊料，锡或低共熔成分，或者其包括导电膏，例如，焊料充填或银充填的膏，等等。导电凸块可以包括一或多种导电材料。在特定的例子中，导电凸块可以包括一或多种贵金属，例如、铜、镍、等。在一个例子中，导电凸块可以这样形成，即通过将包含可熔性金属例如焊料、锡或低共熔的球放在可润湿金属层232上，然后加热其上的导电凸块，以使这些球熔接在可润湿金属层232上。
[0092]最后，封装芯片通过锯切或其它切块方法被沿着切线12彼此切断，以形成单个封装芯片10，如示于图10A-10B。用于将封装芯片切断成各个单元的各种代表性过程描述于这里引用的共同拥有的美国临时申请No.60/761,171和60/775,086中，其中任何一种方法可以用于切断封装芯片以形成示于图10A-10B的单个封装芯片。
[0093]根据本发明的一个实施方式的一种照相机或摄像机模块1030(图11)包括传感器单元1020，其具有触头1042，所述触头布置在传感器单元后侧面、即半导体芯片1000的与承载着成像区域1026的前表面1028相反的表面上。传感器单元可以是例如参照图1所描述和显示的。类似的传感器单元和照相机或摄像机模块描述于共同拥有的2005年11月2日提交的美国专利申请No.11/265,727和2005年12月30日提交的11/322,617，它们进步以代理人案卷号TESSERA3.0-381CIP和3.0-464标识，所述申请的公开内容以引用方式并入本申请。传感器单元的触头1042通过可熔性导电材料例如焊料的块1082连接着电路板1070的端子1080。
[0094]这个配置中的光学单元1050包括转台或支撑结构1051，其具有安装部分1052，所述安装部分被安置成保持一个或多个透镜或其它光学元件1058。支撑结构1051还包括多个后部元件1062，其形式为从安装部分1052向后突伸的细长立柱1062。这些立柱具有后表面1054，其抵接或机械接合传感器单元中的基准平面，以将光学单元相对于传感器单元定位。在示于图11的例子中，后表面1054抵接透明罩盖1034的叠加于成像区域1026上的前表面。或者，转台或支撑结构包括对准特征，例如，柱、销、凹陷或类似物，用于机械地设定光学单元1050相对于芯片1000的高度，同时限制转台相对于芯片成像区域1026的倾斜。
[0095]希望使得立柱1062的后表面和前表面1034之间的连接平整且厚度均匀。在另一实现此目的的措施中，金属附连特征或垫1055可以设置在罩盖1034的外表面1036上，所述金属附连特征或垫通过金属冶金结合，例如，通过扩散结合，结合到位于立柱1062的后表面1054上的金属特征上。或者，某种薄粘合剂可以用于将立柱的后表面结合至罩盖。
[0096]在另一实施方式中，不是使用立柱，而是转台或支撑结构1051包括后部元件，其封闭或基本上封闭圆柱形或多面体形状的容腔。这样的后部元件可以提供为具有圆柱形壁或多面体形状(例如，箱形)的壁，其中后部元件的后表面抵接传感器单元的基准平面，例如提供在罩盖1034的外表面1036上的基准平面。
[0097]在一种对图12中所示的前述实施方式所作的改型中，传感器单元1020被这样安装，即传感器单元的前部并且因此而成像区域1028面向下方，朝向电路板1070的后或底表面。传感器单元的触头1042通过适宜的引线或焊线部1002连接至电路板的导体1076。在这个实施方式中，光学单元1050的后部元件1062突伸穿过电路板中的与成像区域1028对正的孔1072。换言之，孔1072足够大，以容纳从光学元件至成像区域的光路，并且还能容纳后部元件1062。类似的结构可以用于如前所述在前侧面具有触头的传感器单元。
[0098]根据本发明又一实施方式的一种照相机或摄像机模块(图13)包括传感器单元920，如虚线所示，布置在电路板970的底部或后侧。在这里，同样，传感器单元中的芯片的成像区域与电路板中的孔972对正。在这个配置中光学单元950包括转台或支撑结构952，其具有安装部分902，所述安装部分被安置成保持一个或多个透镜或其它光学元件958。支撑结构952还包括多个后部元件962，其形式为从安装部分902向后突伸的细长立柱。这些立柱延伸穿过电路板中的孔眼974，并且因此而机械接合传感器单元，以将光学单元相对于如前所述的传感器单元定位。这里，同样，立柱之间限定出间隙，例如，立柱962a和962b之间的间隙963a。这里，同样，电路板970可以延伸到间隙中，并且因此可以在传感器单元和光学单元之间延伸，这方便了实现连接至如前所述的传感器单元。在图13中的实施方式中，间隙具有很大的高度。完成的组件中的间隙的高度HG等于安装元件902在电路板970的前表面901上方的高度。高度HG理想地大约为2mm或以上，更理想地5mm或以上，最优选1cm或以上。每个间隙的宽度(即，后部元件962a和962b之间平行于电路板的水平距离)理想地也至少为大约2mm，更理想地至少大约5mm，最理想地至少大约1cm。如下面进一步讨论，提供这样大的间隙允许触及到光学元件和孔972之间的空间中，以便对完成的组件执行操作。然而，大的间隙可以提供，而不需要增加组件的整体高度。光学元件例如透镜958和传感器单元之间的距离基于系统光学特性例如透镜958的焦距而确定。因此，在任何情况下，透镜必须被支撑在电路板前方相当大的距离处。
[0099]根据图13中的实施方式的模块或组件可以在组装之后通过一或多个间隙、并且理想地也通过电路板中的孔972对传感器单元执行操作而被处理。例如，组件可以承受清洁操作，其中清洁流体、清洁器具或二者被引入间隙中的一个或多个并且通过孔972，以便清洁传感器模块的表面。例如，在传感器模块组合朝向电路板的后或底表面面向下方的罩盖的地方，罩盖的与孔对正的区域，包括与传感器芯片的成像区域对正的区域，可以被清洁。能够对完成的组件进行这种清洁操作的能力，可以应对组装过程中的各种污染作用。这反过来又可以提供更高质量的照相机或摄像机单元，并且可以允许对组装过程中的可能导致污染的条件的放松。例如，″净室″环境可能就不再是必需的了，或者，价格低的、质量不太高的净室可以被使用。在进一步的例子中，传感器单元可以不采用单独的罩盖，而是可以仅由″裸″半导体芯片构成，该裸半导体芯片具有成像区域并且具有钝化层，钝化层的形式为薄涂层，能够保护裸芯片中的元件在组装过程中不受化学或机械损伤。这样的裸成像芯片在传送过程中典型地要求严格的措施以避免沉积的尘土蒙在一个或多个成像元件上。对于采用罩盖的传感器单元，技术要求相对不那么严格。然而，通过组装之后的后续清洁，不包括罩盖的传感器单元的组装中的技术要求可以不那么严格。
[0100]在根据本发明又一实施方式的方法中，传感器单元可以包括叠加于传感器单元前部的牺牲层，例如，叠加于包括罩盖的传感器单元中的罩盖外表面上的牺牲层，或叠加于不包括罩盖的传感器单元中的芯片的成像区域上的牺牲层。在牺牲层布置就位的情况下，组装较为方便。然后，完成的组件经受下述操作，其中牺牲层或至少是牺牲层的与传感器单元成像区域对正的部分，被通过孔972和通过支撑结构952中的一个或多个间隙963去除。例如，牺牲层可以通过被溶解或通过机械接合牺牲层并将其从传感器单元剥离而去除。去除牺牲层可以去掉任何可能已经聚集在该层上的污染物。
[0101]其它操作也可以通过所述一或多个间隙被执行。例如，工具可以插入一或多个间隙中，以便接合电路板的导体并将它们结合至传感器单元的触头。或者，焊线工具可以用于通过孔972或通过一个或多个附加的孔眼974或通过为此目的提供在电路板中的其它孔眼(未示出)的焊线部而延伸在导体和传感器单元之间。
[0102]并不是必须提供立柱状后部元件来提供如前所述的大间隙。例如，后部元件的形式可以为板或肋。此外，并不是必须提供多个间隙；仅仅一个间隙对于某些操作而言可能就足够了。
[0103]图14示出了根据本发明另一实施方式的光学单元或照相机或摄像机模块。在这个实施方式中，传感器单元1120具有触头1142，其导电连接着叠加于罩盖1128的外表面1138上的电路板的端子1144，例如，通过焊料块1146。罩盖的壁1130优选是倾斜的，以使得壁的边缘1132处的半径是平缓的，并且优选在提供于芯片前表面1102上的一组第一触头1134与壁1130之间形成光滑过渡。一组导电迹线1156从第一触头1134沿着壁1130延伸并且到达罩盖1128的外表面1138，这些导电迹线导电连接着触头1142。介电涂层1158，例如沉积的、优选通过电泳沉积的环氧树脂或其它聚合材料，叠加于导电迹线1156上并且被用作钝化层，例如，带有暴露在触头1142上方的开口的焊料掩膜。
[0104]与参照图12所显示和描述的实施例中一样，光学单元1150具有一组后部元件1162，其从支撑着光学元件1158的结构向后延伸，所述光学元件为例如透镜或选自反射或折射元件、滤光器、反射器和散射器等等的其它光学器件。这里，同样，后部元件的后表面1164被配置成延伸穿过电路板中的孔1172，以便抵接或接合罩盖1128的外表面1138或传感器单元1120的其它基准平面。
[0105]在前面讨论的实施方式中，电路板具有延伸穿过板、与传感器单元的成像区域对正的孔。这样的孔在电路板中形成透明区。在其它实施方式中，电路板包括固体但透明的区，其与传感器单元的成像区域对正。例如，电路板可以由透明介电材料形成，在这种情况下，通过简单地排布电路板的导体的路径以使得没有导体穿过透明区，电路板的透明区可以被提供。
[0106]图15是剖视图，示出了根据封装芯片10(图1)的一种改型的封装芯片1500。如图15中所示，芯片的外部触头1528暴露在由芯片下表面限定的芯片凸缘1515，外部触头1528邻近于半导体芯片的边缘1502被暴露。与外部元件例如电路板之间的互联部可以通过形成接合线1530而实现，该接合线在第一端连接着外部触头1528、在第二端连接着电路板1540的端子1532，电路板具有开口1542与芯片的光电子元件1512例如图像传感器对准。或者，不是采用接合线，导电块，例如焊料块、焊球等等，可以用于将触头1528互联至布置在芯片的后表面114上方的外部元件。
[0107]图16A是剖视图，示出了根据封装芯片10(图1)的一种改型的封装芯片1600。在这个实施方式中，芯片1602中的大开口1604延伸穿过芯片厚度1606的大部分，过孔1608从大开口延伸至前导电触头116。大开口1604可以提供的形式为叠加于各个过孔1608的孔，或者，其形式为延伸越过每个示于图6A的单个芯片的一或多排结合垫的沟槽，或者，其形式为延伸经过包含芯片的晶片(图6B)的长度的沟槽。理想地，在执行形成图16A中所示的封装芯片各步骤之前，处在晶片形式的芯片1606的厚度从其原始厚度减小。例如，在将器件晶片结合至相应的盖子元件之前，包含芯片的器件晶片可以通过从后表面研磨或打磨而减薄，以使得其厚度为大约200微米。如果研磨是在将晶片结合至盖子元件之后进行的，厚度可以减小得更多，例如减小到50微米的厚度。
[0108]在图16A中所示的实施例中，导电迹线1610从芯片的结合垫116沿着过孔1608和开口1604的壁向上延伸。或者，过孔1608可以充填有导电材料。在这种情况下，迹线1610可以从各个过孔沿着由若干过孔共享的开口1604的壁(见朝向后侧面所作的俯视图(图16B))向上延伸。迹线1610在叠加于芯片1602的后表面1614的位置连接着外部触头1628。虽然图1和15至24B示出的实施方式具有充填的小过孔1908(例如，图19A)或沿着过孔(例如，过孔1608)延伸的迹线，但在每种情况下，可更换为导电过孔的备选结构。
[0109]或者，当每个大开口1604中只具有一个过孔时，过孔1608和大开口1604可以充填有导电材料，所述导电材料叠加于布置在过孔1608和开口1604的壁上的介电层1620上。
[0110]图17示出了根据参照图15所显示和描述的实施方式的一种改型的封装芯片。这个例子与图15中所示的结构的不同之处在于，光学透明盖子，而非芯片，具有由下表面限定的邻近于其边缘的凸缘1715和布置在凸缘上的触头1728。图17示出了一种实施方式，其中一个或多个介电层1720、1722，例如，旋涂的介电材料、焊料掩膜等等，可以延伸在盖子的顶表面上。然而，由于盖子1704典型地具有介电特性，因此介电层可能并非必需的，并且通常可以省略。还如图17中所示，盖子的内表面1706通过支撑结构171与芯片的前表面1702分隔。过孔理想地在包含盖子的包覆晶片被结合至包含芯片1700的器件晶片之后被形成，其中支撑结构1710位于所述器件晶片和盖子晶片之间。各种蚀刻、磨削、激光或机械钻销过程，例如前面描述的，可以用于在盖子和支撑结构1710中形成孔1714，以便暴露触头1716，然后过孔被金属化，并且触头1728、迹线等等被形成。
[0111]图18示出了根据图17中所示的实施方式的一种改型的封装芯片，其具有与图16A-B中所示实施方式的相似性。在这个实施方式中，沿着盖子中的大开口1804的壁延伸的迹线1824在第一端连接至金属化过孔1808，在第二端连接至叠加于盖子1820的顶表面1844上的外部触头1828。过孔延伸穿过支撑结构1810到达芯片的导电触头1816。通过附连于外部触头1828的接合线或通过焊料块例如焊球、凸块等，可以提供与外部元件之间的电互联部。
[0112]图19A是剖视图，示出了根据本发明另一实施方式的可叠置的芯片级封装芯片1910。封装芯片可以包括特定类型的微电子器件，例如动态随机存储器(″DRAM″)。封装芯片1910具有与前面描述的封装芯片1600(图16A)类似的特征，即从芯片1901的前侧面1902向内延伸的导电过孔1908连接至沿着芯片的后侧面1914中的大开口的壁延伸的迹线1924。然而，封装芯片1900不包括叠加于前侧面上的盖子，并且导电过孔1908通过沿着芯片1901的前侧面延伸的再分布迹线1912连接着结合垫1909。图19B是朝向封装芯片的后侧面1914所作的相应俯视图。图19A中的视图是沿着图19B中的线19A-19A’所作的。如示于图19B，迹线1924从过孔1908沿着大开口1904的壁1926向上延伸并且到达后表面1914。迹线1924连接至叠加于芯片的后侧面1914上的外部触头1928。参看图19C，朝向芯片1901的前侧面所作的俯视图被提供，芯片包括例如DRAM。在DRAM中，结合垫1909典型地成排提供在存储电路1920之间。图19A是沿着图19C中的线19A-19A’所作视图。前侧面1902上的再分布迹线1912将结合垫1909连接至导电过孔1908。迹线可以如图19B、19C所示布置，以使得一些迹线沿第一方向背离导电过孔延伸，其它迹线沿第二方向背离过孔延伸，其中第二方向与第一方向相反。通过这种方式，导电过孔左侧的结合垫连接着一些导电过孔，导电过孔右侧的结合垫连接着其它导电过孔。
[0113]再次参看图19A，导电过孔1908构成锥形，以使得它们沿着从芯片前侧面1902朝向后侧面1914的方向缩减。导电过孔通过介电层1922与芯片的半导体材料绝缘。叠加于芯片的前侧面1902上的钝化层1924包括导电过孔1908。介电层中的开口1934将触头1936暴露在芯片的前侧面。理想地，前侧面触头1936不与结合垫1909对准，尽管它们也可以对准。
[0114]介电填充材料1940理想地在大开1904中叠加于迹线1924上，以便提供迹线之间的电隔离以及机械支撑封装芯片1901。理想地，介电层1942，例如焊料掩膜，叠加于迹线1924上。介电层中的开口1944暴露出芯片的后侧面触头1946。
[0115]通过提供前侧面触头1936和后侧面触头1946，若干封装芯片可以彼此上下叠置，以形成封装芯片的叠层式组件1950(图19D)。在这样的配置中，前侧面触头与后侧面触头对正。叠层式组件中各相邻封装芯片之间的连接是通过导电块实现的。前侧面的介电层1930和后侧面的介电层1942提供组件中相邻封装芯片1910之间的除了互联部被提供的地方以外的电隔离。
[0116]叠层式组件1950的优点在于，前侧面和后侧面触头相对于封装芯片中的大开口1904偏置。因此，在封装芯片互联时施加在叠层式组件上的压力主要由那些处在背离大开口的位置的触头承担。这样的配置有助于避免在大开口处施加压力至封装芯片，在这种地方，半导体芯片可能会因去除半导体材料以形成大开口而被削弱。
[0117]具有偏置触头的一个潜在益处是能够在芯片的实际结合垫和前后侧面触头之间提供再分布迹线。芯片选择某些类型的存储器例如DRAM的特征，可能要求某些芯片结合垫不连接到直接叠加于它们之上的其它芯片的结合垫。
[0118]图19E是剖视图，示出了示于图19A-19C的实施方式的一种改型。在这种情况下，后侧面触头1946′大开口1904的左侧和右侧暴露在后侧面。类似地，前侧面触头1936′在开口1904的左侧和右侧暴露在前侧面。迹线1926′将两个后侧面触头1946′连接至同一导电过孔1908。图19F是剖视图，示出了相应的叠层式组件，其中导电块1952′将大开口的相应左右侧的前侧面触头结合至至大开口的相应左右侧的后侧面触头。图19E-F中所示的配置的另一可能益处在于减小封装芯片之间的电感，这时由于，对于每个信号，在相邻芯片之间流动的电流现在会流过一组左右触头。
[0119]图20A是剖视图，示出了当芯片包括DRAM时可叠置封装芯片1910的优点。某些类型的半导体芯片包括DRAM包括电容，所述电容形成在从芯片的前侧面向下延伸的具有大高宽比的沟道1960中。通常，芯片的结合垫被布置成紧密邻近于这种沟道型电容的阵列1962。在封装芯片1910中，前侧面触头和后侧面触头之间的互联是通过与沟道型电容阵列1962相隔一些距离的大开口实现的。参看图20B，利用延伸穿过芯片且不与沟道型电容阵列的排布或功能发生冲突的互联部，可以提供层叠体中的相邻芯片1910之间的互联部。
[0120]导电过孔和大开口中迹线之间的互联部可以通过不同方式实现。图21A示出了互联部的一个例子。如示于图21B中的局部放大图，形成为从芯片的前侧面2102向下延伸的导电过孔2108中充填有金属。例如，在从前表面蚀刻了孔后，相对薄层的金属可以被溅镀以罩盖孔的壁和底部。之后，电镀可以用于形成金属填充物。如示于图21B，大开口2104通过化学蚀刻被形成，例如，化学蚀刻选择性蚀刻半导体材料，同时保留导电过孔被形成的金属。过度蚀刻开口2104的结果是完全暴露导电过孔的顶表面2170。之后，介电层2122被形成，然后开口被制作于叠加于过孔2108上的介电层中，例如通过使用激光。激光可以从过孔顶表面上方选择性地去除介电层，这时由于其所处的焦面不同于叠加于大开口底部2106上的介电层所处的焦面。接下来，当导电迹线2124被形成时，迹线接触过孔2108的整个顶表面2170。
[0121]图22A示出了互联部的另一例子。如示于图22B中的局部放大图，在形成导电过孔之后大开口2204通过锯切而形成。然后，在介电层2222被形成后，开口被制作在介电层中，例如通过使用激光。在这个例子中，激光孔径的尺寸被限制，以避免在介电层接触开口2206的底部中的半导体材料的位置处形成开口。
[0122]图23A至23F是剖视图，示出了在芯片的大开口中形成了导电迹线后充填大开口的各种备选方案。如示于图23A，在形成了导电迹线后，可流动的介电填充材料2330被沉积或注入大开口中或到芯片的后侧面上。可流动的介电材料被引起注入到开口中，例如，通过旋涂或热处理，以使得填充材料充入开口2304中，并且提供与后侧面2314大致平齐的表面。然后，焊料掩膜2332被沉积成叠加于填料2330和迹线2328上，焊料掩膜中的开口暴露后侧面触头2346。图23B示出了备选方案，其中填充材料2340具有比大开口更大的体积，以使得填料2340突出到后侧面2304之上。或者，当填料2340不是均匀分布时，填料可以突出到后侧面2314之上。图23C示出了当填料2350的体积小于开口2304的体积或当填料2350被不均匀分布时的另一例子。
[0123]图23D示出了另一备选方案，其类似于图23A中所示的，但其中焊料掩膜层2372在沉积填充材料2370之前被沉积。图23E示出了一个例子，其类似于图23B中所示的，但其中焊料掩膜层2382在沉积填充材料2380之前被沉积。最后，图23F示出了一个例子，其类似于图23C中所示的，但其中焊料掩膜层2392在沉积填充材料2390之前被沉积。
[0124]图24A是剖视图，示出了图19A至19C所示的封装芯片的一种改型。图24B是局部放大图，显示了其导电过孔2408。在这个改型中，导电过孔2408利用沿着朝向芯片的前侧面2402的方向通过大开口应用的过程形成的。在这种情况下，加工过程类似于前面参照图16A-B所描述的。在制造过程中，在前侧面上形成了前侧面触头2436、迹线2432和介电层2422后，包括芯片2400的器件晶片可以以前侧面向下的方式临时安装到承载晶片(未示出)上。在形成了大开口后，孔可以从大开口中形成用作过孔，例如通过激光钻销、蚀刻、机械磨削等。当孔被形成时，承载晶片可以为导电迹线2402提供机械支撑，以有助于将其保持就位于孔的底部。接下来，过孔和大开口可以通过同时加工而金属化，以形成在过孔、大开口内延伸并且到达后侧面2414的导电迹线2442。
[0125]在参照图19A-C所描述的封装芯片1910的另一改型中，图25A示出了一种芯片2510，具有暴露的芯片至芯片互联部，其形式为焊球2550。在这个实施方式中，焊球2550被结合至位于大开口2504内的导电过孔2508的顶表面。导电过孔可以导电连接着芯片2510的前侧面2502上的结合垫2509或其它触头，例如通过导电迹线。钝化层2522叠加于导电迹线2512和结合垫2509上，钝化层2522具有与导电过孔2508对准的开口。图25B示出了一种叠层式组件，包括多个示于图25A的芯片2510，每个芯片与随后相邻的芯片通过它们之间的焊球2550互联。
[0126]图26A示出了图25A中所示的实施方式的一种改型，其中焊球2650被结合至导电过孔2608的底表面2528，以使得其在芯片的前侧面2602下面向下突伸。图26B示出了一种叠层式组件，包括多个芯片2610，它们通过相邻芯片2610之间的焊球2650导电结合在一起。
[0127]图27A示出了图25A中所示的实施方式的另一改型，其中接线柱凸块2750，例如主要由金或其它金属构成，被结合至导电过孔2708的顶表面2718。图27B示出了一种相应的叠层式组件，其中，接线柱凸块2750与相邻芯片的接线柱凸块导电互联。
[0128]图28A示出了又一改型，类似于图26A中所示的，其中接线柱凸块被结合至导电过孔的底表面，以使得接线柱凸块从芯片的前侧面2802向下突伸。图28B示出了一种相应的叠层式组件，其中示于图28A的芯片2810通过接线柱凸块2850导电互联。
[0129]尽管这里参照特定实施方式描述了本发明，但可以理解，这些实施方式仅仅是为了解释本发明的原理和应用。因此，应当理解，在不脱离权利要求中限定的本发明精神和范围的前提下，对所示出的实施方式可以做出多种修改，并且其它配置可以构想出来。
[0130]例如，在本发明的特定的实施方式中，导电迹线从位于半导体芯片的前侧面上的导电特征沿着罩盖半导体芯片的盖子的边缘或沿着形成在盖子中的开口的壁延伸并且到达罩盖元件的外表面。

Claims (46)

1、一种微电子单元，包括：
半导体元件，其具有前表面、远离前表面的后表面，所述前表面和后表面限定出具有第一厚度的薄区和具有至少为第一厚度二倍的第二厚度的厚区，半导体元件包括位于前表面的半导体器件、位于前表面的连接着所述器件的多个第一导电触头、从后表面延伸穿过半导体元件的薄区到达第一导电触头的多个导电过孔；
多个第二导电触头，它们暴露在半导体元件的外部；以及
多个导电迹线，它们将第二导电触头连接至导电过孔。
2、如权利要求1所述的微电子单元，其中，第二导电触头在后表面叠加于所述厚区上。
3、如权利要求2所述的微电子单元，还包括罩盖元件，其至少叠加于布置着半导体器件的前表面部分上。
4、如权利要求3所述的微电子单元，还包括叠加于后表面上的介电层，其中，第二导电触头和导电迹线叠加于介电层上。
5、如权利要求4所述的微电子单元，其中，介电层具有顺应性。
6、一种组件，包括如权利要求5所述的微电子单元和电路板，所述电路板具有结合至第二导电触头的端子，其中，所述介电层的弹性模量和介电层厚度的乘积足够大以补偿微电子单元和电路板之间的热膨胀失配。
7、如权利要求6所述的微电子单元，其中，罩盖元件具有远离半导体元件前侧面的外表面，并且罩盖元件包括暴露在外表面的介电材料。
8、如权利要求1所述的微电子单元，其中，所述多个第二导电触头包括多个金属凸块。
9、一种照相机或摄像机模块，包括如权利要求3所述的微电子单元，其中，半导体器件包括成像区域，照相机或摄像机模块还包括光学单元，所述光学单元具有光学元件，所述光学元件以与成像区域对准的方式安装至罩盖元件。
10、如权利要求1所述的微电子单元，其中，半导体元件包括多个芯片，所述芯片在多条切线处结合在一起。
11、如权利要求1所述的微电子单元，其中，半导体元件包括单一芯片。
12、如权利要求1所述的微电子单元，其中，半导体元件具有延伸在前表面和后表面之间的外周边缘表面，并且第二导电触头被邻近于所述边缘表面布置。
13、一种微电子单元，包括：
半导体元件，其具有前表面、位于前表面的半导体器件、设在前表面的第一导电触头、远离前表面的后表面，所述半导体元件还包括从后表面朝向前表面且部分地穿过半导体元件延伸的具有第一深度的第一孔以及从第一孔延伸至第一导电触头的具有第二深度的第二孔；
多个第一导电过孔，它们沿着第二孔的壁延伸至接触第一导电触头；
多个导电互联部，它们连接着第一导电过孔，所述导电互联部沿着第一孔的壁延伸；
多个第二导电触头，它们连接着所述导电互联部，所述第二触头暴露在半导体元件的外部。
14、如权利要求13所述的微电子单元，其中，第二深度小于第一深度。
15、如权利要求13所述的微电子单元，还包括盖子，其叠加于半导体元件的前表面上。
16、一种微电子单元，包括：
半导体元件，其具有前表面、位于前表面的半导体器件、位于前表面的连接着所述器件的多个第一导电触头；
盖子，其具有面对着半导体元件前表面的内表面、远离内表面的外表面、从外表面朝向内表面且至少部分地穿过盖子延伸的具有第一深度的第一孔；
支撑结构，其在半导体元件的前表面的上方支撑着盖子的内表面，支撑结构具有与第一孔对正的第二孔，第二孔延伸穿过支撑结构到达第一导电触头；
多个第一导电过孔，它们沿着第二孔的壁延伸至接触第一导电触头；
多个第二导电过孔，它们沿着第一孔的壁延伸；
多个第二导电触头，它们暴露在盖子的外部；以及
多个导电迹线，它们将第二导电触头连接至导电过孔。
17、一种微电子单元，包括：
半导体元件，其具有前表面、位于前表面的半导体器件、位于前表面的连接着所述器件的多个第一导电触头；
盖子，其具有面对着半导体元件前表面的内表面、远离内表面的外表面，所述内表面和外表面限定出具有第一厚度的薄区和具有至少为第一厚度二倍的第二厚度的厚区，盖子还包括多个导电过孔，所述导电过孔从外表面延伸穿过盖子的薄区而连接至第一导电触头；
多个第二导电触头；以及
多个导电迹线，它们将第二导电触头连接至导电过孔。
18、一种微电子单元，包括：
盖子，其具有面对着半导体元件前表面的内表面、远离所述前表面的外表面、延伸穿过盖子而接触第一导电触头的多个导电过孔；
多个第二导电触头，它们叠加于盖子外表面上；以及
多个导电迹线，它们将第二导电触头连接至导电过孔。
19、一种微电子单元，包括：
半导体元件，其具有前表面、位于前表面的半导体器件、暴露在前表面的前导电触头、远离前表面的后表面、暴露在后表面的后导电触头；
多个导电过孔，它们连接着前导电触头，所述导电过孔从前表面向下延伸；
开口，其以与导电过孔中的至少一个对准的方式从后表面向下延伸；
导电迹线，其从导电过孔中的至少一个沿着所述开口的壁向上延伸，所述导电迹线连接着后导电触头中的至少一个。
20、如权利要求19所述的微电子单元，其中，导电过孔的距离前表面的最大深度小于所述开口的距离后表面的最大深度。
21、如权利要求19所述的微电子单元，其中，所述开口与所述多个导电过孔对准，并且微电子单元包括多个导电迹线，每个导电迹线将所述多个导电过孔中的一个连接至所述多个后导电触头中的一个。
22、一种叠层式微电子组件，包括多个微电子单元，每个微电子单元如权利要求19所述，其中，一些微电子单元的前导电触头导电连接着其它微电子单元的后导电触头。
23、如权利要求19所述的微电子单元，还包括介电材料，其叠加于所述导电迹线和所述开口的壁上。
24、如权利要求19所述的微电子单元，其中，半导体元件包括从前表面向下延伸的沟道型电容的阵列，并且所述开口不与所述阵列对准。
25、如权利要求19所述的微电子单元，还包括多个导电迹线，其中包括左导电迹线和右导电迹线，每个左导电迹线将导电过孔连接至左后导电触头，每个右导电迹线将导电过孔连接至右后导电触头。
26、一种微电子单元，包括：
半导体元件，其具有前表面、位于前表面的半导体器件、远离前表面的后表面、暴露在后表面的后导电触头；
多个导电过孔，它们从前表面向下延伸；
开口，其以与导电过孔中的至少一个对准的方式从后表面向下延伸；
导电凸块，其结合至所述开口中的导电过孔之一，所述导电凸块从导电过孔延伸至位于由后表面限定的平面上方的位置。
27、如权利要求26所述的微电子单元，其中，导电凸块包括焊料凸块。
28、如权利要求26所述的微电子单元，其中，导电凸块包括接线柱凸块。
29、一种叠层式微电子组件，包括多个微电子单元，每个微电子单元如权利要求26所述，其中，一些微电子单元的导电凸块在一些微电子单元的前表面将导电过孔连接至其它微电子单元的位于开口中的导电过孔。
30、一种微电子单元，包括：
半导体元件，其具有前表面、位于前表面的半导体器件、远离前表面的后表面、暴露在后表面的后导电触头；
多个导电过孔，它们从前表面向下延伸；
开口，其以与导电过孔中的至少一个对准的方式从后表面向下延伸；
导电凸块，其在前表面结合至导电过孔之一，所述导电凸块从前表面向上延伸。
31、一种叠层式微电子组件，包括多个微电子单元，每个微电子单元如权利要求30所述，其中，一些微电子单元的导电凸块在一些微电子单元的前表面将导电过孔连接至其它微电子单元的位于开口中的导电过孔。
32、一种制造微电子单元的方法，包括：
提供半导体元件，其具有前表面、远离前表面的后表面、位于前表面的半导体器件、位于前表面的连接着所述器件的第一导电触头、从后表面延伸穿过半导体元件到达第一导电触头的多个导电过孔；以及
形成叠加于后表面上的多个第二导电触头以及多个导电迹线，所述导电迹线将第二导电触头连接至导电过孔。
33、如权利要求32所述的制造微电子单元的方法，其中，半导体元件包括叠加于第一导电触头上的具有第一厚度的薄区以及具有第二厚度的厚区，所述第二厚度至少为第一厚度的二倍。
34、如权利要求33所述的制造微电子单元的方法，还包括在形成第二导电触头之前在半导体元件上组装罩盖元件，所述罩盖元件叠加于前表面上。
35、如权利要求34所述的方法，还包括在形成第二导电触头和导电迹线之前形成叠加于后表面上的介电层，所述第二导电触头和导电迹线被形成为叠加于介电层上。
36、一种制造微电子单元的方法，包括：
提供半导体元件，其具有前表面、位于前表面的半导体器件、位于前表面的连接着半导体器件的第一导电触头、远离前表面的后表面、暴露在后表面的半导体材料、从后表面延伸穿过半导体元件到达第一导电触头的多个通孔；
在后表面处以及沿着通孔的壁电沉积后介电层到暴露的半导体材料上；以及
形成叠加于后表面上的第二导电触头，在通孔中形成接触第一导电触头的多个导电过孔，以及形成将第二导电触头连接至导电过孔的多个导电迹线。
37、一种制造微电子单元的方法，包括：
(a)将半导体元件与罩盖元件组装在一起，所述罩盖元件叠加于半导体元件的前表面上，由此形成一个单元，半导体元件具有位于前表面的连接着半导体器件的第一导电触头、远离前表面的后表面、从后表面延伸穿过半导体元件到达第一导电触头的多个通孔、暴露在后表面和通孔的壁的半导体材料；
(b)在后表面处以及沿着通孔的壁电沉积介电层，其叠加于暴露的半导体材料上；以及
(c)在介电层上形成：(i)位于通孔中的接触第一导电触头的导电过孔，(ii)叠加于后表面上的多个第二导电触头，以及(iii)将导电过孔连接至第二导电触头的多个导电迹线。
38、如权利要求37所述的制造微电子单元的方法，其中，罩盖元件具有远离半导体元件前侧面的外表面，并且罩盖元件包括暴露在外表面的介电材料。
39、如权利要求37所述的制造微电子单元的方法，其中，半导体元件包括位于前表面和后表面之间的具有第一厚度的第一部分，所述方法还包括将叠加于第一导电触头上的半导体元件部分减薄以形成比第一部分薄的减薄部分，所述通孔延伸穿过所述减薄部分。
40、如权利要求39所述的方法，用于制造多个包覆芯片单元，所述方法还包括：
(d)沿着多条切线将微电子单元切断为多个包覆芯片单元。
41、如权利要求39所述的制造微电子单元的方法，还包括在执行减薄步骤以形成减薄部分之前从后侧面研磨半导体元件以减小第一部分的厚度。
42、如权利要求41所述的方法，其中，半导体元件包括布置在半导体元件的第一导电触头和半导体材料之间的前介电层，所述方法还包括：在执行步骤(c)之前，通过蚀刻半导体元件直至前介电层被暴露而形成所述多个通孔，以及去除通孔中的叠加于第一导电触头上的前介电层部分。
43、如权利要求42所述的方法，其中，所述前介电层部分在执行步骤(b)之后被去除。
44、如权利要求40所述的方法，其中，形成所述多个外部触头的步骤包括形成多个金属凸块。
45、如权利要求37所述的方法，其中，电沉积后介电层的步骤包括用流体聚合成分接触单元的外表面，以及施加流过流体成分的电流以电泳沉积后介电层。
46、如权利要求39所述的方法，其中，半导体芯片包括成像区域，所述方法还包括在单元上组装光学单元，所述光学单元具有与成像区域对准的光学元件，由此形成照相机或摄像机模块，所述光学元件通过罩盖元件与半导体元件分隔。
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Cited By (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102339841A (zh) * 2011-10-08 2012-02-01 江阴长电先进封装有限公司 无硅通孔高可靠性图像传感器封装结构
CN102339843A (zh) * 2011-10-08 2012-02-01 江阴长电先进封装有限公司 无硅通孔低成本图像传感器封装结构
CN102339842A (zh) * 2011-10-08 2012-02-01 江阴长电先进封装有限公司 无硅通孔高可靠性图像传感器封装结构的实现方法
CN102339844A (zh) * 2011-10-08 2012-02-01 江阴长电先进封装有限公司 无硅通孔低成本图像传感器封装结构的实现方法
CN102347271A (zh) * 2010-07-23 2012-02-08 泰塞拉公司 利用微研磨颗粒流形成半导体元件的方法
CN102347283A (zh) * 2010-07-23 2012-02-08 泰塞拉公司 具有覆盖过孔的金属垫的微电子元件
CN102376734A (zh) * 2011-11-07 2012-03-14 江阴长电先进封装有限公司 铆钉互联结构的图像传感器封装结构及实现方法
CN102376733A (zh) * 2011-11-07 2012-03-14 江阴长电先进封装有限公司 铆钉互联结构的图像传感器封装结构
CN102420211A (zh) * 2011-11-14 2012-04-18 江阴长电先进封装有限公司 微凸点互联结构的图像传感器封装结构及实现方法
CN102884623A (zh) * 2010-11-15 2013-01-16 泰塞拉公司 在介电体上具有端子的微电子封装
US8704347B2 (en) 2006-11-22 2014-04-22 Tessera, Inc. Packaged semiconductor chips
US8735287B2 (en) 2007-07-31 2014-05-27 Invensas Corp. Semiconductor packaging process using through silicon vias
CN103871972A (zh) * 2014-03-31 2014-06-18 华为技术有限公司 法兰、半导体功率器件和集成电路板
CN103946972A (zh) * 2011-10-03 2014-07-23 马维尔国际贸易有限公司 去除传导材料以在衬底中形成传导特征
US8796828B2 (en) 2010-12-08 2014-08-05 Tessera, Inc. Compliant interconnects in wafers
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8809190B2 (en) 2010-09-17 2014-08-19 Tessera, Inc. Multi-function and shielded 3D interconnects
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US9041227B2 (en) 2011-10-17 2015-05-26 Invensas Corporation Package-on-package assembly with wire bond vias
US9095074B2 (en) 2012-12-20 2015-07-28 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9099296B2 (en) 2010-12-02 2015-08-04 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages with plural active chips
US9123664B2 (en) 2010-07-19 2015-09-01 Tessera, Inc. Stackable molded microelectronic packages
US9153562B2 (en) 2004-11-03 2015-10-06 Tessera, Inc. Stacked packaging improvements
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US9218988B2 (en) 2005-12-23 2015-12-22 Tessera, Inc. Microelectronic packages and methods therefor
US9224717B2 (en) 2011-05-03 2015-12-29 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9269692B2 (en) 2010-12-02 2016-02-23 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US9299627B2 (en) 2013-01-30 2016-03-29 Kabushiki Kaisha Toshiba Semiconductor package having a cap unit with concave portion and method of manufacturing the same
US9324681B2 (en) 2010-12-13 2016-04-26 Tessera, Inc. Pin attachment
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
CN105980895A (zh) * 2013-12-31 2016-09-28 梅德路米克斯有限公司 用于光波导和接触导线交叉的结构
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9548254B2 (en) 2006-11-22 2017-01-17 Tessera, Inc. Packaged semiconductor chips with array
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9601454B2 (en) 2013-02-01 2017-03-21 Invensas Corporation Method of forming a component having wire bonds and a stiffening layer
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US9691679B2 (en) 2012-02-24 2017-06-27 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
TWI619218B (zh) * 2010-05-11 2018-03-21 精材科技股份有限公司 晶片封裝體及其形成方法
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9953914B2 (en) 2012-05-22 2018-04-24 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
CN108417540A (zh) * 2018-03-26 2018-08-17 李春林 一种指纹识别芯片装置
CN109216384A (zh) * 2017-07-07 2019-01-15 日月光半导体制造股份有限公司 半导体封装装置及制造所述半导体封装装置的方法
CN109216387A (zh) * 2017-07-05 2019-01-15 豪威科技股份有限公司 抗脱层半导体装置以及相关联的方法
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US10460958B2 (en) 2013-08-07 2019-10-29 Invensas Corporation Method of manufacturing embedded packaging with preformed vias
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires

Families Citing this family (127)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7829438B2 (en) 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US7952195B2 (en) 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
US8173906B2 (en) * 2007-02-07 2012-05-08 Raytheon Company Environmental protection coating system and method
US7767589B2 (en) 2007-02-07 2010-08-03 Raytheon Company Passivation layer for a circuit device and method of manufacture
CN101675516B (zh) 2007-03-05 2012-06-20 数字光学欧洲有限公司 具有通过过孔连接到前侧触头的后侧触头的芯片
JP4380718B2 (ja) * 2007-03-15 2009-12-09 ソニー株式会社 半導体装置の製造方法
JP4483896B2 (ja) * 2007-05-16 2010-06-16 ソニー株式会社 半導体装置及びその製造方法
WO2009017758A2 (en) 2007-07-27 2009-02-05 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
CN101861646B (zh) 2007-08-03 2015-03-18 泰塞拉公司 利用再生晶圆的堆叠封装
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
US20100053407A1 (en) * 2008-02-26 2010-03-04 Tessera, Inc. Wafer level compliant packages for rear-face illuminated solid state image sensors
US20090212381A1 (en) * 2008-02-26 2009-08-27 Tessera, Inc. Wafer level packages for rear-face illuminated solid state image sensors
JP5639052B2 (ja) 2008-06-16 2014-12-10 テッセラ，インコーポレイテッド ウェハレベルでの縁部の積重ね
DE102008028757B4 (de) * 2008-06-17 2017-03-16 Epcos Ag Verfahren zur Herstellung einer Halbleiterchipanordnung
KR20100039686A (ko) 2008-10-08 2010-04-16 주식회사 하이닉스반도체 이미지 센서 모듈 및 이의 제조 방법
US7943428B2 (en) * 2008-12-24 2011-05-17 International Business Machines Corporation Bonded semiconductor substrate including a cooling mechanism
WO2010104610A2 (en) 2009-03-13 2010-09-16 Tessera Technologies Hungary Kft. Stacked microelectronic assemblies having vias extending through bond pads
US8280080B2 (en) * 2009-04-28 2012-10-02 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Microcap acoustic transducer device
WO2010138493A1 (en) 2009-05-28 2010-12-02 Hsio Technologies, Llc High performance surface mount electrical interconnect
US9276336B2 (en) 2009-05-28 2016-03-01 Hsio Technologies, Llc Metalized pad to electrical contact interface
US9536815B2 (en) 2009-05-28 2017-01-03 Hsio Technologies, Llc Semiconductor socket with direct selective metalization
US9184527B2 (en) 2009-06-02 2015-11-10 Hsio Technologies, Llc Electrical connector insulator housing
US9603249B2 (en) 2009-06-02 2017-03-21 Hsio Technologies, Llc Direct metalization of electrical circuit structures
US9277654B2 (en) 2009-06-02 2016-03-01 Hsio Technologies, Llc Composite polymer-metal electrical contacts
US8988093B2 (en) 2009-06-02 2015-03-24 Hsio Technologies, Llc Bumped semiconductor wafer or die level electrical interconnect
US8618649B2 (en) * 2009-06-02 2013-12-31 Hsio Technologies, Llc Compliant printed circuit semiconductor package
US9196980B2 (en) 2009-06-02 2015-11-24 Hsio Technologies, Llc High performance surface mount electrical interconnect with external biased normal force loading
US8987886B2 (en) 2009-06-02 2015-03-24 Hsio Technologies, Llc Copper pillar full metal via electrical circuit structure
US9054097B2 (en) 2009-06-02 2015-06-09 Hsio Technologies, Llc Compliant printed circuit area array semiconductor device package
WO2014011226A1 (en) 2012-07-10 2014-01-16 Hsio Technologies, Llc Hybrid printed circuit assembly with low density main core and embedded high density circuit regions
US8610265B2 (en) 2009-06-02 2013-12-17 Hsio Technologies, Llc Compliant core peripheral lead semiconductor test socket
US8928344B2 (en) 2009-06-02 2015-01-06 Hsio Technologies, Llc Compliant printed circuit socket diagnostic tool
US9930775B2 (en) 2009-06-02 2018-03-27 Hsio Technologies, Llc Copper pillar full metal via electrical circuit structure
WO2010141303A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Resilient conductive electrical interconnect
US9613841B2 (en) 2009-06-02 2017-04-04 Hsio Technologies, Llc Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection
US8525346B2 (en) 2009-06-02 2013-09-03 Hsio Technologies, Llc Compliant conductive nano-particle electrical interconnect
WO2011002712A1 (en) 2009-06-29 2011-01-06 Hsio Technologies, Llc Singulated semiconductor device separable electrical interconnect
WO2012074963A1 (en) 2010-12-01 2012-06-07 Hsio Technologies, Llc High performance surface mount electrical interconnect
US9318862B2 (en) 2009-06-02 2016-04-19 Hsio Technologies, Llc Method of making an electronic interconnect
US9184145B2 (en) 2009-06-02 2015-11-10 Hsio Technologies, Llc Semiconductor device package adapter
US8789272B2 (en) 2009-06-02 2014-07-29 Hsio Technologies, Llc Method of making a compliant printed circuit peripheral lead semiconductor test socket
WO2010147934A1 (en) 2009-06-16 2010-12-23 Hsio Technologies, Llc Semiconductor die terminal
WO2010141297A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit wafer level semiconductor package
US8955216B2 (en) 2009-06-02 2015-02-17 Hsio Technologies, Llc Method of making a compliant printed circuit peripheral lead semiconductor package
US9276339B2 (en) 2009-06-02 2016-03-01 Hsio Technologies, Llc Electrical interconnect IC device socket
WO2010141316A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit wafer probe diagnostic tool
US9414500B2 (en) 2009-06-02 2016-08-09 Hsio Technologies, Llc Compliant printed flexible circuit
WO2012061008A1 (en) * 2010-10-25 2012-05-10 Hsio Technologies, Llc High performance electrical circuit structure
WO2012078493A1 (en) 2010-12-06 2012-06-14 Hsio Technologies, Llc Electrical interconnect ic device socket
US8803539B2 (en) 2009-06-03 2014-08-12 Hsio Technologies, Llc Compliant wafer level probe assembly
US8981568B2 (en) 2009-06-16 2015-03-17 Hsio Technologies, Llc Simulated wirebond semiconductor package
US9320144B2 (en) 2009-06-17 2016-04-19 Hsio Technologies, Llc Method of forming a semiconductor socket
US8981809B2 (en) 2009-06-29 2015-03-17 Hsio Technologies, Llc Compliant printed circuit semiconductor tester interface
US8952519B2 (en) * 2010-01-13 2015-02-10 Chia-Sheng Lin Chip package and fabrication method thereof
JP5182448B2 (ja) * 2010-02-18 2013-04-17 株式会社村田製作所 部品内蔵基板
TW201137960A (en) * 2010-04-20 2011-11-01 Raydium Semiconductor Corp Integrated circuit wafer dicing method
US8758067B2 (en) 2010-06-03 2014-06-24 Hsio Technologies, Llc Selective metalization of electrical connector or socket housing
US9689897B2 (en) 2010-06-03 2017-06-27 Hsio Technologies, Llc Performance enhanced semiconductor socket
US9350093B2 (en) 2010-06-03 2016-05-24 Hsio Technologies, Llc Selective metalization of electrical connector or socket housing
US10159154B2 (en) 2010-06-03 2018-12-18 Hsio Technologies, Llc Fusion bonded liquid crystal polymer circuit structure
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
US8598695B2 (en) 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
US8541262B2 (en) * 2010-09-02 2013-09-24 Taiwan Semiconductor Manufacturing Company, Ltd. Die edge contacts for semiconductor devices
US8435835B2 (en) * 2010-09-02 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming base leads from base substrate as standoff for stacking semiconductor die
KR101059490B1 (ko) 2010-11-15 2011-08-25 테세라 리써치 엘엘씨 임베드된 트레이스에 의해 구성된 전도성 패드
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8742541B2 (en) 2010-12-09 2014-06-03 Tessera, Inc. High density three-dimensional integrated capacitors
US8502340B2 (en) 2010-12-09 2013-08-06 Tessera, Inc. High density three-dimensional integrated capacitors
US8486758B2 (en) 2010-12-20 2013-07-16 Tessera, Inc. Simultaneous wafer bonding and interconnect joining
KR101095945B1 (ko) 2011-02-03 2011-12-19 테쎄라 노쓰 아메리카, 아이엔씨. 상이한 파장을 균일하게 수광하기 위한 흡광 재료를 포함하는 이면 조사 센서 패키지
KR101133154B1 (ko) 2011-02-03 2012-04-06 디지털옵틱스 코포레이션 이스트 상이한 파장을 균일하게 수광하기 위한 차등 높이 실리콘을 포함하는 이면 조사 센서 패키지
US8841765B2 (en) 2011-04-22 2014-09-23 Tessera, Inc. Multi-chip module with stacked face-down connected dies
US8975751B2 (en) 2011-04-22 2015-03-10 Tessera, Inc. Vias in porous substrates
US8552518B2 (en) 2011-06-09 2013-10-08 Optiz, Inc. 3D integrated microelectronic assembly with stress reducing interconnects
US8723049B2 (en) 2011-06-09 2014-05-13 Tessera, Inc. Low-stress TSV design using conductive particles
US8546951B2 (en) 2011-06-09 2013-10-01 Optiz, Inc. 3D integration microelectronic assembly for integrated circuit devices
US8546900B2 (en) 2011-06-09 2013-10-01 Optiz, Inc. 3D integration microelectronic assembly for integrated circuit devices
US8604576B2 (en) 2011-07-19 2013-12-10 Opitz, Inc. Low stress cavity package for back side illuminated image sensor, and method of making same
US8816505B2 (en) 2011-07-29 2014-08-26 Tessera, Inc. Low stress vias
US9018725B2 (en) 2011-09-02 2015-04-28 Optiz, Inc. Stepped package for image sensor and method of making same
US8796800B2 (en) 2011-11-21 2014-08-05 Optiz, Inc. Interposer package for CMOS image sensor and method of making same
US8432011B1 (en) 2011-12-06 2013-04-30 Optiz, Inc. Wire bond interposer package for CMOS image sensor and method of making same
US8570669B2 (en) 2012-01-23 2013-10-29 Optiz, Inc Multi-layer polymer lens and method of making same
WO2013115780A1 (en) 2012-01-31 2013-08-08 Hewlett-Packard Development Company, L.P. Hybrid electro-optical package for an opto-electronic engine
US8692344B2 (en) 2012-03-16 2014-04-08 Optiz, Inc Back side illuminated image sensor architecture, and method of making same
US9233511B2 (en) 2012-05-10 2016-01-12 Optiz, Inc. Method of making stamped multi-layer polymer lens
US8772946B2 (en) 2012-06-08 2014-07-08 Invensas Corporation Reduced stress TSV and interposer structures
US9761520B2 (en) 2012-07-10 2017-09-12 Hsio Technologies, Llc Method of making an electrical connector having electrodeposited terminals
US8921759B2 (en) 2012-07-26 2014-12-30 Optiz, Inc. Integrated image sensor package with liquid crystal lens
US8846447B2 (en) 2012-08-23 2014-09-30 Invensas Corporation Thin wafer handling and known good die test method
US8759930B2 (en) * 2012-09-10 2014-06-24 Optiz, Inc. Low profile image sensor package
US8963335B2 (en) 2012-09-13 2015-02-24 Invensas Corporation Tunable composite interposer
JP2014082291A (ja) * 2012-10-16 2014-05-08 Tokyo Electron Ltd 半導体装置の製造方法及び半導体装置
US9076785B2 (en) 2012-12-11 2015-07-07 Invensas Corporation Method and structures for via substrate repair and assembly
US9219091B2 (en) 2013-03-12 2015-12-22 Optiz, Inc. Low profile sensor module and method of making same
US9190443B2 (en) 2013-03-12 2015-11-17 Optiz Inc. Low profile image sensor
US9142695B2 (en) 2013-06-03 2015-09-22 Optiz, Inc. Sensor package with exposed sensor array and method of making same
US10506722B2 (en) 2013-07-11 2019-12-10 Hsio Technologies, Llc Fusion bonded liquid crystal polymer electrical circuit structure
US10667410B2 (en) 2013-07-11 2020-05-26 Hsio Technologies, Llc Method of making a fusion bonded circuit structure
US9496247B2 (en) 2013-08-26 2016-11-15 Optiz, Inc. Integrated camera module and method of making same
US9461190B2 (en) 2013-09-24 2016-10-04 Optiz, Inc. Low profile sensor package with cooling feature and method of making same
TWI525673B (zh) * 2013-10-08 2016-03-11 精材科技股份有限公司 晶圓級晶片封裝體的製造方法
MA36343B1 (fr) * 2013-10-14 2016-04-29 Nemotek Technologies Procédé de métallisation en cuivre destiné à la fabrication d'un circuit intégré en utilisant la technologie wafer level packaging 3d
US9496297B2 (en) 2013-12-05 2016-11-15 Optiz, Inc. Sensor package with cooling feature and method of making same
US9667900B2 (en) 2013-12-09 2017-05-30 Optiz, Inc. Three dimensional system-on-chip image sensor package
US9454177B2 (en) * 2014-02-14 2016-09-27 Apple Inc. Electronic devices with housing-based interconnects and coupling structures
US9985063B2 (en) 2014-04-22 2018-05-29 Optiz, Inc. Imaging device with photo detectors and color filters arranged by color transmission characteristics and absorption coefficients
US9524917B2 (en) 2014-04-23 2016-12-20 Optiz, Inc. Chip level heat dissipation using silicon
US9666730B2 (en) 2014-08-18 2017-05-30 Optiz, Inc. Wire bond sensor package
TWI569427B (zh) * 2014-10-22 2017-02-01 精材科技股份有限公司 半導體封裝件及其製法
US9543347B2 (en) 2015-02-24 2017-01-10 Optiz, Inc. Stress released image sensor package structure and method
US9755335B2 (en) 2015-03-18 2017-09-05 Hsio Technologies, Llc Low profile electrical interconnect with fusion bonded contact retention and solder wick reduction
FR3041147B1 (fr) * 2015-09-14 2018-02-02 3Dis Tech Procede d'integration d'au moins une interconnexion 3d pour la fabrication de circuit integre
CN205752132U (zh) * 2016-05-19 2016-11-30 深圳市汇顶科技股份有限公司 硅通孔芯片、指纹识别传感器和终端设备
KR102624624B1 (ko) * 2016-06-15 2024-01-12 삼성디스플레이 주식회사 집적 회로 및 그 제조 방법
US10769854B2 (en) 2016-07-12 2020-09-08 Tyco Fire & Security Gmbh Holographic technology implemented security solution
US10283445B2 (en) 2016-10-26 2019-05-07 Invensas Corporation Bonding of laminates with electrical interconnects
US9996725B2 (en) 2016-11-03 2018-06-12 Optiz, Inc. Under screen sensor assembly
DE102017212763A1 (de) * 2017-07-25 2019-01-31 Infineon Technologies Ag Eine Vorrichtung und ein Verfahren zum Herstellen einer Vorrichtung
CN107888812A (zh) * 2017-11-27 2018-04-06 维沃移动通信有限公司 一种电子设备及电子设备的摄像模组
JP7021021B2 (ja) * 2018-07-25 2022-02-16 日産自動車株式会社 半導体装置及びその製造方法
DE102018131386A1 (de) * 2018-12-07 2020-06-10 Osram Opto Semiconductors Gmbh Verfahren zur herstellung von optoelektronischen halbleiterbauteilen und optoelektronisches halbleiterbauteil
FR3093592B1 (fr) 2019-03-04 2021-05-07 St Microelectronics Tours Sas Circuit intégré comportant un condensateur tridimensionnel
US11605576B2 (en) * 2019-06-25 2023-03-14 Semiconductor Components Industries, Llc Via for semiconductor devices and related methods
US11408589B2 (en) 2019-12-05 2022-08-09 Optiz, Inc. Monolithic multi-focus light source device

Family Cites Families (230)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160645A (ja) * 1984-02-01 1985-08-22 Hitachi Ltd 積層半導体集積回路装置
NL8403613A (nl) * 1984-11-28 1986-06-16 Philips Nv Elektronenbundelinrichting en halfgeleiderinrichting voor een dergelijke inrichting.
US4765864A (en) * 1987-07-15 1988-08-23 Sri International Etching method for producing an electrochemical cell in a crystalline substrate
JPH0817177B2 (ja) * 1987-11-16 1996-02-21 日産自動車株式会社 半導体装置
EP0316799B1 (en) 1987-11-13 1994-07-27 Nissan Motor Co., Ltd. Semiconductor device
US5229647A (en) 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US5322816A (en) * 1993-01-19 1994-06-21 Hughes Aircraft Company Method for forming deep conductive feedthroughs
IL106892A0 (en) 1993-09-02 1993-12-28 Pierre Badehi Methods and apparatus for producing integrated circuit devices
US5380681A (en) * 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
IL110261A0 (en) * 1994-07-10 1994-10-21 Schellcase Ltd Packaged integrated circuit
GB2292015B (en) * 1994-07-29 1998-07-22 Plessey Semiconductors Ltd Trimmable inductor structure
US6826827B1 (en) * 1994-12-29 2004-12-07 Tessera, Inc. Forming conductive posts by selective removal of conductive material
JP3186941B2 (ja) * 1995-02-07 2001-07-11 シャープ株式会社 半導体チップおよびマルチチップ半導体モジュール
US5703408A (en) * 1995-04-10 1997-12-30 United Microelectronics Corporation Bonding pad structure and method thereof
US5821608A (en) * 1995-09-08 1998-10-13 Tessera, Inc. Laterally situated stress/strain relieving lead for a semiconductor chip package
US6284563B1 (en) * 1995-10-31 2001-09-04 Tessera, Inc. Method of making compliant microelectronic assemblies
US6013948A (en) * 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US5686762A (en) * 1995-12-21 1997-11-11 Micron Technology, Inc. Semiconductor device with improved bond pads
TW343210B (en) * 1996-01-12 1998-10-21 Matsushita Electric Works Ltd Process for impregnating a substrate, impregnated substrate and products thereof
US5808874A (en) * 1996-05-02 1998-09-15 Tessera, Inc. Microelectronic connections with liquid conductive elements
US5700735A (en) * 1996-08-22 1997-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bond pad structure for the via plug process
JP3620936B2 (ja) * 1996-10-11 2005-02-16 浜松ホトニクス株式会社 裏面照射型受光デバイスおよびその製造方法
US6143396A (en) * 1997-05-01 2000-11-07 Texas Instruments Incorporated System and method for reinforcing a bond pad
JP3725300B2 (ja) 1997-06-26 2005-12-07 松下電器産業株式会社 Ａｃｆ接合構造
US6573609B2 (en) * 1997-11-25 2003-06-03 Tessera, Inc. Microelectronic component with rigid interposer
EP0926723B1 (en) * 1997-11-26 2007-01-17 STMicroelectronics S.r.l. Process for forming front-back through contacts in micro-integrated electronic devices
US6620731B1 (en) 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
JP3447941B2 (ja) 1998-01-05 2003-09-16 株式会社東芝 半導体装置及びその製造方法
TW410392B (en) * 1998-01-23 2000-11-01 Rohm Co Ltd Damascene interconnection and semiconductor device
US6982475B1 (en) * 1998-03-20 2006-01-03 Mcsp, Llc Hermetic wafer scale integrated circuit structure
US5986343A (en) 1998-05-04 1999-11-16 Lucent Technologies Inc. Bond pad design for integrated circuits
US6492201B1 (en) * 1998-07-10 2002-12-10 Tessera, Inc. Forming microelectronic connection components by electrophoretic deposition
US6103552A (en) * 1998-08-10 2000-08-15 Lin; Mou-Shiung Wafer scale packaging scheme
US6261865B1 (en) * 1998-10-06 2001-07-17 Micron Technology, Inc. Multi chip semiconductor package and method of construction
JP2000195896A (ja) * 1998-12-25 2000-07-14 Nec Corp 半導体装置
US6181016B1 (en) * 1999-06-08 2001-01-30 Winbond Electronics Corp Bond-pad with a single anchoring structure
US6368410B1 (en) * 1999-06-28 2002-04-09 General Electric Company Semiconductor processing article
US6168965B1 (en) * 1999-08-12 2001-01-02 Tower Semiconductor Ltd. Method for making backside illuminated image sensor
JP4139533B2 (ja) * 1999-09-10 2008-08-27 大日本印刷株式会社 半導体装置とその製造方法
US6277669B1 (en) * 1999-09-15 2001-08-21 Industrial Technology Research Institute Wafer level packaging method and packages formed
JP2001127243A (ja) * 1999-10-26 2001-05-11 Sharp Corp 積層半導体装置
JP3399456B2 (ja) * 1999-10-29 2003-04-21 株式会社日立製作所 半導体装置およびその製造方法
US6507113B1 (en) * 1999-11-19 2003-01-14 General Electric Company Electronic interface structures and methods of fabrication
JP3684978B2 (ja) 2000-02-03 2005-08-17 セイコーエプソン株式会社 半導体装置およびその製造方法ならびに電子機器
US6498387B1 (en) * 2000-02-15 2002-12-24 Wen-Ken Yang Wafer level package and the process of the same
US6586955B2 (en) * 2000-03-13 2003-07-01 Tessera, Inc. Methods and structures for electronic probing arrays
JP3879816B2 (ja) * 2000-06-02 2007-02-14 セイコーエプソン株式会社 半導体装置及びその製造方法、積層型半導体装置、回路基板並びに電子機器
US6472247B1 (en) * 2000-06-26 2002-10-29 Ricoh Company, Ltd. Solid-state imaging device and method of production of the same
US6399892B1 (en) 2000-09-19 2002-06-04 International Business Machines Corporation CTE compensated chip interposer
JP3433193B2 (ja) 2000-10-23 2003-08-04 松下電器産業株式会社 半導体チップおよびその製造方法
US6693358B2 (en) * 2000-10-23 2004-02-17 Matsushita Electric Industrial Co., Ltd. Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device
EP1207015A3 (en) * 2000-11-17 2003-07-30 Keltech Engineering, Inc. Raised island abrasive, method of use and lapping apparatus
JP2002162212A (ja) 2000-11-24 2002-06-07 Foundation Of River & Basin Integrated Communications Japan 堤体ひずみ計測センサ
US20020098620A1 (en) * 2001-01-24 2002-07-25 Yi-Chuan Ding Chip scale package and manufacturing method thereof
KR100352236B1 (ko) * 2001-01-30 2002-09-12 삼성전자 주식회사 접지 금속층을 갖는 웨이퍼 레벨 패키지
US6867123B2 (en) * 2001-02-08 2005-03-15 Renesas Technology Corp. Semiconductor integrated circuit device and its manufacturing method
KR100364635B1 (ko) * 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
US6498381B2 (en) 2001-02-22 2002-12-24 Tru-Si Technologies, Inc. Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same
JP2002270718A (ja) * 2001-03-07 2002-09-20 Seiko Epson Corp 配線基板及びその製造方法、半導体装置及びその製造方法、回路基板並びに電子機器
JP2002359347A (ja) 2001-03-28 2002-12-13 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP2002373957A (ja) 2001-06-14 2002-12-26 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP2003020404A (ja) 2001-07-10 2003-01-24 Hitachi Ltd 耐熱性低弾性率材およびそれを用いた装置
US6531384B1 (en) 2001-09-14 2003-03-11 Motorola, Inc. Method of forming a bond pad and structure thereof
US20030059976A1 (en) * 2001-09-24 2003-03-27 Nathan Richard J. Integrated package and methods for making same
JP2003124393A (ja) * 2001-10-17 2003-04-25 Hitachi Ltd 半導体装置およびその製造方法
US6727576B2 (en) * 2001-10-31 2004-04-27 Infineon Technologies Ag Transfer wafer level packaging
US20040051173A1 (en) * 2001-12-10 2004-03-18 Koh Philip Joseph High frequency interconnect system using micromachined plugs and sockets
TW544882B (en) 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
TW517361B (en) 2001-12-31 2003-01-11 Megic Corp Chip package structure and its manufacture process
US6743660B2 (en) * 2002-01-12 2004-06-01 Taiwan Semiconductor Manufacturing Co., Ltd Method of making a wafer level chip scale package
JP2003282791A (ja) 2002-03-20 2003-10-03 Fujitsu Ltd 接触型センサ内蔵半導体装置及びその製造方法
JP2003318178A (ja) 2002-04-24 2003-11-07 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
TWI229435B (en) * 2002-06-18 2005-03-11 Sanyo Electric Co Manufacture of semiconductor device
US6716737B2 (en) 2002-07-29 2004-04-06 Hewlett-Packard Development Company, L.P. Method of forming a through-substrate interconnect
US7030010B2 (en) * 2002-08-29 2006-04-18 Micron Technology, Inc. Methods for creating electrophoretically insulated vias in semiconductive substrates and resulting structures
US6903442B2 (en) * 2002-08-29 2005-06-07 Micron Technology, Inc. Semiconductor component having backside pin contacts
US7329563B2 (en) * 2002-09-03 2008-02-12 Industrial Technology Research Institute Method for fabrication of wafer level package incorporating dual compliant layers
JP4440554B2 (ja) 2002-09-24 2010-03-24 浜松ホトニクス株式会社 半導体装置
WO2004030102A1 (ja) 2002-09-24 2004-04-08 Hamamatsu Photonics K.K. フォトダイオードアレイ及びその製造方法
JP2004128063A (ja) 2002-09-30 2004-04-22 Toshiba Corp 半導体装置及びその製造方法
US20040104454A1 (en) * 2002-10-10 2004-06-03 Rohm Co., Ltd. Semiconductor device and method of producing the same
TW569395B (en) 2002-10-30 2004-01-01 Intelligent Sources Dev Corp Method of forming a stacked-gate cell structure and its NAND-type flash memory array
US20050012225A1 (en) * 2002-11-15 2005-01-20 Choi Seung-Yong Wafer-level chip scale package and method for fabricating and using the same
JP3918935B2 (ja) 2002-12-20 2007-05-23 セイコーエプソン株式会社 半導体装置の製造方法
JP4072677B2 (ja) * 2003-01-15 2008-04-09 セイコーエプソン株式会社 半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器
JP2004356618A (ja) 2003-03-19 2004-12-16 Ngk Spark Plug Co Ltd 中継基板、半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体、中継基板の製造方法
SG137651A1 (en) * 2003-03-14 2007-12-28 Micron Technology Inc Microelectronic devices and methods for packaging microelectronic devices
JP3680839B2 (ja) * 2003-03-18 2005-08-10 セイコーエプソン株式会社 半導体装置および半導体装置の製造方法
US6841883B1 (en) * 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
EP1519410A1 (en) * 2003-09-25 2005-03-30 Interuniversitair Microelektronica Centrum vzw ( IMEC) Method for producing electrical through hole interconnects and devices made thereof
US6908856B2 (en) * 2003-04-03 2005-06-21 Interuniversitair Microelektronica Centrum (Imec) Method for producing electrical through hole interconnects and devices made thereof
JP4373695B2 (ja) 2003-04-16 2009-11-25 浜松ホトニクス株式会社 裏面照射型光検出装置の製造方法
DE10319538B4 (de) * 2003-04-30 2008-01-17 Qimonda Ag Halbleitervorrichtung und Verfahren zur Herstellung einer Halbleitereinrichtung
EP1482553A3 (en) * 2003-05-26 2007-03-28 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US6972480B2 (en) * 2003-06-16 2005-12-06 Shellcase Ltd. Methods and apparatus for packaging integrated circuit devices
US6927156B2 (en) * 2003-06-18 2005-08-09 Intel Corporation Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon
JP3646720B2 (ja) * 2003-06-19 2005-05-11 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP5058597B2 (ja) * 2003-06-20 2012-10-24 エヌエックスピー ビー ヴィ 電子デバイス、アセンブリ、電子デバイスの製造方法
JP2005026405A (ja) 2003-07-01 2005-01-27 Sharp Corp 貫通電極構造およびその製造方法、半導体チップならびにマルチチップ半導体装置
JP2005045073A (ja) 2003-07-23 2005-02-17 Hamamatsu Photonics Kk 裏面入射型光検出素子
JP4499386B2 (ja) * 2003-07-29 2010-07-07 浜松ホトニクス株式会社 裏面入射型光検出素子の製造方法
KR100537892B1 (ko) * 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7180149B2 (en) * 2003-08-28 2007-02-20 Fujikura Ltd. Semiconductor package with through-hole
JP2005093486A (ja) 2003-09-12 2005-04-07 Seiko Epson Corp 半導体装置の製造方法及び半導体装置
JP2005101268A (ja) * 2003-09-25 2005-04-14 Sanyo Electric Co Ltd 半導体装置の製造方法
US7129576B2 (en) * 2003-09-26 2006-10-31 Tessera, Inc. Structure and method of making capped chips including vertical interconnects having stud bumps engaged to surfaces of said caps
JP4948756B2 (ja) * 2003-09-30 2012-06-06 アギア システムズ インコーポレーテッド 集積回路内に形成されたインダクタ及びその製造方法
US7495179B2 (en) * 2003-10-06 2009-02-24 Tessera, Inc. Components with posts and pads
TWI259564B (en) * 2003-10-15 2006-08-01 Infineon Technologies Ag Wafer level packages for chips with sawn edge protection
TWI234244B (en) 2003-12-26 2005-06-11 Intelligent Sources Dev Corp Paired stack-gate flash cell structure and its contactless NAND-type flash memory arrays
US20050156330A1 (en) * 2004-01-21 2005-07-21 Harris James M. Through-wafer contact to bonding pad
JP4198072B2 (ja) * 2004-01-23 2008-12-17 シャープ株式会社 半導体装置、光学装置用モジュール及び半導体装置の製造方法
JP2005216921A (ja) * 2004-01-27 2005-08-11 Hitachi Maxell Ltd 半導体装置製造用のメタルマスク及び半導体装置の製造方法
US7026175B2 (en) 2004-03-29 2006-04-11 Applied Materials, Inc. High throughput measurement of via defects in interconnects
US7368695B2 (en) * 2004-05-03 2008-05-06 Tessera, Inc. Image sensor package and fabrication method
US20050248002A1 (en) * 2004-05-07 2005-11-10 Michael Newman Fill for large volume vias
KR100618837B1 (ko) * 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
JP4343044B2 (ja) 2004-06-30 2009-10-14 新光電気工業株式会社 インターポーザ及びその製造方法並びに半導体装置
JP2006019455A (ja) * 2004-06-30 2006-01-19 Nec Electronics Corp 半導体装置およびその製造方法
KR100605314B1 (ko) * 2004-07-22 2006-07-28 삼성전자주식회사 재배선 보호 피막을 가지는 웨이퍼 레벨 패키지의 제조 방법
JP2006041148A (ja) * 2004-07-27 2006-02-09 Seiko Epson Corp 半導体装置の製造方法、半導体装置、及び電子機器
US7750487B2 (en) * 2004-08-11 2010-07-06 Intel Corporation Metal-metal bonding of compliant interconnect
US7598167B2 (en) * 2004-08-24 2009-10-06 Micron Technology, Inc. Method of forming vias in semiconductor substrates without damaging active regions thereof and resulting structures
US7378342B2 (en) * 2004-08-27 2008-05-27 Micron Technology, Inc. Methods for forming vias varying lateral dimensions
US7129567B2 (en) * 2004-08-31 2006-10-31 Micron Technology, Inc. Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements
KR100604049B1 (ko) 2004-09-01 2006-07-24 동부일렉트로닉스 주식회사 반도체 칩 패키지 및 그 제조방법
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
JP4139803B2 (ja) * 2004-09-28 2008-08-27 シャープ株式会社 半導体装置の製造方法
JP4246132B2 (ja) * 2004-10-04 2009-04-02 シャープ株式会社 半導体装置およびその製造方法
KR100676493B1 (ko) 2004-10-08 2007-02-01 디엔제이 클럽 인코 재배선 기판을 이용한 웨이퍼 레벨 칩 스케일 패키지의제조 방법
US7819119B2 (en) * 2004-10-08 2010-10-26 Ric Investments, Llc User interface having a pivotable coupling
US7081408B2 (en) 2004-10-28 2006-07-25 Intel Corporation Method of creating a tapered via using a receding mask and resulting structure
JP4873517B2 (ja) 2004-10-28 2012-02-08 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
US20060278997A1 (en) * 2004-12-01 2006-12-14 Tessera, Inc. Soldered assemblies and methods of making the same
JP4795677B2 (ja) 2004-12-02 2011-10-19 ルネサスエレクトロニクス株式会社 半導体装置およびそれを用いた半導体モジュール、ならびに半導体装置の製造方法
JP4290158B2 (ja) 2004-12-20 2009-07-01 三洋電機株式会社 半導体装置
KR20060087273A (ko) * 2005-01-28 2006-08-02 삼성전기주식회사 반도체 패키지및 그 제조방법
TWI313914B (en) * 2005-01-31 2009-08-21 Sanyo Electric Co Semiconductor device and a method for manufacturing thereof
US7675153B2 (en) * 2005-02-02 2010-03-09 Kabushiki Kaisha Toshiba Semiconductor device having semiconductor chips stacked and mounted thereon and manufacturing method thereof
US7538032B2 (en) * 2005-06-23 2009-05-26 Teledyne Scientific & Imaging, Llc Low temperature method for fabricating high-aspect ratio vias and devices fabricated by said method
TWI244186B (en) 2005-03-02 2005-11-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
TWI264807B (en) 2005-03-02 2006-10-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
US20060264029A1 (en) * 2005-05-23 2006-11-23 Intel Corporation Low inductance via structures
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
JP4694305B2 (ja) 2005-08-16 2011-06-08 ルネサスエレクトロニクス株式会社 半導体ウエハの製造方法
US20070049470A1 (en) * 2005-08-29 2007-03-01 Johnson Health Tech Co., Ltd. Rapid circuit training machine with dual resistance
US7772115B2 (en) 2005-09-01 2010-08-10 Micron Technology, Inc. Methods for forming through-wafer interconnects, intermediate structures so formed, and devices and systems having at least one solder dam structure
US20070052050A1 (en) 2005-09-07 2007-03-08 Bart Dierickx Backside thinned image sensor with integrated lens stack
JP2007157844A (ja) 2005-12-01 2007-06-21 Sharp Corp 半導体装置、および半導体装置の製造方法
US20070126085A1 (en) 2005-12-02 2007-06-07 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
US7456479B2 (en) 2005-12-15 2008-11-25 United Microelectronics Corp. Method for fabricating a probing pad of an integrated circuit chip
JP4826248B2 (ja) 2005-12-19 2011-11-30 Ｔｄｋ株式会社 Ｉｃ内蔵基板の製造方法
KR100714310B1 (ko) 2006-02-23 2007-05-02 삼성전자주식회사 변압기 또는 안테나를 구비하는 반도체 패키지들
US20080029879A1 (en) 2006-03-01 2008-02-07 Tessera, Inc. Structure and method of making lidded chips
JP4659660B2 (ja) 2006-03-31 2011-03-30 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
JP2007311676A (ja) 2006-05-22 2007-11-29 Sony Corp 半導体装置とその製造方法
KR100837269B1 (ko) 2006-05-22 2008-06-11 삼성전자주식회사 웨이퍼 레벨 패키지 및 그 제조 방법
JP4950559B2 (ja) 2006-05-25 2012-06-13 パナソニック株式会社 スルーホール電極の形成方法
US7605019B2 (en) 2006-07-07 2009-10-20 Qimonda Ag Semiconductor device with stacked chips and method for manufacturing thereof
KR100750741B1 (ko) 2006-09-15 2007-08-22 삼성전기주식회사 캡 웨이퍼, 이를 구비한 반도체 칩, 및 그 제조방법
US7531445B2 (en) 2006-09-26 2009-05-12 Hymite A/S Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane
US20080079779A1 (en) 2006-09-28 2008-04-03 Robert Lee Cornell Method for Improving Thermal Conductivity in Micro-Fluid Ejection Heads
JP2008091632A (ja) 2006-10-02 2008-04-17 Manabu Bonshihara 半導体装置の外部回路接続部の構造及びその形成方法
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US7759166B2 (en) 2006-10-17 2010-07-20 Tessera, Inc. Microelectronic packages fabricated at the wafer level and methods therefor
US7719121B2 (en) * 2006-10-17 2010-05-18 Tessera, Inc. Microelectronic packages and methods therefor
US7807508B2 (en) 2006-10-31 2010-10-05 Tessera Technologies Hungary Kft. Wafer-level fabrication of lidded chips with electrodeposited dielectric coating
US7935568B2 (en) * 2006-10-31 2011-05-03 Tessera Technologies Ireland Limited Wafer-level fabrication of lidded chips with electrodeposited dielectric coating
KR100830581B1 (ko) 2006-11-06 2008-05-22 삼성전자주식회사 관통전극을 구비한 반도체 소자 및 그 형성방법
US7781781B2 (en) 2006-11-17 2010-08-24 International Business Machines Corporation CMOS imager array with recessed dielectric
US7791199B2 (en) 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US20080136038A1 (en) * 2006-12-06 2008-06-12 Sergey Savastiouk Integrated circuits with conductive features in through holes passing through other conductive features and through a semiconductor substrate
FR2911006A1 (fr) 2007-01-03 2008-07-04 St Microelectronics Sa Puce de circuit electronique integre comprenant une inductance
JP2008177249A (ja) 2007-01-16 2008-07-31 Sharp Corp 半導体集積回路のボンディングパッド、その製造方法、半導体集積回路、並びに電子機器
US7518226B2 (en) 2007-02-06 2009-04-14 Stats Chippac Ltd. Integrated circuit packaging system with interposer
CN101675516B (zh) * 2007-03-05 2012-06-20 数字光学欧洲有限公司 具有通过过孔连接到前侧触头的后侧触头的芯片
JP4380718B2 (ja) 2007-03-15 2009-12-09 ソニー株式会社 半導体装置の製造方法
KR100845006B1 (ko) 2007-03-19 2008-07-09 삼성전자주식회사 적층 칩 패키지 및 그 제조 방법
JP2008258258A (ja) 2007-04-02 2008-10-23 Sanyo Electric Co Ltd 半導体装置
US7977155B2 (en) 2007-05-04 2011-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level flip-chip assembly methods
US20080284041A1 (en) 2007-05-18 2008-11-20 Samsung Electronics Co., Ltd. Semiconductor package with through silicon via and related method of fabrication
JP4937842B2 (ja) 2007-06-06 2012-05-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7767497B2 (en) * 2007-07-12 2010-08-03 Tessera, Inc. Microelectronic package element and method of fabricating thereof
US7932179B2 (en) 2007-07-27 2011-04-26 Micron Technology, Inc. Method for fabricating semiconductor device having backside redistribution layers
WO2009017758A2 (en) 2007-07-27 2009-02-05 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
KR101538648B1 (ko) 2007-07-31 2015-07-22 인벤사스 코포레이션 실리콘 쓰루 비아를 사용하는 반도체 패키지 공정
KR101387701B1 (ko) 2007-08-01 2014-04-23 삼성전자주식회사 반도체 패키지 및 이의 제조방법
US7902069B2 (en) 2007-08-02 2011-03-08 International Business Machines Corporation Small area, robust silicon via structure and process
WO2009023462A1 (en) 2007-08-10 2009-02-19 Spansion Llc Semiconductor device and method for manufacturing thereof
KR100885924B1 (ko) 2007-08-10 2009-02-26 삼성전자주식회사 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법
KR100905784B1 (ko) 2007-08-16 2009-07-02 주식회사 하이닉스반도체 반도체 패키지용 관통 전극 및 이를 갖는 반도체 패키지
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
JP2009088201A (ja) 2007-09-28 2009-04-23 Nec Electronics Corp 半導体装置
JP2009129953A (ja) 2007-11-20 2009-06-11 Hitachi Ltd 半導体装置
US20090127667A1 (en) 2007-11-21 2009-05-21 Powertech Technology Inc. Semiconductor chip device having through-silicon-via (TSV) and its fabrication method
US7998524B2 (en) 2007-12-10 2011-08-16 Abbott Cardiovascular Systems Inc. Methods to improve adhesion of polymer coatings over stents
US7446036B1 (en) 2007-12-18 2008-11-04 International Business Machines Corporation Gap free anchored conductor and dielectric structure and method for fabrication thereof
WO2009104668A1 (ja) 2008-02-21 2009-08-27 日本電気株式会社 配線基板及び半導体装置
US20090212381A1 (en) 2008-02-26 2009-08-27 Tessera, Inc. Wafer level packages for rear-face illuminated solid state image sensors
US7791174B2 (en) 2008-03-07 2010-09-07 Advanced Inquiry Systems, Inc. Wafer translator having a silicon core isolated from signal paths by a ground plane
US7842548B2 (en) 2008-04-22 2010-11-30 Taiwan Semconductor Manufacturing Co., Ltd. Fixture for P-through silicon via assembly
US20090267183A1 (en) 2008-04-28 2009-10-29 Research Triangle Institute Through-substrate power-conducting via with embedded capacitance
US7939449B2 (en) 2008-06-03 2011-05-10 Micron Technology, Inc. Methods of forming hybrid conductive vias including small dimension active surface ends and larger dimension back side ends
US7863721B2 (en) 2008-06-11 2011-01-04 Stats Chippac, Ltd. Method and apparatus for wafer level integration using tapered vias
US20100013060A1 (en) 2008-06-22 2010-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a conductive trench in a silicon wafer and silicon wafer comprising such trench
JP5183340B2 (ja) 2008-07-23 2013-04-17 日本電波工業株式会社 表面実装型の発振器およびこの発振器を搭載した電子機器
KR20100020718A (ko) 2008-08-13 2010-02-23 삼성전자주식회사 반도체 칩, 그 스택 구조 및 이들의 제조 방법
US20100117242A1 (en) 2008-11-10 2010-05-13 Miller Gary L Technique for packaging multiple integrated circuits
US7906404B2 (en) 2008-11-21 2011-03-15 Teledyne Scientific & Imaging, Llc Power distribution for CMOS circuits using in-substrate decoupling capacitors and back side metal layers
US7939926B2 (en) 2008-12-12 2011-05-10 Qualcomm Incorporated Via first plus via last technique for IC interconnects
JP5308145B2 (ja) 2008-12-19 2013-10-09 ルネサスエレクトロニクス株式会社 半導体装置
US20100159699A1 (en) 2008-12-19 2010-06-24 Yoshimi Takahashi Sandblast etching for through semiconductor vias
TWI366890B (en) 2008-12-31 2012-06-21 Ind Tech Res Inst Method of manufacturing through-silicon-via and through-silicon-via structure
KR20100087566A (ko) 2009-01-28 2010-08-05 삼성전자주식회사 반도체 소자 패키지의 형성방법
US8158515B2 (en) 2009-02-03 2012-04-17 International Business Machines Corporation Method of making 3D integrated circuits
US7998860B2 (en) 2009-03-12 2011-08-16 Micron Technology, Inc. Method for fabricating semiconductor components using maskless back side alignment to conductive vias
WO2010104610A2 (en) * 2009-03-13 2010-09-16 Tessera Technologies Hungary Kft. Stacked microelectronic assemblies having vias extending through bond pads
TWI466258B (zh) 2009-04-10 2014-12-21 Nanya Technology Corp 電性通透連接及其形成方法
US8263434B2 (en) 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
JP5715334B2 (ja) 2009-10-15 2015-05-07 ルネサスエレクトロニクス株式会社 半導体装置
US8519538B2 (en) 2010-04-28 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Laser etch via formation
US8796135B2 (en) * 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8697569B2 (en) 2010-07-23 2014-04-15 Tessera, Inc. Non-lithographic formation of three-dimensional conductive elements
US8598695B2 (en) 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8686565B2 (en) 2010-09-16 2014-04-01 Tessera, Inc. Stacked chip assembly having vertical vias
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip

Cited By (115)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9570416B2 (en) 2004-11-03 2017-02-14 Tessera, Inc. Stacked packaging improvements
US9153562B2 (en) 2004-11-03 2015-10-06 Tessera, Inc. Stacked packaging improvements
US9984901B2 (en) 2005-12-23 2018-05-29 Tessera, Inc. Method for making a microelectronic assembly having conductive elements
US9218988B2 (en) 2005-12-23 2015-12-22 Tessera, Inc. Microelectronic packages and methods therefor
US9548254B2 (en) 2006-11-22 2017-01-17 Tessera, Inc. Packaged semiconductor chips with array
US8704347B2 (en) 2006-11-22 2014-04-22 Tessera, Inc. Packaged semiconductor chips
US8735287B2 (en) 2007-07-31 2014-05-27 Invensas Corp. Semiconductor packaging process using through silicon vias
TWI619218B (zh) * 2010-05-11 2018-03-21 精材科技股份有限公司 晶片封裝體及其形成方法
US9123664B2 (en) 2010-07-19 2015-09-01 Tessera, Inc. Stackable molded microelectronic packages
US9553076B2 (en) 2010-07-19 2017-01-24 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US10128216B2 (en) 2010-07-19 2018-11-13 Tessera, Inc. Stackable molded microelectronic packages
US9570382B2 (en) 2010-07-19 2017-02-14 Tessera, Inc. Stackable molded microelectronic packages
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
CN102347283A (zh) * 2010-07-23 2012-02-08 泰塞拉公司 具有覆盖过孔的金属垫的微电子元件
CN102347271A (zh) * 2010-07-23 2012-02-08 泰塞拉公司 利用微研磨颗粒流形成半导体元件的方法
CN102347271B (zh) * 2010-07-23 2014-05-07 泰塞拉公司 利用微研磨颗粒流形成半导体元件的方法
CN102347283B (zh) * 2010-07-23 2015-06-03 泰塞拉公司 具有覆盖过孔的金属垫的微电子元件
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US10354942B2 (en) 2010-09-17 2019-07-16 Tessera, Inc. Staged via formation from both sides of chip
US8809190B2 (en) 2010-09-17 2014-08-19 Tessera, Inc. Multi-function and shielded 3D interconnects
US9355948B2 (en) 2010-09-17 2016-05-31 Tessera, Inc. Multi-function and shielded 3D interconnects
US9847277B2 (en) 2010-09-17 2017-12-19 Tessera, Inc. Staged via formation from both sides of chip
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US9362203B2 (en) 2010-09-17 2016-06-07 Tessera, Inc. Staged via formation from both sides of chip
US8957527B2 (en) 2010-11-15 2015-02-17 Tessera, Inc. Microelectronic package with terminals on dielectric mass
CN102884623A (zh) * 2010-11-15 2013-01-16 泰塞拉公司 在介电体上具有端子的微电子封装
US9099296B2 (en) 2010-12-02 2015-08-04 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages with plural active chips
US9269692B2 (en) 2010-12-02 2016-02-23 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US9620437B2 (en) 2010-12-02 2017-04-11 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US9368476B2 (en) 2010-12-02 2016-06-14 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8796828B2 (en) 2010-12-08 2014-08-05 Tessera, Inc. Compliant interconnects in wafers
US9324681B2 (en) 2010-12-13 2016-04-26 Tessera, Inc. Pin attachment
US10593643B2 (en) 2011-05-03 2020-03-17 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9224717B2 (en) 2011-05-03 2015-12-29 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9691731B2 (en) 2011-05-03 2017-06-27 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US10062661B2 (en) 2011-05-03 2018-08-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US11424211B2 (en) 2011-05-03 2022-08-23 Tessera Llc Package-on-package assembly with wire bonds to encapsulation surface
CN103946972A (zh) * 2011-10-03 2014-07-23 马维尔国际贸易有限公司 去除传导材料以在衬底中形成传导特征
CN103946972B (zh) * 2011-10-03 2017-08-04 马维尔国际贸易有限公司 去除传导材料以在衬底中形成传导特征
CN102339841A (zh) * 2011-10-08 2012-02-01 江阴长电先进封装有限公司 无硅通孔高可靠性图像传感器封装结构
CN102339843A (zh) * 2011-10-08 2012-02-01 江阴长电先进封装有限公司 无硅通孔低成本图像传感器封装结构
CN102339842A (zh) * 2011-10-08 2012-02-01 江阴长电先进封装有限公司 无硅通孔高可靠性图像传感器封装结构的实现方法
CN102339844A (zh) * 2011-10-08 2012-02-01 江阴长电先进封装有限公司 无硅通孔低成本图像传感器封装结构的实现方法
US9105483B2 (en) 2011-10-17 2015-08-11 Invensas Corporation Package-on-package assembly with wire bond vias
US9761558B2 (en) 2011-10-17 2017-09-12 Invensas Corporation Package-on-package assembly with wire bond vias
US9041227B2 (en) 2011-10-17 2015-05-26 Invensas Corporation Package-on-package assembly with wire bond vias
US11735563B2 (en) 2011-10-17 2023-08-22 Invensas Llc Package-on-package assembly with wire bond vias
US10756049B2 (en) 2011-10-17 2020-08-25 Invensas Corporation Package-on-package assembly with wire bond vias
US11189595B2 (en) 2011-10-17 2021-11-30 Invensas Corporation Package-on-package assembly with wire bond vias
US9252122B2 (en) 2011-10-17 2016-02-02 Invensas Corporation Package-on-package assembly with wire bond vias
CN102376734A (zh) * 2011-11-07 2012-03-14 江阴长电先进封装有限公司 铆钉互联结构的图像传感器封装结构及实现方法
CN102376733A (zh) * 2011-11-07 2012-03-14 江阴长电先进封装有限公司 铆钉互联结构的图像传感器封装结构
CN102420211A (zh) * 2011-11-14 2012-04-18 江阴长电先进封装有限公司 微凸点互联结构的图像传感器封装结构及实现方法
CN102420211B (zh) * 2011-11-14 2014-04-16 江阴长电先进封装有限公司 微凸点互联结构的图像传感器封装结构及实现方法
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9691679B2 (en) 2012-02-24 2017-06-27 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US10170412B2 (en) 2012-05-22 2019-01-01 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9953914B2 (en) 2012-05-22 2018-04-24 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US10510659B2 (en) 2012-05-22 2019-12-17 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9917073B2 (en) 2012-07-31 2018-03-13 Invensas Corporation Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US10297582B2 (en) 2012-08-03 2019-05-21 Invensas Corporation BVA interposer
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US9095074B2 (en) 2012-12-20 2015-07-28 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9615456B2 (en) 2012-12-20 2017-04-04 Invensas Corporation Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface
US9299627B2 (en) 2013-01-30 2016-03-29 Kabushiki Kaisha Toshiba Semiconductor package having a cap unit with concave portion and method of manufacturing the same
US9601454B2 (en) 2013-02-01 2017-03-21 Invensas Corporation Method of forming a component having wire bonds and a stiffening layer
US10460958B2 (en) 2013-08-07 2019-10-29 Invensas Corporation Method of manufacturing embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US10629567B2 (en) 2013-11-22 2020-04-21 Invensas Corporation Multiple plated via arrays of different wire heights on same substrate
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10290613B2 (en) 2013-11-22 2019-05-14 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
CN105980895A (zh) * 2013-12-31 2016-09-28 梅德路米克斯有限公司 用于光波导和接触导线交叉的结构
US10529636B2 (en) 2014-01-17 2020-01-07 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US11404338B2 (en) 2014-01-17 2022-08-02 Invensas Corporation Fine pitch bva using reconstituted wafer with area array accessible for testing
US9837330B2 (en) 2014-01-17 2017-12-05 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
CN103871972A (zh) * 2014-03-31 2014-06-18 华为技术有限公司 法兰、半导体功率器件和集成电路板
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US10032647B2 (en) 2014-05-29 2018-07-24 Invensas Corporation Low CTE component with wire bond interconnects
US10475726B2 (en) 2014-05-29 2019-11-12 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9947641B2 (en) 2014-05-30 2018-04-17 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US10806036B2 (en) 2015-03-05 2020-10-13 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US10559537B2 (en) 2015-10-12 2020-02-11 Invensas Corporation Wire bond wires for interference shielding
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US11462483B2 (en) 2015-10-12 2022-10-04 Invensas Llc Wire bond wires for interference shielding
US10115678B2 (en) 2015-10-12 2018-10-30 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10325877B2 (en) 2015-12-30 2019-06-18 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
CN109216387A (zh) * 2017-07-05 2019-01-15 豪威科技股份有限公司 抗脱层半导体装置以及相关联的方法
CN109216387B (zh) * 2017-07-05 2022-05-06 豪威科技股份有限公司 抗脱层半导体装置以及相关联的方法
CN109216384A (zh) * 2017-07-07 2019-01-15 日月光半导体制造股份有限公司 半导体封装装置及制造所述半导体封装装置的方法
CN109216384B (zh) * 2017-07-07 2020-10-20 日月光半导体制造股份有限公司 半导体封装装置及制造所述半导体封装装置的方法
CN108417540A (zh) * 2018-03-26 2018-08-17 李春林 一种指纹识别芯片装置

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