JP4290158B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4290158B2 JP4290158B2 JP2005354656A JP2005354656A JP4290158B2 JP 4290158 B2 JP4290158 B2 JP 4290158B2 JP 2005354656 A JP2005354656 A JP 2005354656A JP 2005354656 A JP2005354656 A JP 2005354656A JP 4290158 B2 JP4290158 B2 JP 4290158B2
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Description
<<<半導体装置単体>>>
前述した半導体装置1(図2A)のソルダーレジスト20の表側において、回路素子16であるスパイラルインダクタ(平面状コイル)と相反する面上に、以下述べるダミーパターン(導電パターン)220が設けられていてもよい。
図7(a)の断面模式図に例示されるように、前述した半導体装置1’は、例えばはんだバンプ180を介して例えば携帯機器の回路基板300に実装可能である。同図の例示では、半導体装置1’の表面パターン170と、回路基板300上に形成された導電路(電極)310とが、はんだバンプ180を介して電気的に接続されている。一方、同図の例示では、回路基板300上には、半導体装置1’とともに、半導体部品230が実装されており、半導体装置1’は、そのダミーパターン220が半導体部品230と対向するような位置に実装されている。尚、同図の例示では、半導体部品230は、導電路310及びはんだバンプ180を介して半導体装置1’に対し電気的に接続されているが、これに限定されるものではなく、半導体部品230は半導体装置1’から電気的に独立した素子であってもよい。また、この半導体部品230は、前述したMOS構造の能動素子や集積回路等であってもよいし、前述した抵抗やインダクタ、コンデンサ等の受動素子であってもよい。
前述した半導体装置1(図2A)の裏側において、回路素子16であるスパイラルインダクタ(平面状コイル)と対向するように、以下述べるダミーパターン(導電パターン)420が設けられていてもよい。
前述した半導体装置1(図2A)を回路基板300に実装する際に、回路素子16であるスパイラルインダクタ(平面状コイル)が、回路基板(実装基板)300上のダミーパターン(導電パターン)500と対向するように実装されてもよい。
前述した構成を備える半導体装置1001、1002の製造方法について説明する。尚、以下の説明では、半導体基板401としてシリコン基板を用いるものとする。また、ベースとなるウェハとして、表面及び裏面に熱酸化法やプラズマCVD(Plasma Chemical Vapor Deposition)、スパッタリング法等により5μm厚のシリコン酸化膜(SiO2)による絶縁層155”,156”が施された、130μm厚のシリコンウェハを用いるものとする。また、半導体基板401の表面には、熱酸化法やCVD(Chemical Vapor Deposition)、スパッタ、リソグラフィ、不純物拡散等の前工程により、MOS(Metal Oxide Semiconductor)構造又はBIP(Bipolar)構造の能動素子や集積回路等の電子デバイスが形成されているものとする。
図10において、半導体基板401に貫通電極(例えば、貫通電極406a、406b)を形成するプロセスを示している。前述したように、半導体基板401の裏面(拡散により形成された表面と反対の面)には、シリコン酸化膜(SiO2)や絶縁性の樹脂膜等の絶縁層155”が形成されている。貫通電極の形成に際しては、先ずこの裏面の貫通電極が形成される部分(40μm径)以外の部分にフォトレジスト(PR)を施した後、四フッ化炭素(CF4)等のエッチングガスを用いてエッチングを行い、貫通電極が形成される部分に形成されている絶縁層155”を除去する。貫通電極が形成される部分に形成されている絶縁層155”が除去された後の状態を図10(a)に示している。尚、電極MLは、金属材料からなる電極又は配線であり、例えば、Al、Cu、又は、下地から順にTi−TiN−Alを形成してなる層等からなるものである。
次に、以上のような貫通電極が形成された半導体基板401の裏面に裏面パターン(例えば、電極415)を形成する。裏面パターンを形成する際のプロセスフローは、図4に例示されるものと略同様であるため、同図に基づいて説明する。
次に、半導体基板401の表面に表面パターン(例えば、電極404、405)を形成する。表面パターンを形成する際のプロセスフローは、図5に例示されるものと略同様であるため、同図に基づいて説明する。
2、 2 半導体モジュール
10、100 半導体基板
11 表面
12 裏面
13、130 貫通電極
14、140 電子デバイス
15、150 裏面パターン
16、160 回路素子
17、170 表面パターン
18、180 はんだバンプ
19 ワイヤーボンディング
20 ソルダーレジスト
21 緩衝層
200、413 ソルダーレジスト
220、420 ダミーパターン
230 半導体部品
300 回路基板
310 導電路
400 コイル
401 半導体基板
403、408 絶縁層
404 エミッタ電極
405 ベース電極
406a、406b 貫通電極
407a、407b コンタクト電極
409 シリコン酸化膜
410 絶縁性樹脂
412 はんだバンプ
415 電極
500 ダミーパターン
Claims (2)
- 表面に電子デバイスが形成されるとともに、表面に第1の絶縁層を介して前記電子デバイスと電気的に接続される電極及び当該電極から延在する再配線が設けられる、シリコンを材料とする半導体基板と、
前記半導体基板を貫通する貫通孔に対し絶縁層を介さずに形成されて、前記再配線を介して前記電子デバイスと電気的に接続される、銅を材料とする貫通電極と、
前記半導体基板の表面側に設けられて、前記再配線を介して前記貫通電極と電気的に接続されるはんだバンプと、
前記半導体基板の裏面に、第2の絶縁層を介して、銅を材料として前記貫通電極とともに形成されて、前記電子デバイスと電気的に接続されるインダクタと、
を有し、
前記第2の絶縁層と前記インダクタとの間に樹脂材料を素材とする緩衝層が形成されてなる、
ことを特徴とする半導体装置。 - 請求項1に記載の半導体装置であって、
前記インダクタは、前記半導体基板の裏面側に形成される配線パターン自体によって構成されることを特徴とする半導体装置。
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JP2005354656A JP4290158B2 (ja) | 2004-12-20 | 2005-12-08 | 半導体装置 |
US11/275,190 US20070035020A1 (en) | 2004-12-20 | 2005-12-16 | Semiconductor Apparatus and Semiconductor Module |
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JP2004367523 | 2004-12-20 | ||
JP2005354656A JP4290158B2 (ja) | 2004-12-20 | 2005-12-08 | 半導体装置 |
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JP2007306999A Division JP2008085362A (ja) | 2004-12-20 | 2007-11-28 | 半導体装置及び半導体モジュール |
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JP2006203176A JP2006203176A (ja) | 2006-08-03 |
JP4290158B2 true JP4290158B2 (ja) | 2009-07-01 |
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JP2005354656A Expired - Fee Related JP4290158B2 (ja) | 2004-12-20 | 2005-12-08 | 半導体装置 |
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JP (1) | JP4290158B2 (ja) |
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JP5103032B2 (ja) * | 2007-03-01 | 2012-12-19 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5584474B2 (ja) | 2007-03-05 | 2014-09-03 | インヴェンサス・コーポレイション | 貫通ビアによって前面接点に接続された後面接点を有するチップ |
JP2010535427A (ja) | 2007-07-31 | 2010-11-18 | テッセラ,インコーポレイテッド | 貫通シリコンビアを使用する半導体実装プロセス |
JP5592053B2 (ja) * | 2007-12-27 | 2014-09-17 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
JPWO2010052839A1 (ja) | 2008-11-06 | 2012-03-29 | パナソニック株式会社 | 半導体装置 |
US8791575B2 (en) | 2010-07-23 | 2014-07-29 | Tessera, Inc. | Microelectronic elements having metallic pads overlying vias |
US8796135B2 (en) | 2010-07-23 | 2014-08-05 | Tessera, Inc. | Microelectronic elements with rear contacts connected with via first or via middle structures |
US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
US8610259B2 (en) | 2010-09-17 | 2013-12-17 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
US8637968B2 (en) | 2010-12-02 | 2014-01-28 | Tessera, Inc. | Stacked microelectronic assembly having interposer connecting active chips |
US8587126B2 (en) * | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
US8736066B2 (en) * | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
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US8610264B2 (en) | 2010-12-08 | 2013-12-17 | Tessera, Inc. | Compliant interconnects in wafers |
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CN111512425A (zh) | 2018-06-27 | 2020-08-07 | 应用材料公司 | 化学机械抛光的温度控制 |
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2005
- 2005-12-08 JP JP2005354656A patent/JP4290158B2/ja not_active Expired - Fee Related
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