US20140167900A1 - Surface-mount inductor structures for forming one or more inductors with substrate traces - Google Patents

Surface-mount inductor structures for forming one or more inductors with substrate traces Download PDF

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Publication number
US20140167900A1
US20140167900A1 US13/715,016 US201213715016A US2014167900A1 US 20140167900 A1 US20140167900 A1 US 20140167900A1 US 201213715016 A US201213715016 A US 201213715016A US 2014167900 A1 US2014167900 A1 US 2014167900A1
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Prior art keywords
strips
inductor
substrate
die
conductive material
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Abandoned
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US13/715,016
Inventor
Gregorio R. Murtagian
Robert L. Sankman
Brent S. Stone
Kaladhar Radhakrishnan
Joshua D. Heppner
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Intel Corp
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Intel Corp
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Priority to US13/715,016 priority Critical patent/US20140167900A1/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SANKMAN, ROBERT L., HEPPNER, JOSHUA D., MURTAGIAN, GREGORIO R., RADHAKRISHNAN, KALADHAR, STONE, BRENT S.
Publication of US20140167900A1 publication Critical patent/US20140167900A1/en
Priority to US14/616,508 priority patent/US10056182B2/en
Abandoned legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00Details of transformers or inductances, in general
    • H01F27/28Coils; Windings; Conductive connections
    • H01F27/2847Sheets; Strips
    • H01F27/2852Construction of conductive connections, of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00Details of transformers or inductances, in general
    • H01F27/28Coils; Windings; Conductive connections
    • H01F27/29Terminals; Tapping arrangements for signal inductances
    • H01F27/292Surface mounted devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • H01F17/04Fixed inductances of the signal type  with magnetic core
    • H01F17/045Fixed inductances of the signal type  with magnetic core with core of cylindric geometry and coil wound along its longitudinal axis, i.e. rod or drum core
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00Details of transformers or inductances, in general
    • H01F27/02Casings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00Details of transformers or inductances, in general
    • H01F27/02Casings
    • H01F27/027Casings specially adapted for combination of signal type inductors or transformers with electronic circuits, e.g. mounting on printed circuit boards
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00Details of transformers or inductances, in general
    • H01F27/06Mounting, supporting or suspending transformers, reactors or choke coils not being of the signal type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00Details of transformers or inductances, in general
    • H01F27/28Coils; Windings; Conductive connections
    • H01F27/2847Sheets; Strips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00Details of transformers or inductances, in general
    • H01F27/06Mounting, supporting or suspending transformers, reactors or choke coils not being of the signal type
    • H01F2027/065Mounting on printed circuit boards
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00Details of transformers or inductances, in general
    • H01F27/28Coils; Windings; Conductive connections
    • H01F27/29Terminals; Tapping arrangements for signal inductances
    • H01F2027/297Terminals; Tapping arrangements for signal inductances with pin-like terminal to be inserted in hole of printed path
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/4902Electromagnet, transformer or inductor

Definitions

  • Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to inductor structures configured for forming one or more inductors with substrate traces, and associated techniques and configurations.
  • inductors are needed to regulate electrical power, among other uses.
  • the inductors are integrated into the IC package to provide voltage regulation.
  • multi-layer inductors are integrated into a circuit board by drilling holes in the circuit board followed by metal fill of the holes to create vias between the layers.
  • these inductors require a complex manufacturing process and a relatively large substrate thickness.
  • FIG. 1A illustrates a perspective view of an inductor structure, in accordance with some embodiments.
  • FIG. 1B illustrates a perspective view of the inductor structure of FIG. 1A without the housing in accordance with some embodiments.
  • FIG. 1C illustrates strips of conductive material of the inductor structure of FIG. 1A in accordance with some embodiments.
  • FIG. 2A illustrates a perspective view of sheet of conductive material used to form an inductor structure, in accordance with some embodiments.
  • FIG. 2B illustrates a perspective view of the sheet of FIG. 2A with slots formed in the sheet to form strips of conductive material, in accordance with some embodiments.
  • FIG. 2C illustrates a perspective view of the sheet of FIG. 2B with a core and a housing formed around the strips of conductive material, in accordance with some embodiments.
  • FIG. 2D illustrates a perspective view of the structure of FIG. 2C with connecting portions of the sheet removed, in accordance with some embodiments.
  • FIG. 2E illustrates a perspective view of the structure of FIG. 2D with the strips folded into a “U” shape, in accordance with some embodiments.
  • FIG. 3A illustrates a perspective view of an inductor structure, in accordance with some embodiments.
  • FIG. 3B illustrates a perspective view of the inductor structure of FIG. 3A without the housing, in accordance with some embodiments.
  • FIG. 3C illustrates strips of conductive material of the inductor structure of FIG. 3A , in accordance with some embodiments.
  • FIG. 4 illustrates a perspective view of an inductor structure, in accordance with some embodiments.
  • FIG. 5 illustrates a perspective view of an inductor structure, in accordance with some embodiments.
  • FIG. 6A illustrates a perspective front view of a modular inductor structure, in accordance with some embodiments.
  • FIG. 6B illustrates a perspective rear view of the modular inductor structure of FIG. 6A without a strip of conductive material, in accordance with some embodiments.
  • FIG. 6C illustrates a perspective view of a pair of the modular inductor structures of FIG. 6A coupled to one another, in accordance with some embodiments.
  • FIG. 7 illustrates a perspective view of a substrate having a plurality of inductor structures mounted to a surface of the substrate, in accordance with some embodiments.
  • FIG. 8 schematically illustrates a cross-section side view of a integrated circuit (IC) package assembly having an inductor structure mounted on a land side of a substrate of the IC package assembly, in accordance with some embodiments.
  • IC integrated circuit
  • FIG. 9 schematically illustrates a flow diagram for a method of fabricating an inductor structure and mounting the inductor structure on a substrate, in accordance with some embodiments.
  • FIG. 10 schematically illustrates a computing device in accordance with one implementation of various embodiments disclosed herein.
  • Embodiments of the present disclosure describe surface-mount inductor structures for forming one or more inductors with substrate traces, and associated techniques and configurations.
  • various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
  • phrase “A and/or B” means (A), (B), or (A and B).
  • phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
  • Coupled may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other.
  • directly coupled may mean that two or more elements are in direct contact.
  • the phrase “a first feature formed, deposited, or otherwise disposed on a second feature,” may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.
  • direct contact e.g., direct physical and/or electrical contact
  • indirect contact e.g., having one or more other features between the first feature and the second feature
  • FIG. 1A illustrates an inductor structure 100 in accordance with various embodiments.
  • Inductor structure 100 includes a core 102 and a plurality of strips 104 a - f of conductive material.
  • the inductor structure 100 may further include a housing 106 .
  • FIG. 1B illustrates the inductor structure 100 without the housing 106
  • FIG. 1C illustrates the strips 104 a - f without the core 102 or the housing 106 , to more fully illustrate the components of inductor structure 100 .
  • the strips 104 a - f include respective contacts 108 a - l at ends of the strips 104 a - f as best seen in FIG. 2C .
  • the contacts 108 a - l may be surface-mount technology (SMT) contacts to facilitate mounting the inductive structure 100 on a surface of a substrate.
  • the strips 104 a - f may be disposed around the core 102 with a gap 110 between the contacts 108 a - l of respective individual strips 104 a - f across a lower surface of the core 102 .
  • the housing 106 may cover a portion of the strips 104 a - f and leave the contacts 108 a - l exposed.
  • the inductor structure 100 may be formed of any suitable materials.
  • the core may include an insulating material, such as plastic (e.g., molded plastic).
  • the core may include a magnetic material, such as iron and/or ferrite.
  • the core 102 may include a magnetic material surrounded by a non-magnetic material (e.g., plastic), a non-magnetic material with portions of a magnetic material spread throughout the non-magnetic material, and/or the core 102 may be composed entirely of a magnetic material.
  • the magnetic material may improve the magnetic flux and/or efficiency of inductors formed by the inductor structure 100 .
  • the strips 104 a - f may include any suitable conductive material or materials, such as copper.
  • the strips 104 a - f may be plated, such as with nickel, tin, palladium, silver and/or gold, to prevent corrosion and/or facilitate soldering.
  • the inductor structure 100 may further include a housing 106 .
  • the housing 106 may be a separate piece or may be integrated with the core 102 .
  • the housing 106 and core 102 may be formed as a single piece by plastic over-molding.
  • Other embodiments of the inductor structure 100 may not include a housing 106 .
  • the inductor structure 100 may be mounted to a substrate (e.g., substrate 702 shown in FIG. 7 and/or substrate 802 shown in FIG. 8 , both of which are discussed further below).
  • a substrate e.g., substrate 702 shown in FIG. 7 and/or substrate 802 shown in FIG. 8 , both of which are discussed further below.
  • One or more traces may be formed in a surface of the substrate to electrically couple (e.g. conductively) two or more of the strips 104 a - f to one another to form inductive coils.
  • the one or more traces may be formed across the gap 110 to electrically couple adjacent strips to one another to form an inductive coil.
  • contact 108 b of strip 104 a may be coupled by a trace to contact 108 c of strip 104 b .
  • one or more inductors may be formed from the inductor structure 104 .
  • the contacts that are not coupled to an adjacent strip e.g., contacts 108 a and 108 d in the above example
  • any set of two or more of the strips 104 a - f may be coupled to one another by one or more traces to form an inductor.
  • the inductor structure 100 may be used to form any suitable number and/or arrangement of inductors.
  • the inductor structure 100 may be used to form one inductor that includes up to six strips, two inductors that each include three strips, or one inductor including two strips and one inductor including four strips. It will be apparent that many other arrangements of one or more inductors are possible using inductor structure 100 .
  • a transformer including a first inductor and a second inductor, may be formed from the inductor structure 100 .
  • the one or more inductors formed by the inductor structure 100 may be included in a voltage regulator to convert a supply voltage (e.g., from a power supply) to an input voltage for a circuit (e.g., on a die).
  • a supply voltage e.g., from a power supply
  • a circuit e.g., on a die
  • the spacing between the strips 104 a - f may not be the same between each adjacent strip.
  • the strips 104 a - f may be arranged into groups of strips that are spaced together. The grouping and/or spacing may facilitate an intended electrical connection among the strips 104 a - f , and/or facilitate a desired inductance.
  • the strips 104 a - f are arranged in three pairs (e.g., with strips 104 a and 104 b spaced more closely together than strips 104 b and 104 c ).
  • Other embodiments may include other spacing arrangements of the strips 104 a - f .
  • the strips 104 a - f may be spaced evenly from one another.
  • the inductor structure 100 may be manufactured in any suitable manner.
  • the inductor structure 100 may be manufactured at a relatively low cost, with low manufacturing complexity.
  • the strips may be formed from conductive wire (e.g., copper wire).
  • the core may be molded, e.g. from plastic. The strips may be bent and/or wrapped around the core to form the inductor structure 100 .
  • the strips may be formed from a sheet of conductive material.
  • FIG. 2A illustrates a sheet 202 of conductive material.
  • An array of slots 204 may be formed in the sheet 202 as shown in FIG. 2B , thereby forming strips 206 .
  • the slots 204 may be formed, for example, by metal stamping.
  • a core 210 and housing 212 may be formed around the strips 206 , as shown in FIG. 2C .
  • connecting portions 208 of the sheet 202 may be removed to separate the strips 206 .
  • the strips 206 may be bent into a desired shape, such as a “U” shape as shown in FIG. 2E , thereby forming an inductor structure 200 with contacts 214 .
  • the operations illustrated in FIG. 2A-E may be performed in any suitable order.
  • the sheet 202 may be bent into a desired shape prior to forming the core 210 and/or housing 212 around the strips 206 and/or prior to removing the connecting portions 208 .
  • the core 210 and/or housing 212 may be formed around the strips 206 by over-molding.
  • the core 102 of inductor structure 100 is shown with a cross-sectional shape that resembles a rectangle, it will be apparent that the core 102 may have any suitable cross-sectional shape, such as circular, elliptical, or polygonal.
  • FIGS. 3A , 3 B, and 3 C illustrate an inductor structure 300 having two strips 304 disposed around a core 302 in accordance with various embodiments.
  • the strips 304 include respective contacts 308 .
  • the inductor structure 300 further includes a housing 306 that partially covers the strips 304 and leaves the contacts 308 exposed.
  • FIG. 4 illustrates an inductor structure 400 with SMT contacts 408 having an alternative arrangement from that of contacts 108 a - l .
  • Inductor structure 400 is shown upside-down with contacts 408 pointed upward.
  • the inductor structure 400 includes a core 402 with an upper surface 412 and a lower surface 414 .
  • Inductor structure 400 further includes strips 404 that extend across the upper surface 412 of the core 402 and partially across the lower surface 414 , leaving a gap 410 between the contacts 408 .
  • the core 402 includes ridges 405 to facilitate spacing and/or alignment of the strips 404 .
  • the ends of the strips 402 are bent from a plane of the lower surface 414 , thereby providing contacts 408 that extend from the lower surface 414 .
  • the gap 410 between the contacts 408 of individual strips 404 in inductor structure 400 may be less than the gap 110 between the contacts 108 a - l of inductor structure 104 for a core of similar size. This may allow shorter traces to be used to electrically couple the contacts 408 to one another to form one or more inductors.
  • FIG. 5 illustrates another inductor structure 500 that includes flush-mount SMT contacts 508 in accordance with various embodiments.
  • the inductor structure 500 includes a core 502 with an upper surface 512 and a lower surface 514 .
  • Inductor structure 500 further includes strips 504 that extend around the upper surface 512 of the and partially across the lower surface 514 , leaving a gap 510 between the contacts 508 .
  • the contacts 508 are disposed flat against the lower surface 514 , thereby allowing for the inductor structure 500 to be flush-mounted onto the substrate.
  • FIG. 6A illustrates a modular inductor structure 600 in accordance with various embodiments.
  • Inductor structure 600 that may be coupled with one or more other inductor structures 600 to form an array of inductor structures 600 .
  • Inductor structure 600 includes a strip 604 (not shown in FIG. 6B ) disposed around a core 602 . Another view of core 602 is shown in FIG. 6B , without the strip 604 .
  • Core 602 further includes a first mating feature 616 and a second mating feature 618 .
  • the first mating feature 616 may be mated with the second mating feature 618 of another inductor structure 600 to couple the inductor structures 600 together. Accordingly, the inductor structure 600 may be used to form an array of strips 604 having any desired quantity of strips 604 .
  • FIG. 6C shows two inductor structures 600 coupled to one another.
  • Other embodiments may include any number of one or more inductor structures 600 coupled to one another.
  • the individual inductor structures 600 may include any suitable number of one or more strips 604 .
  • FIG. 7 illustrates an integrated circuit (IC) assembly 700 in accordance with various embodiments.
  • IC assembly 700 includes a substrate 702 with a plurality of inductor structures 100 and a plurality of inductor structures 200 mounted on a surface 704 of the substrate 702 . Traces (not shown) may be formed in the surface 704 of the substrate 702 to form inductors from the inductor structures 100 and/or 200 .
  • the substrate 702 is an epoxy-based laminate substrate having a core and/or build-up layers such as, for example, an Ajinomoto Build-up Film (ABF) substrate.
  • the substrate 702 may include other suitable types of substrates in other embodiments including, for example, substrates formed from glass, ceramic, or semiconductor materials.
  • IC assembly 700 is shown in FIG. 7 to include a plurality of inductor structures 100 and a plurality of inductor structures 200 , other embodiments may include any suitable number of one or more inductor structures 100 and/or 200 .
  • one or more inductor structures as described herein may be mounted on a same substrate on which a die is mounted.
  • the inductor structures may be used to route electrical power from a power source to the die.
  • the inductor structures may be included in a voltage regulator to regulate the power delivered to the die.
  • the inductor structure may be mounted on a land side of the substrate, opposite the die.
  • FIG. 8 schematically illustrates a cross-section side view of an example integrated circuit (IC) package assembly 800 , in accordance with some embodiments.
  • the IC package assembly 800 may also be referred to as a die package assembly.
  • the IC package assembly 800 includes a substrate 802 having a first side, S 1 , and a second side, S 2 , opposite the first side.
  • the first side S 1 may also be referred to as the die side of the substrate 802
  • the second side S 2 may also be referred to as the land side of the substrate 802 .
  • One or more dies (hereinafter “die 804 ) may be mounted on the first side S 1 .
  • one or more inductor structures 806 may be coupled to the second side S 2 of the substrate. Suitable inductor structures 806 may include inductor structures 100 , 200 , 300 , 400 , 500 , and/or 600 discussed herein.
  • the inductor structure 806 may include one or more strips of conductive material having contacts at a first end and a second end of each strip.
  • the strips may be disposed around a core of the inductor structure 806 , with a gap between the first end and second end of the individual strips.
  • the strips may be disposed adjacent to one another in an array.
  • the IC package assembly 800 may further include traces 808 on a surface of the second side to electrically couple two or more of the strips of conductive material to one another to form inductive coils. Accordingly, the inductor structure 806 may be used to form one or more inductors in combination with the traces 808 .
  • the inductor structures 806 may be included in a voltage regulator to route electrical power from a power source (not shown) to the die 804 .
  • the voltage regulator may convert a supply voltage provided by the power supply to an input voltage used by the die 804 . In some embodiments, the supply voltage may be higher than the input voltage.
  • the voltage regulator may include one or more other components besides inductor structure 806 , such as one or more capacitors and/or switches. In some embodiments, the voltage regulator may be a single or multiple phase voltage regulator, such as a Buck voltage regulator.
  • one or more inductor structures 806 may be used to form a transformer.
  • the transformer may be used in the voltage regulator.
  • the traces 808 may form a first inductor and a second inductor from one or more of the inductor structures 806 .
  • the first inductor may be electrically coupled to the power source and the second inductor may be electrically coupled to the die 804 to transform the supply voltage provided by the power supply to the input voltage used by the die 804 .
  • the inductor structures 806 may be coupled to the second side S 2 within a shadow of the die 804 (shown at 805 ). In some embodiments, the inductor structures 806 may be mounted to a land-side cavity on the second side S 2 of the substrate 802 . One or more other devices, such as one or more capacitors, may also be mounted on the second side S 2 of the substrate 802 .
  • the die 804 may be attached to the substrate 802 according to a variety of suitable configurations, including a flip-chip configuration, as depicted, or other configurations such as wirebonding and the like.
  • a flip-chip configuration an active side of the die 804 is attached to the first side S 1 of the substrate 802 using die interconnect structures 810 such as bumps, pillars, or other suitable structures.
  • the active side of the die 804 may have one or more transistor devices formed thereon.
  • the die 804 may represent a discrete chip and may be, include, or be a part of a processor, memory, or application-specific integrated circuit (ASIC) in some embodiments.
  • an encapsulant 812 such as, for example, molding compound or underfill material may fully or partially encapsulate the die 804 .
  • the die interconnect structures 810 may be configured to route electrical signals between the die 804 and the substrate 802 .
  • the electrical signals may include, for example, input/output (I/O) signals and/or power or ground signals associated with the operation of the die 804 .
  • the substrate 802 may include structures configured to route electrical signals to or from the die 804 and/or inductor structures 806 .
  • the structures may include, for example, traces (e.g., traces 808 ) disposed on one or more surfaces of the substrate 802 and/or internal structures such as, for example, trenches, vias or other interconnect structures (not shown) to route electrical signals through the substrate 802 .
  • the substrate 802 may include structures such as die bond pads (not shown) configured to receive the die interconnect structures 810 and route electrical signals between the die 804 and the substrate 802 .
  • the substrate 802 is an epoxy-based laminate substrate having a core and/or build-up layers such as, for example, an Ajinomoto Build-up Film (ABF) substrate.
  • the substrate 802 may include other suitable types of substrates in other embodiments including, for example, substrates formed from glass, ceramic, or semiconductor materials.
  • FIG. 9 schematically illustrates a flow diagram for a method 900 of fabricating an inductor structure and/or forming one or more inductors from an inductor structure coupled to a substrate, in accordance with some embodiments.
  • the method 900 may comport with embodiments described in connection with FIGS. 1-8 .
  • the method 900 includes providing a substrate (e.g., substrate 802 of FIG. 8 ) having a first surface (e.g., S 1 of FIG. 8 ) and a second surface (e.g., S 2 of FIG. 8 ) opposite to the first surface.
  • the first surface may be configured to have a die mounted thereon in some embodiments.
  • the method 900 may further include forming the substrate.
  • the substrate may be formed using techniques such as, for example, lamination of electrically insulative materials, deposition of electrically conductive materials, patterning of the electrically conductive materials by additive or subtractive processes, creating holes or vias by mechanical means, laser drilling or etch processes, the like, and other techniques.
  • the method 900 further includes forming an inductor structure (e.g., inductor structure 100 , 200 , 300 , 400 , 500 , 600 , and/or 806 described herein).
  • the inductor structure may include a core and a plurality of strips of conductive material having contacts at a first end and a second end. The strips may be disposed around the core with a gap between the first end and the second end.
  • forming the inductor structure at 904 may include forming the strips from a sheet of conductive material and/or over-molding the core around the strips (e.g., as shown in FIGS. 2A-2E and described above). Other embodiments may include forming the strips from conductive wire and bending and/or wrapping the strips around the core.
  • the method 900 further includes forming one or more traces (e.g., traces 808 ) on the second surface of the substrate to electrically couple two or more strips of the conductive material to one another to form one or more inductors.
  • the traces may be formed by any suitable method, such as etching to form a stencil on the second surface.
  • the method 900 further includes mounting the inductor structure on the second surface of the substrate.
  • the inductor structure may be mounted on the second surface with respective contacts of the inductor structure coupled to the one or more traces to form the one or more inductors.
  • the inductor structure may be mounted with the contacts disposed in or on holes in the stencil that are electrically connected by the traces.
  • the contacts may be coupled to the second surface, for example, by soldering.
  • FIG. 10 schematically illustrates a computing device 1000 in accordance with one implementation of the invention.
  • the computing device 1000 may house a board such as motherboard 1002 .
  • the motherboard 1002 may be a substrate (e.g., substrate 702 of FIG. 7 and/or substrate 802 of FIG. 8 ) having one or more inductor structures (e.g., inductor structures 100 , 200 , 300 , 400 , 500 , 600 , and/or 806 ) mounted to a surface of the substrate as described herein.
  • the motherboard 1002 may include a number of components, including but not limited to a processor 1004 and at least one communication chip 1006 .
  • the processor 1004 may be physically and electrically coupled to the motherboard 1002 .
  • the at least one communication chip 1006 may also be physically and electrically coupled to the motherboard 1002 .
  • the communication chip 1006 may be part of the processor 1004 .
  • the processor 1004 , the communication chip 1006 or other components (e.g., memory devices) described in connection with the computing device 1000 may be in the form of one or more dies (e.g., die 804 of FIG. 8 ) as described herein.
  • the one or more inductor structures may be disposed on the motherboard 1002 and/or on a die package substrate.
  • the one or more inductors may be disposed on the land-side of the die package substrate, within a die shadow region (e.g., indicated by arrow 805 of FIG. 8 ).
  • computing device 1000 may include other components that may or may not be physically and electrically coupled to the motherboard 1002 .
  • these other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor,
  • the communication chip 1006 may enable wireless communications for the transfer of data to and from the computing device 1000 .
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 1006 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.).
  • IEEE 802.16 compatible BWA networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards.
  • the communication chip 1006 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.
  • GSM Global System for Mobile Communication
  • GPRS General Packet Radio Service
  • UMTS Universal Mobile Telecommunications System
  • High Speed Packet Access HSPA
  • E-HSPA Evolved HSPA
  • LTE LTE network.
  • the communication chip 1006 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN).
  • EDGE Enhanced Data for GSM Evolution
  • GERAN GSM EDGE Radio Access Network
  • UTRAN Universal Terrestrial Radio Access Network
  • E-UTRAN Evolved UTRAN
  • the communication chip 1006 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • CDMA Code Division Multiple Access
  • TDMA Time Division Multiple Access
  • DECT Digital Enhanced Cordless Telecommunications
  • EV-DO Evolution-Data Optimized
  • derivatives thereof as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the communication chip 1006 may operate in accordance with other wireless protocols in other embodiments.
  • the computing device 1000 may include a plurality of communication chips 1006 .
  • a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 1004 of the computing device 1000 may include a die (e.g., die 804 of FIG. 8 ) in an IC package assembly (e.g., IC package assembly 800 of FIG. 8 ) as described herein.
  • the term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 1006 may also include a die (e.g., die 804 of FIG. 8 ) in an IC package assembly (e.g., IC package assembly 800 of FIG. 8 ) as described herein.
  • a die e.g., die 804 of FIG. 8
  • another component e.g., memory device or other integrated circuit device housed within the computing device 1000 may contain a die (e.g., die 804 of FIG. 8 ) in an IC package assembly (e.g., IC package assembly 800 of FIG. 8 ) as described herein.
  • the computing device 1000 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 1000 may be any other electronic device that processes data.

Abstract

Embodiments of the present disclosure are directed towards an inductor structure having one or more strips of conductive material disposed around a core. The strips may have contacts at a first end and a second end of the strips, and may be disposed around the core with a gap between the contacts. The inductor structure may be mounted on a surface of a substrate, and one or more traces may be formed in the surface of the substrate to electrically couple two or more of the strips of conductive material to one another to form inductive coils. Other embodiments may be described and/or claimed.

Description

    FIELD
  • Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to inductor structures configured for forming one or more inductors with substrate traces, and associated techniques and configurations.
  • BACKGROUND
  • In many integrated circuit packages, inductors are needed to regulate electrical power, among other uses. In some IC packages, the inductors are integrated into the IC package to provide voltage regulation. For example, in some IC packages multi-layer inductors are integrated into a circuit board by drilling holes in the circuit board followed by metal fill of the holes to create vias between the layers. However, these inductors require a complex manufacturing process and a relatively large substrate thickness.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.
  • FIG. 1A illustrates a perspective view of an inductor structure, in accordance with some embodiments.
  • FIG. 1B illustrates a perspective view of the inductor structure of FIG. 1A without the housing in accordance with some embodiments.
  • FIG. 1C illustrates strips of conductive material of the inductor structure of FIG. 1A in accordance with some embodiments.
  • FIG. 2A illustrates a perspective view of sheet of conductive material used to form an inductor structure, in accordance with some embodiments.
  • FIG. 2B illustrates a perspective view of the sheet of FIG. 2A with slots formed in the sheet to form strips of conductive material, in accordance with some embodiments.
  • FIG. 2C illustrates a perspective view of the sheet of FIG. 2B with a core and a housing formed around the strips of conductive material, in accordance with some embodiments.
  • FIG. 2D illustrates a perspective view of the structure of FIG. 2C with connecting portions of the sheet removed, in accordance with some embodiments.
  • FIG. 2E illustrates a perspective view of the structure of FIG. 2D with the strips folded into a “U” shape, in accordance with some embodiments.
  • FIG. 3A illustrates a perspective view of an inductor structure, in accordance with some embodiments.
  • FIG. 3B illustrates a perspective view of the inductor structure of FIG. 3A without the housing, in accordance with some embodiments.
  • FIG. 3C illustrates strips of conductive material of the inductor structure of FIG. 3A, in accordance with some embodiments.
  • FIG. 4 illustrates a perspective view of an inductor structure, in accordance with some embodiments.
  • FIG. 5 illustrates a perspective view of an inductor structure, in accordance with some embodiments.
  • FIG. 6A illustrates a perspective front view of a modular inductor structure, in accordance with some embodiments.
  • FIG. 6B illustrates a perspective rear view of the modular inductor structure of FIG. 6A without a strip of conductive material, in accordance with some embodiments.
  • FIG. 6C illustrates a perspective view of a pair of the modular inductor structures of FIG. 6A coupled to one another, in accordance with some embodiments.
  • FIG. 7 illustrates a perspective view of a substrate having a plurality of inductor structures mounted to a surface of the substrate, in accordance with some embodiments.
  • FIG. 8 schematically illustrates a cross-section side view of a integrated circuit (IC) package assembly having an inductor structure mounted on a land side of a substrate of the IC package assembly, in accordance with some embodiments.
  • FIG. 9 schematically illustrates a flow diagram for a method of fabricating an inductor structure and mounting the inductor structure on a substrate, in accordance with some embodiments.
  • FIG. 10 schematically illustrates a computing device in accordance with one implementation of various embodiments disclosed herein.
  • DETAILED DESCRIPTION
  • Embodiments of the present disclosure describe surface-mount inductor structures for forming one or more inductors with substrate traces, and associated techniques and configurations. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
  • In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.
  • For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
  • The description may use perspective-based descriptions such as top/bottom, in/out, over/under, and the like. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.
  • The description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
  • The term “coupled with,” along with its derivatives, may be used herein. “Coupled” may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term “directly coupled” may mean that two or more elements are in direct contact.
  • In various embodiments, the phrase “a first feature formed, deposited, or otherwise disposed on a second feature,” may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.
  • FIG. 1A illustrates an inductor structure 100 in accordance with various embodiments. Inductor structure 100 includes a core 102 and a plurality of strips 104 a-f of conductive material. In some embodiments, the inductor structure 100 may further include a housing 106. FIG. 1B illustrates the inductor structure 100 without the housing 106, and FIG. 1C illustrates the strips 104 a-f without the core 102 or the housing 106, to more fully illustrate the components of inductor structure 100.
  • The strips 104 a-f include respective contacts 108 a-l at ends of the strips 104 a-f as best seen in FIG. 2C. In some embodiments, the contacts 108 a-l may be surface-mount technology (SMT) contacts to facilitate mounting the inductive structure 100 on a surface of a substrate. The strips 104 a-f may be disposed around the core 102 with a gap 110 between the contacts 108 a-l of respective individual strips 104 a-f across a lower surface of the core 102. The housing 106 may cover a portion of the strips 104 a-f and leave the contacts 108 a-l exposed.
  • The inductor structure 100 may be formed of any suitable materials. In some embodiments the core may include an insulating material, such as plastic (e.g., molded plastic). Alternatively, or additionally, the core may include a magnetic material, such as iron and/or ferrite. For example, the core 102 may include a magnetic material surrounded by a non-magnetic material (e.g., plastic), a non-magnetic material with portions of a magnetic material spread throughout the non-magnetic material, and/or the core 102 may be composed entirely of a magnetic material. The magnetic material may improve the magnetic flux and/or efficiency of inductors formed by the inductor structure 100.
  • The strips 104 a-f may include any suitable conductive material or materials, such as copper. In some embodiments, the strips 104 a-f may be plated, such as with nickel, tin, palladium, silver and/or gold, to prevent corrosion and/or facilitate soldering. In some embodiments, the inductor structure 100 may further include a housing 106. The housing 106 may be a separate piece or may be integrated with the core 102. For example, in one embodiment, the housing 106 and core 102 may be formed as a single piece by plastic over-molding. Other embodiments of the inductor structure 100 may not include a housing 106.
  • In various embodiments, the inductor structure 100 may be mounted to a substrate (e.g., substrate 702 shown in FIG. 7 and/or substrate 802 shown in FIG. 8, both of which are discussed further below). One or more traces (not shown) may be formed in a surface of the substrate to electrically couple (e.g. conductively) two or more of the strips 104 a-f to one another to form inductive coils. In some embodiments, the one or more traces may be formed across the gap 110 to electrically couple adjacent strips to one another to form an inductive coil. For example, contact 108 b of strip 104 a may be coupled by a trace to contact 108 c of strip 104 b. Accordingly, one or more inductors may be formed from the inductor structure 104. The contacts that are not coupled to an adjacent strip (e.g., contacts 108 a and 108 d in the above example) may be used as input and/or output terminals for the inductor.
  • In various embodiments, any set of two or more of the strips 104 a-f may be coupled to one another by one or more traces to form an inductor. The inductor structure 100 may be used to form any suitable number and/or arrangement of inductors. For example, the inductor structure 100 may be used to form one inductor that includes up to six strips, two inductors that each include three strips, or one inductor including two strips and one inductor including four strips. It will be apparent that many other arrangements of one or more inductors are possible using inductor structure 100. In some embodiments, a transformer, including a first inductor and a second inductor, may be formed from the inductor structure 100. In some embodiments, the one or more inductors formed by the inductor structure 100 may be included in a voltage regulator to convert a supply voltage (e.g., from a power supply) to an input voltage for a circuit (e.g., on a die).
  • In some embodiments, the spacing between the strips 104 a-f may not be the same between each adjacent strip. For example, the strips 104 a-f may be arranged into groups of strips that are spaced together. The grouping and/or spacing may facilitate an intended electrical connection among the strips 104 a-f, and/or facilitate a desired inductance. As shown in FIGS. 1A-C, the strips 104 a-f are arranged in three pairs (e.g., with strips 104 a and 104 b spaced more closely together than strips 104 b and 104 c). Other embodiments may include other spacing arrangements of the strips 104 a-f. In some embodiments, the strips 104 a-f may be spaced evenly from one another.
  • The inductor structure 100 may be manufactured in any suitable manner. The inductor structure 100 may be manufactured at a relatively low cost, with low manufacturing complexity. For example, in some embodiments, the strips may be formed from conductive wire (e.g., copper wire). The core may be molded, e.g. from plastic. The strips may be bent and/or wrapped around the core to form the inductor structure 100.
  • In embodiments, the strips may be formed from a sheet of conductive material. For example, FIG. 2A illustrates a sheet 202 of conductive material. An array of slots 204 may be formed in the sheet 202 as shown in FIG. 2B, thereby forming strips 206. The slots 204 may be formed, for example, by metal stamping. A core 210 and housing 212 may be formed around the strips 206, as shown in FIG. 2C. As shown in FIG. 2D, connecting portions 208 of the sheet 202 may be removed to separate the strips 206. The strips 206 may be bent into a desired shape, such as a “U” shape as shown in FIG. 2E, thereby forming an inductor structure 200 with contacts 214. It will be apparent that the operations illustrated in FIG. 2A-E may be performed in any suitable order. For example, in some embodiments, the sheet 202 may be bent into a desired shape prior to forming the core 210 and/or housing 212 around the strips 206 and/or prior to removing the connecting portions 208. In some embodiments, the core 210 and/or housing 212 may be formed around the strips 206 by over-molding.
  • Referring again to FIGS. 1A-1C, although the core 102 of inductor structure 100 is shown with a cross-sectional shape that resembles a rectangle, it will be apparent that the core 102 may have any suitable cross-sectional shape, such as circular, elliptical, or polygonal.
  • Additionally, although inductor structure 100 is shown with six strips 104 a-f, other embodiments may include any number of one or more strips. For example, FIGS. 3A, 3B, and 3C illustrate an inductor structure 300 having two strips 304 disposed around a core 302 in accordance with various embodiments. The strips 304 include respective contacts 308. The inductor structure 300 further includes a housing 306 that partially covers the strips 304 and leaves the contacts 308 exposed.
  • Furthermore, it will be apparent that other arrangements of the strips and/or contacts of the inductor structure are possible without departing from the embodiments described herein.
  • For example, FIG. 4 illustrates an inductor structure 400 with SMT contacts 408 having an alternative arrangement from that of contacts 108 a-l. Inductor structure 400 is shown upside-down with contacts 408 pointed upward. The inductor structure 400 includes a core 402 with an upper surface 412 and a lower surface 414. Inductor structure 400 further includes strips 404 that extend across the upper surface 412 of the core 402 and partially across the lower surface 414, leaving a gap 410 between the contacts 408. The core 402 includes ridges 405 to facilitate spacing and/or alignment of the strips 404. The ends of the strips 402 are bent from a plane of the lower surface 414, thereby providing contacts 408 that extend from the lower surface 414. The gap 410 between the contacts 408 of individual strips 404 in inductor structure 400 may be less than the gap 110 between the contacts 108 a-l of inductor structure 104 for a core of similar size. This may allow shorter traces to be used to electrically couple the contacts 408 to one another to form one or more inductors.
  • FIG. 5 illustrates another inductor structure 500 that includes flush-mount SMT contacts 508 in accordance with various embodiments. The inductor structure 500 includes a core 502 with an upper surface 512 and a lower surface 514. Inductor structure 500 further includes strips 504 that extend around the upper surface 512 of the and partially across the lower surface 514, leaving a gap 510 between the contacts 508. The contacts 508 are disposed flat against the lower surface 514, thereby allowing for the inductor structure 500 to be flush-mounted onto the substrate.
  • FIG. 6A illustrates a modular inductor structure 600 in accordance with various embodiments. Inductor structure 600 that may be coupled with one or more other inductor structures 600 to form an array of inductor structures 600. Inductor structure 600 includes a strip 604 (not shown in FIG. 6B) disposed around a core 602. Another view of core 602 is shown in FIG. 6B, without the strip 604. Core 602 further includes a first mating feature 616 and a second mating feature 618. The first mating feature 616 may be mated with the second mating feature 618 of another inductor structure 600 to couple the inductor structures 600 together. Accordingly, the inductor structure 600 may be used to form an array of strips 604 having any desired quantity of strips 604.
  • FIG. 6C shows two inductor structures 600 coupled to one another. Other embodiments may include any number of one or more inductor structures 600 coupled to one another. Additionally, or alternatively, the individual inductor structures 600 may include any suitable number of one or more strips 604.
  • FIG. 7 illustrates an integrated circuit (IC) assembly 700 in accordance with various embodiments. IC assembly 700 includes a substrate 702 with a plurality of inductor structures 100 and a plurality of inductor structures 200 mounted on a surface 704 of the substrate 702. Traces (not shown) may be formed in the surface 704 of the substrate 702 to form inductors from the inductor structures 100 and/or 200.
  • In some embodiments, the substrate 702 is an epoxy-based laminate substrate having a core and/or build-up layers such as, for example, an Ajinomoto Build-up Film (ABF) substrate. The substrate 702 may include other suitable types of substrates in other embodiments including, for example, substrates formed from glass, ceramic, or semiconductor materials.
  • Although IC assembly 700 is shown in FIG. 7 to include a plurality of inductor structures 100 and a plurality of inductor structures 200, other embodiments may include any suitable number of one or more inductor structures 100 and/or 200.
  • In some embodiments, one or more inductor structures as described herein may be mounted on a same substrate on which a die is mounted. In some embodiments, the inductor structures may be used to route electrical power from a power source to the die. For example, the inductor structures may be included in a voltage regulator to regulate the power delivered to the die. In some embodiments, the inductor structure may be mounted on a land side of the substrate, opposite the die.
  • For example, FIG. 8 schematically illustrates a cross-section side view of an example integrated circuit (IC) package assembly 800, in accordance with some embodiments. The IC package assembly 800 may also be referred to as a die package assembly. The IC package assembly 800 includes a substrate 802 having a first side, S1, and a second side, S2, opposite the first side. The first side S1 may also be referred to as the die side of the substrate 802, while the second side S2 may also be referred to as the land side of the substrate 802. One or more dies (hereinafter “die 804) may be mounted on the first side S1. In various embodiments, one or more inductor structures 806 may be coupled to the second side S2 of the substrate. Suitable inductor structures 806 may include inductor structures 100, 200, 300, 400, 500, and/or 600 discussed herein.
  • As discussed herein, the inductor structure 806 may include one or more strips of conductive material having contacts at a first end and a second end of each strip. The strips may be disposed around a core of the inductor structure 806, with a gap between the first end and second end of the individual strips. The strips may be disposed adjacent to one another in an array. The IC package assembly 800 may further include traces 808 on a surface of the second side to electrically couple two or more of the strips of conductive material to one another to form inductive coils. Accordingly, the inductor structure 806 may be used to form one or more inductors in combination with the traces 808.
  • In some embodiments, the inductor structures 806 may be included in a voltage regulator to route electrical power from a power source (not shown) to the die 804. The voltage regulator may convert a supply voltage provided by the power supply to an input voltage used by the die 804. In some embodiments, the supply voltage may be higher than the input voltage. The voltage regulator may include one or more other components besides inductor structure 806, such as one or more capacitors and/or switches. In some embodiments, the voltage regulator may be a single or multiple phase voltage regulator, such as a Buck voltage regulator.
  • In some embodiments, one or more inductor structures 806 may be used to form a transformer. The transformer may be used in the voltage regulator. For example, the traces 808 may form a first inductor and a second inductor from one or more of the inductor structures 806. The first inductor may be electrically coupled to the power source and the second inductor may be electrically coupled to the die 804 to transform the supply voltage provided by the power supply to the input voltage used by the die 804.
  • In some embodiments, the inductor structures 806 may be coupled to the second side S2 within a shadow of the die 804 (shown at 805). In some embodiments, the inductor structures 806 may be mounted to a land-side cavity on the second side S2 of the substrate 802. One or more other devices, such as one or more capacitors, may also be mounted on the second side S2 of the substrate 802.
  • The die 804 may be attached to the substrate 802 according to a variety of suitable configurations, including a flip-chip configuration, as depicted, or other configurations such as wirebonding and the like. In the flip-chip configuration, an active side of the die 804 is attached to the first side S1 of the substrate 802 using die interconnect structures 810 such as bumps, pillars, or other suitable structures. The active side of the die 804 may have one or more transistor devices formed thereon. The die 804 may represent a discrete chip and may be, include, or be a part of a processor, memory, or application-specific integrated circuit (ASIC) in some embodiments. In some embodiments, an encapsulant 812 such as, for example, molding compound or underfill material may fully or partially encapsulate the die 804.
  • The die interconnect structures 810 may be configured to route electrical signals between the die 804 and the substrate 802. In some embodiments, the electrical signals may include, for example, input/output (I/O) signals and/or power or ground signals associated with the operation of the die 804.
  • The substrate 802 may include structures configured to route electrical signals to or from the die 804 and/or inductor structures 806. The structures may include, for example, traces (e.g., traces 808) disposed on one or more surfaces of the substrate 802 and/or internal structures such as, for example, trenches, vias or other interconnect structures (not shown) to route electrical signals through the substrate 802. For example, in some embodiments, the substrate 802 may include structures such as die bond pads (not shown) configured to receive the die interconnect structures 810 and route electrical signals between the die 804 and the substrate 802.
  • In some embodiments, the substrate 802 is an epoxy-based laminate substrate having a core and/or build-up layers such as, for example, an Ajinomoto Build-up Film (ABF) substrate. The substrate 802 may include other suitable types of substrates in other embodiments including, for example, substrates formed from glass, ceramic, or semiconductor materials.
  • FIG. 9 schematically illustrates a flow diagram for a method 900 of fabricating an inductor structure and/or forming one or more inductors from an inductor structure coupled to a substrate, in accordance with some embodiments. The method 900 may comport with embodiments described in connection with FIGS. 1-8.
  • At 902, the method 900 includes providing a substrate (e.g., substrate 802 of FIG. 8) having a first surface (e.g., S1 of FIG. 8) and a second surface (e.g., S2 of FIG. 8) opposite to the first surface. The first surface may be configured to have a die mounted thereon in some embodiments.
  • In some embodiments, the method 900 may further include forming the substrate. The substrate may be formed using techniques such as, for example, lamination of electrically insulative materials, deposition of electrically conductive materials, patterning of the electrically conductive materials by additive or subtractive processes, creating holes or vias by mechanical means, laser drilling or etch processes, the like, and other techniques.
  • At 904, the method 900 further includes forming an inductor structure (e.g., inductor structure 100, 200, 300, 400, 500, 600, and/or 806 described herein). The inductor structure may include a core and a plurality of strips of conductive material having contacts at a first end and a second end. The strips may be disposed around the core with a gap between the first end and the second end.
  • In some embodiments, forming the inductor structure at 904 may include forming the strips from a sheet of conductive material and/or over-molding the core around the strips (e.g., as shown in FIGS. 2A-2E and described above). Other embodiments may include forming the strips from conductive wire and bending and/or wrapping the strips around the core.
  • At 906, the method 900 further includes forming one or more traces (e.g., traces 808) on the second surface of the substrate to electrically couple two or more strips of the conductive material to one another to form one or more inductors. The traces may be formed by any suitable method, such as etching to form a stencil on the second surface.
  • At 908, the method 900 further includes mounting the inductor structure on the second surface of the substrate. The inductor structure may be mounted on the second surface with respective contacts of the inductor structure coupled to the one or more traces to form the one or more inductors. For example, the inductor structure may be mounted with the contacts disposed in or on holes in the stencil that are electrically connected by the traces. The contacts may be coupled to the second surface, for example, by soldering.
  • Various operations are described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. Embodiments of the present disclosure may be implemented into a system using any suitable hardware and/or software to configure as desired.
  • FIG. 10 schematically illustrates a computing device 1000 in accordance with one implementation of the invention. The computing device 1000 may house a board such as motherboard 1002. According to various embodiments, the motherboard 1002 may be a substrate (e.g., substrate 702 of FIG. 7 and/or substrate 802 of FIG. 8) having one or more inductor structures (e.g., inductor structures 100, 200, 300, 400, 500, 600, and/or 806) mounted to a surface of the substrate as described herein. The motherboard 1002 may include a number of components, including but not limited to a processor 1004 and at least one communication chip 1006. The processor 1004 may be physically and electrically coupled to the motherboard 1002. In some implementations, the at least one communication chip 1006 may also be physically and electrically coupled to the motherboard 1002. In further implementations, the communication chip 1006 may be part of the processor 1004. According to various embodiments, the processor 1004, the communication chip 1006 or other components (e.g., memory devices) described in connection with the computing device 1000 may be in the form of one or more dies (e.g., die 804 of FIG. 8) as described herein. The one or more inductor structures may be disposed on the motherboard 1002 and/or on a die package substrate. In some embodiments, the one or more inductors may be disposed on the land-side of the die package substrate, within a die shadow region (e.g., indicated by arrow 805 of FIG. 8).
  • Depending on its applications, computing device 1000 may include other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • The communication chip 1006 may enable wireless communications for the transfer of data to and from the computing device 1000. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible BWA networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 1006 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1006 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1006 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1006 may operate in accordance with other wireless protocols in other embodiments.
  • The computing device 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • The processor 1004 of the computing device 1000 may include a die (e.g., die 804 of FIG. 8) in an IC package assembly (e.g., IC package assembly 800 of FIG. 8) as described herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • The communication chip 1006 may also include a die (e.g., die 804 of FIG. 8) in an IC package assembly (e.g., IC package assembly 800 of FIG. 8) as described herein. In further implementations, another component (e.g., memory device or other integrated circuit device) housed within the computing device 1000 may contain a die (e.g., die 804 of FIG. 8) in an IC package assembly (e.g., IC package assembly 800 of FIG. 8) as described herein.
  • In various implementations, the computing device 1000 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1000 may be any other electronic device that processes data.
  • The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
  • These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims (19)

1. An apparatus comprising:
a substrate having a surface;
an inductor structure coupled to the surface, the inductor structure including
a core, and
a plurality of strips of conductive material having contacts at a first end and a second end, the strips disposed around the core with a gap between the first end and the second end; and
one or more traces on the surface of the substrate to electrically couple two or more of the strips of conductive material to one another to form one or more inductors.
2. The apparatus of claim 1, further comprising a housing covering a portion of the strips and leaving the contacts exposed.
3. The apparatus of claim 1, wherein the one or more traces form a first inductor and a second inductor from the plurality of strips of conductive material to form a transformer from the inductor structure.
4. The apparatus of claim 1, wherein the one or more traces electrically couple the two or more strips by electrically coupling the contact at the first end of a first strip of conductive material to the contact at the second end of an adjacent strip.
5. The apparatus of claim 1, wherein the strips of conductive material include copper wire.
6. The apparatus of claim 1, wherein the core includes molded plastic.
7. The apparatus of claim 1, wherein the core includes a magnetic material.
8. The apparatus of claim 1, wherein the contacts are surface-mount technology (SMT) leads.
9-18. (canceled)
19. A system comprising:
a substrate having a first surface and a second surface opposite to the first surface;
a die coupled to the first surface of the substrate, the die having an input terminal to receive electrical power for the die;
an inductor structure coupled to the second surface of the substrate and coupled to the input terminal to route electrical power from a power source to the die, the inductor structure including
a core, and
a plurality of strips of conductive material having contacts at a first end and a second end, the strips disposed around the core with a gap between the first end and the second end; and
one or more traces on the second surface of the substrate to electrically couple two or more of the strips of conductive material to one another to form one or more inductors.
20. The system of claim 19, further comprising a housing covering a portion of the strips and leaving the contacts exposed.
21. The system of claim 19, wherein the one or more inductors are included in a voltage regulator to convert a supply voltage provided from the power source to an input voltage used by the die.
22. The system of claim 19, wherein the one or more traces form a first inductor and a second inductor from the plurality of strips of conductive material to form a transformer to regulate the power routed to the die, wherein the first inductor is configured to be electrically coupled to the power source and the second inductor is configured to be electrically coupled to the die.
23. The system of claim 19, wherein the one or more traces electrically couple the two or more strips by electrically coupling the contact at the first end of a first strip of conductive material to the contact at the second end of an adjacent strip.
24. The system of claim 19, wherein the strips of conductive material include copper wire.
25. The system of claim 19, wherein the core includes molded plastic.
26. The system of claim 19, wherein the core includes a magnetic material.
27. The system of claim 19, wherein the inductor structure is disposed on the substrate in a shadow of the die.
28. The system of claim 19, wherein the contacts are surface-mount technology (SMT) leads.
US13/715,016 2012-12-14 2012-12-14 Surface-mount inductor structures for forming one or more inductors with substrate traces Abandoned US20140167900A1 (en)

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9480162B2 (en) 2012-10-30 2016-10-25 Intel Corporation Circuit board with integrated passive devices
US20170178797A1 (en) * 2015-12-21 2017-06-22 Infineon Technologies Austria Ag Surface Mount Inductor for Placement Over a Power Stage of a Power Converter
US20170178795A1 (en) * 2015-12-21 2017-06-22 Infineon Technologies Austria Ag Through-Hole Inductor for Placement Over a Power Stage of a Power Converter
TWI640023B (en) * 2017-09-26 2018-11-01 綠點高新科技股份有限公司 A method for making an inductor and the product made therefrom
US10333407B2 (en) 2015-05-06 2019-06-25 Infineon Technologies Austria Ag Power stage packages of a multi-phase DC-DC converter under a coupled inductor
JP2019207915A (en) * 2018-05-28 2019-12-05 太陽誘電株式会社 Coil component and electronic apparatus
US10855178B2 (en) 2015-05-29 2020-12-01 Infineon Technologies Austria Ag Discrete power stage transistor dies of a DC-DC converter under an inductor
CN112071580A (en) * 2020-08-14 2020-12-11 南京博兰得电子科技有限公司 Coupling inductor
US10944147B2 (en) 2018-03-06 2021-03-09 Avx Corporation Thin film surface mountable high frequency coupler
US11367557B2 (en) 2019-12-16 2022-06-21 International Business Machines Corporation Semiconductor chip having one or more on-chip metal winding and enclosed by top and bottom chip-external ferromagnetic cores
US11399238B2 (en) * 2018-07-23 2022-07-26 Knowles Electronics, Llc Microphone device with inductive filtering

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11259413B2 (en) * 2018-04-05 2022-02-22 Abb Power Electronics Inc. Inductively balanced power supply circuit and method of manufacture

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5351167A (en) * 1992-01-24 1994-09-27 Pulse Engineering, Inc. Self-leaded surface mounted rod inductor
US5805431A (en) * 1996-01-17 1998-09-08 Synergy Microwave Corporation Surface Mountable transformer
US6367143B1 (en) * 1998-03-10 2002-04-09 Smart Card Technologies Co. Ltd. Coil element and method for manufacturing thereof
US6445271B1 (en) * 1999-05-28 2002-09-03 Honeywell International Inc. Three-dimensional micro-coils in planar substrates
US20020140538A1 (en) * 2001-03-31 2002-10-03 Lg. Philips Lcd Co., Ltd. Method of winding coil and transformer and inverter liquid crystal display having coil wound using the same
US20060109071A1 (en) * 2004-11-19 2006-05-25 Thongsouk Christopher H Circuit board inductor
US20060145800A1 (en) * 2004-08-31 2006-07-06 Majid Dadafshar Precision inductive devices and methods
US7768370B2 (en) * 2007-08-29 2010-08-03 Hammond Power Solutions, Inc. Method and apparatus for mounting a circuit board to a transformer

Family Cites Families (108)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4597169A (en) * 1984-06-05 1986-07-01 Standex International Corporation Method of manufacturing a turnable microinductor
JP2877132B2 (en) 1997-03-26 1999-03-31 日本電気株式会社 Multilayer printed circuit board and manufacturing method thereof
US6108212A (en) 1998-06-05 2000-08-22 Motorola, Inc. Surface-mount device package having an integral passive component
US8178435B2 (en) 1998-12-21 2012-05-15 Megica Corporation High performance system-on-chip inductor using post passivation process
US6303423B1 (en) 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
JP3792445B2 (en) 1999-03-30 2006-07-05 日本特殊陶業株式会社 Wiring board with capacitor
KR100823767B1 (en) 1999-09-02 2008-04-21 이비덴 가부시키가이샤 Printed circuit board and method for manufacturing printed circuit board
KR101384035B1 (en) 1999-09-02 2014-04-09 이비덴 가부시키가이샤 Printed circuit board and method of manufacturing printed circuit board
US6370013B1 (en) 1999-11-30 2002-04-09 Kyocera Corporation Electric element incorporating wiring board
JP2001185442A (en) 1999-12-27 2001-07-06 Murata Mfg Co Ltd Connection structure of multiplayer capacitor and decoupling capacitor and wiring substrate
US6903617B2 (en) 2000-05-25 2005-06-07 Silicon Laboratories Inc. Method and apparatus for synthesizing high-frequency signals for wireless communications
US6970362B1 (en) 2000-07-31 2005-11-29 Intel Corporation Electronic assemblies and systems comprising interposer with embedded capacitors
US6775150B1 (en) 2000-08-30 2004-08-10 Intel Corporation Electronic assembly comprising ceramic/organic hybrid substrate with embedded capacitors and methods of manufacture
US6549071B1 (en) 2000-09-12 2003-04-15 Silicon Laboratories, Inc. Power amplifier circuitry and method using an inductance coupled to power amplifier switching devices
US6710433B2 (en) 2000-11-15 2004-03-23 Skyworks Solutions, Inc. Leadless chip carrier with embedded inductor
US6624500B2 (en) 2000-11-30 2003-09-23 Kyocera Corporation Thin-film electronic component and motherboard
US6532143B2 (en) 2000-12-29 2003-03-11 Intel Corporation Multiple tier array capacitor
US6512182B2 (en) 2001-03-12 2003-01-28 Ngk Spark Plug Co., Ltd. Wiring circuit board and method for producing same
DE60219712T2 (en) 2001-04-19 2008-02-28 Interuniversitair Microelektronica Centrum Vzw Manufacture of integrated tunable / switchable passive micro and millimeter wave modules
KR20020088212A (en) 2001-05-18 2002-11-27 삼성전자 주식회사 Stack chip scale package
US20030112110A1 (en) 2001-09-19 2003-06-19 Mark Pavier Embedded inductor for semiconductor device circuit
JP3492348B2 (en) 2001-12-26 2004-02-03 新光電気工業株式会社 Method of manufacturing package for semiconductor device
JP4202641B2 (en) 2001-12-26 2008-12-24 富士通株式会社 Circuit board and manufacturing method thereof
US6606237B1 (en) 2002-06-27 2003-08-12 Murata Manufacturing Co., Ltd. Multilayer capacitor, wiring board, decoupling circuit, and high frequency circuit incorporating the same
JP4243117B2 (en) 2002-08-27 2009-03-25 新光電気工業株式会社 Semiconductor package, manufacturing method thereof, and semiconductor device
TW571375B (en) * 2002-11-13 2004-01-11 Advanced Semiconductor Eng Semiconductor package structure with ground and method for manufacturing thereof
JP2004214258A (en) 2002-12-27 2004-07-29 Renesas Technology Corp Semiconductor module
US7327554B2 (en) 2003-03-19 2008-02-05 Ngk Spark Plug Co., Ltd. Assembly of semiconductor device, interposer and substrate
JP2004349457A (en) 2003-05-22 2004-12-09 Matsushita Electric Ind Co Ltd Large-scale integrated circuit (lsi) package
US7271476B2 (en) 2003-08-28 2007-09-18 Kyocera Corporation Wiring substrate for mounting semiconductor components
JP4700332B2 (en) 2003-12-05 2011-06-15 イビデン株式会社 Multilayer printed circuit board
US7095108B2 (en) 2004-05-05 2006-08-22 Intel Corporation Array capacitors in interposers, and methods of using same
JP2005327984A (en) 2004-05-17 2005-11-24 Shinko Electric Ind Co Ltd Electronic component and method of manufacturing electronic-component mounting structure
US7268419B2 (en) 2004-06-17 2007-09-11 Apple Inc. Interposer containing bypass capacitors for reducing voltage noise in an IC device
KR100645643B1 (en) 2004-07-14 2006-11-15 삼성전기주식회사 Manufacturing method of PCB having embedded passive-chips
TWI301739B (en) 2004-12-03 2008-10-01 Via Tech Inc Structure and method for embedded passive component assembly
JP4290158B2 (en) 2004-12-20 2009-07-01 三洋電機株式会社 Semiconductor device
US7541265B2 (en) 2005-01-10 2009-06-02 Endicott Interconnect Technologies, Inc. Capacitor material for use in circuitized substrates, circuitized substrate utilizing same, method of making said circuitized substrate, and information handling system utilizing said circuitized substrate
US20070177331A1 (en) 2005-01-10 2007-08-02 Endicott Interconnect Technologies, Inc. Non-flaking capacitor material, capacitive substrate having an internal capacitor therein including said non-flaking capacitor material, and method of making a capacitor member for use in a capacitive substrate
US7025607B1 (en) 2005-01-10 2006-04-11 Endicott Interconnect Technologies, Inc. Capacitor material with metal component for use in circuitized substrates, circuitized substrate utilizing same, method of making said circuitized substrate, and information handling system utilizing said circuitized substrate
US7750434B2 (en) * 2005-01-31 2010-07-06 Sanyo Electric Co., Ltd. Circuit substrate structure and circuit apparatus
JP2006237520A (en) 2005-02-28 2006-09-07 Nec Tokin Corp Thin-shaped multi-terminal capacitor, and manufacturing method therefor
US7372126B2 (en) 2005-03-31 2008-05-13 Intel Corporation Organic substrates with embedded thin-film capacitors, methods of making same, and systems containing same
KR100651358B1 (en) 2005-06-22 2006-11-29 삼성전기주식회사 Pcb embedding rf module
CN101213638B (en) * 2005-06-30 2011-07-06 L·皮尔·德罗什蒙 Electronic component and method of manufacture
JP4787559B2 (en) * 2005-07-26 2011-10-05 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP4838068B2 (en) 2005-09-01 2011-12-14 日本特殊陶業株式会社 Wiring board
US7742314B2 (en) 2005-09-01 2010-06-22 Ngk Spark Plug Co., Ltd. Wiring board and capacitor
JP5089880B2 (en) 2005-11-30 2012-12-05 日本特殊陶業株式会社 Capacitor for wiring board built-in, wiring board with built-in capacitor and manufacturing method thereof
EP1986320B1 (en) 2006-02-13 2013-06-26 Murata Manufacturing Co. Ltd. Saw filter
JP4892253B2 (en) 2006-02-28 2012-03-07 ルネサスエレクトロニクス株式会社 Electronic equipment
JP2007234843A (en) 2006-03-01 2007-09-13 Fujitsu Ltd Thin-film capacitor element, interposer, manufacturing method therefor, and semiconductor device
JP4714049B2 (en) 2006-03-15 2011-06-29 Okiセミコンダクタ株式会社 Semiconductor device and manufacturing method of semiconductor device
TWI407870B (en) 2006-04-25 2013-09-01 Ngk Spark Plug Co Method for manufacturing wiring board
US7808799B2 (en) 2006-04-25 2010-10-05 Ngk Spark Plug Co., Ltd. Wiring board
US7636242B2 (en) 2006-06-29 2009-12-22 Intel Corporation Integrated inductor
US7751205B2 (en) 2006-07-10 2010-07-06 Ibiden Co., Ltd. Package board integrated with power supply
US7518229B2 (en) 2006-08-03 2009-04-14 International Business Machines Corporation Versatile Si-based packaging with integrated passive components for mmWave applications
JP4920335B2 (en) 2006-08-07 2012-04-18 新光電気工業株式会社 Capacitor built-in interposer, manufacturing method thereof, and electronic component device
KR100780961B1 (en) 2006-10-02 2007-12-03 삼성전자주식회사 Reworkable passive element embedded printed circuit board and method for fabricating the same and semiconductor module with the same
KR100905862B1 (en) 2007-02-26 2009-07-02 삼성전기주식회사 Integrated multilayer chip capacitor module and integrated circuit apparatus having the same
US8713769B2 (en) 2007-03-10 2014-05-06 Sanmina-Sci Corporation Embedded capacitive stack
US7742276B2 (en) 2007-03-30 2010-06-22 Industrial Technology Research Institute Wiring structure of laminated capacitors
US7902662B2 (en) 2007-04-02 2011-03-08 E.I. Du Pont De Nemours And Company Power core devices and methods of making thereof
US8072732B2 (en) 2007-04-10 2011-12-06 Ngk Spark Plug Co., Ltd. Capacitor and wiring board including the capacitor
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
JP4429346B2 (en) 2007-08-31 2010-03-10 富士通株式会社 Semiconductor device and manufacturing method thereof
WO2009050829A1 (en) 2007-10-18 2009-04-23 Ibiden Co., Ltd. Wiring board and its manufacturing method
US7868431B2 (en) 2007-11-23 2011-01-11 Alpha And Omega Semiconductor Incorporated Compact power semiconductor package and method with stacked inductor and integrated circuit die
US8564967B2 (en) 2007-12-03 2013-10-22 Cda Processing Limited Liability Company Device and method for reducing impedance
US8106829B2 (en) 2007-12-12 2012-01-31 Broadcom Corporation Method and system for an integrated antenna and antenna management
JP5284155B2 (en) 2008-03-24 2013-09-11 日本特殊陶業株式会社 Component built-in wiring board
EP2259669A4 (en) 2008-03-24 2011-12-28 Ngk Spark Plug Co Component-incorporating wiring board
US8338940B2 (en) 2008-03-28 2012-12-25 Nec Corporation Semiconductor device
JP2009277940A (en) 2008-05-15 2009-11-26 Panasonic Corp Semiconductor package, circuit board for mounting, and mounting structure
US8161609B2 (en) 2008-05-21 2012-04-24 Intel Corporation Methods of fabricating an array capacitor
JPWO2010024233A1 (en) 2008-08-27 2012-01-26 日本電気株式会社 Wiring board capable of incorporating functional elements and method for manufacturing the same
US7791897B2 (en) 2008-09-09 2010-09-07 Endicott Interconnect Technologies, Inc. Multi-layer embedded capacitance and resistance substrate core
JP2010087499A (en) 2008-09-30 2010-04-15 Ibiden Co Ltd Method of manufacturing capacitor device
JP4711026B2 (en) * 2008-10-08 2011-06-29 株式会社村田製作所 Compound module
JP5407667B2 (en) 2008-11-05 2014-02-05 株式会社村田製作所 Semiconductor device
JP2010171414A (en) 2008-12-26 2010-08-05 Ngk Spark Plug Co Ltd Method of manufacturing wiring board with built-in component
JP2010171413A (en) 2008-12-26 2010-08-05 Ngk Spark Plug Co Ltd Method of manufacturing wiring board with built-in component
US8166447B1 (en) 2009-02-04 2012-04-24 Altera Corporation Power delivery network calculator tool for printed circuit board capacitors
JP2010212595A (en) 2009-03-12 2010-09-24 Murata Mfg Co Ltd Package substrate
JP5535765B2 (en) 2009-06-01 2014-07-02 日本特殊陶業株式会社 Manufacturing method of ceramic capacitor
US20100327433A1 (en) 2009-06-25 2010-12-30 Qualcomm Incorporated High Density MIM Capacitor Embedded in a Substrate
JP6039182B2 (en) 2009-06-30 2016-12-07 日本電気株式会社 Semiconductor device, mounting substrate used in the device, and method for manufacturing the mounting substrate
US20110050334A1 (en) * 2009-09-02 2011-03-03 Qualcomm Incorporated Integrated Voltage Regulator with Embedded Passive Device(s)
CN102474992B (en) 2009-12-15 2015-08-12 日本特殊陶业株式会社 Electric capacity built-in wiring substrate and accessory built-in wiring substrate
JP5381696B2 (en) 2009-12-25 2014-01-08 ソニー株式会社 Circuit board laminated module and electronic device
JP5603600B2 (en) 2010-01-13 2014-10-08 新光電気工業株式会社 WIRING BOARD, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR PACKAGE
JP2011146517A (en) 2010-01-14 2011-07-28 Murata Mfg Co Ltd Bypass capacitor mounting structure
JP5613523B2 (en) 2010-03-10 2014-10-22 パナソニック株式会社 Electronic circuit
US9048112B2 (en) 2010-06-29 2015-06-02 Qualcomm Incorporated Integrated voltage regulator with embedded passive device(s) for a stacked IC
JP5549494B2 (en) 2010-09-10 2014-07-16 富士通株式会社 Capacitor and manufacturing method thereof, circuit board, and semiconductor device
EP2619791B1 (en) 2010-09-23 2015-10-21 Qualcomm Mems Technologies, Inc. Integrated passives and power amplifier
KR20120039460A (en) 2010-10-15 2012-04-25 삼성전자주식회사 Semiconductor package
TWI405322B (en) 2010-12-29 2013-08-11 Ind Tech Res Inst Embedded capacitive substrate module
US9398694B2 (en) 2011-01-18 2016-07-19 Sony Corporation Method of manufacturing a package for embedding one or more electronic components
US9113569B2 (en) 2011-03-25 2015-08-18 Ibiden Co., Ltd. Wiring board and method for manufacturing same
US20120314389A1 (en) 2011-03-25 2012-12-13 Ibiden Co., Ltd. Wiring board and method for manufacturing same
JP2012209421A (en) 2011-03-30 2012-10-25 Sony Corp Solid-state image pickup device and electronic equipment
JP5275401B2 (en) 2011-04-18 2013-08-28 新光電気工業株式会社 WIRING BOARD, SEMICONDUCTOR DEVICE, AND WIRING BOARD MANUFACTURING METHOD
JP5275400B2 (en) 2011-04-18 2013-08-28 新光電気工業株式会社 WIRING BOARD, SEMICONDUCTOR DEVICE, AND WIRING BOARD MANUFACTURING METHOD
US20130015871A1 (en) 2011-07-11 2013-01-17 Cascade Microtech, Inc. Systems, devices, and methods for two-sided testing of electronic devices
US9406738B2 (en) 2011-07-20 2016-08-02 Xilinx, Inc. Inductive structure formed using through silicon vias
US9035194B2 (en) 2012-10-30 2015-05-19 Intel Corporation Circuit board with integrated passive devices

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5351167A (en) * 1992-01-24 1994-09-27 Pulse Engineering, Inc. Self-leaded surface mounted rod inductor
US5805431A (en) * 1996-01-17 1998-09-08 Synergy Microwave Corporation Surface Mountable transformer
US6367143B1 (en) * 1998-03-10 2002-04-09 Smart Card Technologies Co. Ltd. Coil element and method for manufacturing thereof
US6445271B1 (en) * 1999-05-28 2002-09-03 Honeywell International Inc. Three-dimensional micro-coils in planar substrates
US20020140538A1 (en) * 2001-03-31 2002-10-03 Lg. Philips Lcd Co., Ltd. Method of winding coil and transformer and inverter liquid crystal display having coil wound using the same
US20060145800A1 (en) * 2004-08-31 2006-07-06 Majid Dadafshar Precision inductive devices and methods
US20060109071A1 (en) * 2004-11-19 2006-05-25 Thongsouk Christopher H Circuit board inductor
US7768370B2 (en) * 2007-08-29 2010-08-03 Hammond Power Solutions, Inc. Method and apparatus for mounting a circuit board to a transformer

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9480162B2 (en) 2012-10-30 2016-10-25 Intel Corporation Circuit board with integrated passive devices
US10333407B2 (en) 2015-05-06 2019-06-25 Infineon Technologies Austria Ag Power stage packages of a multi-phase DC-DC converter under a coupled inductor
US11283356B2 (en) 2015-05-29 2022-03-22 Infineon Technologies North America Corp. Method of assembling a DC-DC converter
US10855178B2 (en) 2015-05-29 2020-12-01 Infineon Technologies Austria Ag Discrete power stage transistor dies of a DC-DC converter under an inductor
US20170178795A1 (en) * 2015-12-21 2017-06-22 Infineon Technologies Austria Ag Through-Hole Inductor for Placement Over a Power Stage of a Power Converter
US20170178797A1 (en) * 2015-12-21 2017-06-22 Infineon Technologies Austria Ag Surface Mount Inductor for Placement Over a Power Stage of a Power Converter
TWI640023B (en) * 2017-09-26 2018-11-01 綠點高新科技股份有限公司 A method for making an inductor and the product made therefrom
US10944147B2 (en) 2018-03-06 2021-03-09 Avx Corporation Thin film surface mountable high frequency coupler
US11652265B2 (en) 2018-03-06 2023-05-16 KYOCERA AVX Components Corporation Surface mountable microstrip line coupler having a coupling factor that is greater than −30dB at 28 GHz
JP2019207915A (en) * 2018-05-28 2019-12-05 太陽誘電株式会社 Coil component and electronic apparatus
JP7198000B2 (en) 2018-05-28 2022-12-28 太陽誘電株式会社 Coil parts and electronic equipment
US11399238B2 (en) * 2018-07-23 2022-07-26 Knowles Electronics, Llc Microphone device with inductive filtering
US11367557B2 (en) 2019-12-16 2022-06-21 International Business Machines Corporation Semiconductor chip having one or more on-chip metal winding and enclosed by top and bottom chip-external ferromagnetic cores
CN112071580A (en) * 2020-08-14 2020-12-11 南京博兰得电子科技有限公司 Coupling inductor

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