KR100645643B1 - Manufacturing method of PCB having embedded passive-chips - Google Patents

Abstract

The present invention provides a passive element chip embedded type that places a passive element chip on a printed circuit board and forms an unperforated hole for stacking an insulating layer or inserts the passive element chip in a printed circuit board, and inserts the passive element chip into the formed non-through hole. A method for manufacturing a printed circuit board. In addition, according to the present invention, a first step of forming a non-penetrating hole for inserting the passive element in the raw material layer laminated on the disc forming the core layer; After the circuit pattern is formed on the copper foil of the raw material, a passive element chip is inserted into an unthrough hole, and an insulating layer or another raw material in which a copper foil layer is laminated on one surface of the insulating layer is laminated on both sides of the raw material into which the passive element chip is inserted. A second step of heating and pressing; A third step of processing a via hole for providing an electrical connection to an outside of the electrode of the passive device chip; And a fourth step of forming copper plating on the via hole and forming a circuit pattern on the outside thereof.

Passive Device Chips, Printed Circuit Boards, Embedded Capacitors

Description

Manufacturing method of PCB having embedded passive-chips             

1A to 1E are process diagrams of a method of manufacturing a printed circuit board of a passive element chip embedded type according to a first embodiment of the present invention.

2A to 2E are flowcharts illustrating a method of manufacturing a printed circuit board having a passive element chip according to a second embodiment of the present invention.

3A to 3D are flowcharts illustrating a method of manufacturing a printed circuit board having a passive element chip according to a third embodiment of the present invention.

4A to 4D are flowcharts illustrating a method of manufacturing a printed circuit board having a passive device chip according to a fourth embodiment of the present invention.

5A through 5E are flowcharts illustrating a method of manufacturing a printed circuit board having a passive device chip according to a fifth embodiment of the present invention.

6A to 6C are flowcharts illustrating a method of manufacturing a printed circuit board having a passive element chip according to a sixth embodiment of the present invention.

FIG. 7 is a view for explaining a method of making an electrical connection using an electrically conductive material in a pattern formed on the lower copper foil layer of the unthrough hole of the first to sixth embodiments of the present invention.

8A to 8D are views showing various patterns formed on the lower copper foil layers used in the first to sixth embodiments.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed circuit board having a passive device chip embedded therein, and more particularly, to insert a passive device chip into an unthrough hole formed by forming an unthrough hole for inserting a passive device chip into a printed circuit board, The present invention relates to a method for manufacturing a printed circuit board having a passive device chip (PCB) on which a passive device chip is placed and an insulating layer is stacked.

To date, most discrete printed circuit boards (PCBs) are equipped with a typical discrete chip resistor or a typical discrete chip capacitor, but recently printed circuits incorporating passive elements such as resistors or capacitors Substrates are being developed.

This passive element embedded printed circuit board technology replaces the role of the existing chip resistors and chip capacitors by inserting passive elements such as resistors or capacitors into the outer or inner layers of the substrate by using new materials and materials. .

In other words, a printed circuit board having a passive element embedded therein is a form in which a passive element, for example, a capacitor is buried inside or outside the substrate itself, and a capacitor, which is a passive element regardless of the size of the substrate itself, is integrated as part of the printed circuit board. If so, this is referred to as an "embedded capacitor," and this substrate is called an embedded capacitor PCB.

The most important feature of such passive printed circuit boards is that the passive devices do not need to be mounted on the substrate surface because they are inherently provided as part of the printed circuit board.

On the other hand, the passive element embedded printed circuit board technology to date can be largely classified into three methods, which will be described in detail below.

First, there is a method of implementing a polymer thick film type capacitor which applies a polymer capacitor paste and thermally cures, that is, dries to form a capacitor.

This method produces a built-in capacitor by applying a polymer capacitor paste to an inner layer of a printed circuit board, and then printing and drying the copper paste to form an electrode after drying it.

Secondly, a ceramic filled photo-dielectric resin is coated on a printed circuit board to realize an embedded discrete type capacitor. Holds.

In this method, after the photosensitive resin containing ceramic powder is coated on a substrate, copper foils are laminated to form respective upper and lower electrodes, and then circuit patterns are formed and the photosensitive resin is etched. To implement individual capacitors.

Third, a capacitor is implemented by inserting a separate dielectric layer having a capacitance characteristic in an inner layer of the printed circuit board to replace the decoupling capacitor mounted on the surface of the printed circuit board. Saga holds related patented technology.

This method implements a power distributed decoupling capacitor by inserting a dielectric layer consisting of a power electrode and a ground electrode into an inner layer of a printed circuit board.

However, according to the conventional technology, there is a problem that the capacity value is very low and practicality is inferior. To solve this problem, an attempt to increase the capacity by using a material having a high capacitor capacity as a component and narrowing the interval between the contact points is made. there was.

However, the conventional method of the printed circuit board has a limitation in narrowing the gap, and a material having a high capacity value has a brittle property in which the physical properties of the material are well broken, so that the capacity of the printed circuit board is high. There have been significant problems in applying materials with values.

Because of these problems, recent attempts have been made to embed capacitor chips used in surface mounting into substrates. Japanese Patent Application Publication No. 2002-118367A of IBIDEN of Japan has already introduced a method of inserting a capacitor chip into the core layer of a printed circuit board.

The disclosed method impregnates the capacitor chip by inserting the capacitor chip into the core, covering the semi-cured epoxy resin on both sides, and heating and pressurizing it, forming a hole using a laser drill, and making electrical contact through plating. It is about how to make it.

However, this method has a problem of moving away from the IC mounted on the surface as the capacitor chip is inserted into the core. In addition, as a through hole is formed in the core and the capacitor chip is inserted, a process for hole processing is added, and even when inserted into the through hole, a circuit cannot be formed in the upper and lower portions of the capacitor chip. .

In addition, when the capacitor chip is inserted into the through hole of the core (Core), there is a problem that the handling is not easy because the capacitor chip is falling down.

Accordingly, the present invention has been made in order to solve the above problems, to form a through-hole in any insulating layer, but leave or remove the copper foil layer in the bottom of the through-hole as it is, inserting a passive device chip It is an object of the present invention to provide a method for manufacturing a passive circuit chip embedded printed circuit board that prevents the passive component chip from falling to the floor after insertion.                         

In addition, the present invention, by forming a non-penetrating hole in the core (Core) to leave the opposite copper foil as it is possible to form a circuit on the remaining copper foil, so that the passive device chip does not fall to the floor after insertion of the passive device chip. An object of the present invention is to provide a method for manufacturing a printed circuit board with a passive element chip.

In addition, the present invention, by placing a passive element chip on the surface of any insulating layer or core layer and stacking the insulating resin to reduce the number of steps due to the formation of unperforated holes, and close the distance to the IC chip to improve the electrical characteristics An object of the present invention is to provide an improved method for manufacturing a printed circuit board having a passive device chip embedded therein. In this case, a hole may be formed in the uncured insulating resin so that the passive device chip may be easily inserted into the insulating layer.

In addition, the present invention, by applying an electrically conductive material to the electrode of the passive element chip, and then inserted into the unthrough hole, the pad on the inner surface of the pad or circuit board in the bottom of the unthrough hole in the heating and pressing process of the insulating layer. The electrical connection can be made. On the contrary, after the material with electrical conductivity is applied to the pad on the bottom of the non-through hole or the pad on the inner surface of the circuit board, the passive element chip is inserted and the electrical connection is made in the heating and pressing process. It is an object of the present invention to provide a method for manufacturing a passive circuit chip embedded printed circuit board, which can reduce the number of holes and significantly reduce the processing cost and processing time of the holes.

In addition, the present invention forms an electrically conductive bump on the upper conductive layer before inserting the passive element chip or placing the passive element chip on the surface of an arbitrary insulating layer or core layer, before covering the insulating layer and pressing under heat. By using a method of attempting electrical contact by using a process of covering and heating and pressurizing it, a passive element chip embedded printing that reduces the hole processing process for electrical contact after heating and pressurizing and makes the electrical connection of the passive element easier and more efficient It is an object of the present invention to provide a method for manufacturing a circuit board.

The present invention for achieving the above object is a first step of forming a non-penetrating hole for inserting the passive device chip in the insulating layer of the raw material laminated on the disc forming the core layer; After the circuit pattern is formed on the copper foil of the raw material, a passive element chip is inserted into an unthrough hole, and an insulating layer or another raw material in which a copper foil layer is laminated on one surface of the insulating layer is laminated on both sides of the raw material into which the passive element chip is inserted. A second step of heating and pressing; A third step of processing a via hole for providing an electrical connection to an outside of the electrode of the passive device chip; And a fourth step of forming copper plating on the via hole and forming a circuit pattern on the outside.

In addition, the present invention comprises a first step of forming a non-through hole for inserting the passive element chip in the core layer and the copper foil layer remains to form a circuit pattern on the bottom surface of the non-through hole; The passive element chip is inserted into the non-through hole, and an insulating layer or a raw material in which a copper foil layer is laminated on one surface of the insulating layer on the core into which the passive element chip is inserted is laminated on one surface where the passive element chip is inserted and heated and pressed. Two steps; A pattern including a circuit was formed on the copper foil layer on the bottom surface of the unthrough hole, and the heating material was laminated by laminating the raw material on which the copper foil layer was laminated on one surface of the insulating layer or on the bottom surface of the unthrough hole on which the circuit was formed. A third step of doing; A fourth step of processing a via hole for providing an electrical connection to an outside of the electrode of the passive device chip; And a fifth step of forming copper plating on the via hole and forming a circuit pattern on the outside.

In addition, the present invention is a first step of placing a passive device chip on the insulating layer of the raw material laminated on the disc forming the core layer; A second step of heating and pressing the uncured insulating resin on the raw material on which the passive device chip of the first step is laminated; A third step of processing a via hole for providing an electrical connection to an outside of the electrode of the passive device chip; And a fourth step of forming copper plating on the via hole and forming a circuit pattern on the outside.

In addition, the present invention is a first step of placing a passive device chip on the core (Core) layer in which a circuit pattern is formed; A second step of heating and pressurizing the raw material having an insulating layer or a copper foil layer laminated on one surface of the insulating layer on both surfaces of the core layer; A third step of processing a via hole for providing an electrical connection to an outside of the electrode of the passive device chip; And a fourth step of forming copper plating on the via hole and forming a circuit pattern on the outside.

In addition, the present invention provides a first through-hole through which a passive element chip is to be inserted into an insulating layer of a raw material stacked on a disc forming a core layer, and after the circuit pattern is formed, inserting the passive element chip into an unthrough hole. step; A second step of laminating an insulating layer on the raw material into which the passive device chip is inserted and laminating copper foil having an electrically conductive bump; And a third step of forming a circuit pattern on the outside.

In addition, the present invention, the first step of forming a non-through hole to insert the passive device chip in the core layer; A second step of forming a circuit pattern on the copper foil of the raw material and inserting a passive element chip into an unthrough hole; A third step of laminating a raw material having a copper foil layer having conductive bumps formed thereon on the raw material into which the passive device chip is inserted and heating and pressing the raw material; And a fourth step of forming a circuit pattern on the outside.

In addition, the present invention is a first step of placing a passive element chip on the core layer or the raw material laminated on the original plate forming the core layer; A second step of laminating a raw material having a copper foil layer having conductive bumps formed thereon on the raw material where the passive device chip is located and heating and pressing the raw material; And a third step of forming a circuit pattern on the outside.

Referring now to Figure 1a below, the preferred embodiment of the present invention will be described in detail.

1A to 1E are process diagrams of a method of manufacturing a printed circuit board of a passive element chip embedded type according to a first embodiment of the present invention.

First, as shown in FIG. 1A, a circuit pattern is formed on the copper foil 102 of the master plate 100 forming the core layer by using an image forming process, and the insulating material 111 or the insulating material 111 is formed thereon. And one side is made of copper foil 112, the raw material 110 is laminated by heating and pressurizing in vacuum.

The type of copper foil laminate used as the master plate 100 includes glass / epoxy copper laminate, heat-resistant resin copper foil laminate, paper / phenolic copper foil laminate, high frequency copper foil laminate, flexible copper clad laminate, There are various things, such as a composite copper foil laminated board. However, for the production of double-sided printed circuit boards and multilayered printed circuit boards, it is preferable to use the glass / epoxy copper foil laminate 100 coated with the copper foil layers 102 and 103 on the insulating resin layer 101 which is mainly used.

After applying a dry film (not shown) to the original plate 100, a dry film is exposed and developed using an art work film on which a predetermined pattern is printed, thereby predetermining the dry film. Forming a pattern, spraying the corrosion solution to remove the copper foil 102 in the remaining areas except for the area protected by the dry film, and peeling off the dry film having played a role to finally form a wiring pattern of the copper foil 102. .

The dry film is composed of three layers, a cover film, a photo-resist film, and a mylar film, and a layer that substantially acts as a resist is a photoresist film.

In the exposure and development steps of the dry film, the artwork film having a predetermined pattern printed thereon is brought into close contact with the dry film and then irradiated with ultraviolet rays.

In this case, the black portion on which the pattern of the artwork film is printed does not transmit ultraviolet rays, and the non-printed portions transmit ultraviolet rays to cure the dry film under the artwork film.

Thus, when the dry film hardened copper foil laminated plate 102 is immersed in the developer, the uncured dry film portion is removed by the developer, leaving only the cured dry film portion to form a resist pattern. As the developer, an aqueous solution of sodium carbonate (Na ₂ CO ₃ ) or calcium carbonate (K ₂ CO ₃ ) is used.

As such, when a resist pattern is formed on the original plate 100 through the image forming process, the corrosion solution is sprayed to remove the copper foil 102 in the remaining regions except for the region protected by the resist pattern. The wiring pattern of the copper foil 102 is formed.

In addition, as shown in FIG. 1B, non-through holes 113a and 113b are formed in the portion where the passive element chip is to be inserted, and a circuit pattern is formed in the copper foil layer 112 into which the chip is inserted through an image process. The copper foil may be completely removed by spraying the corrosion solution on the lower part of the hole where the passive element chips 120a and 120b are inserted, or the copper foil layer 112 may be formed by forming the circuit pattern by preventing the corrosion solution from entering. You can leave it as it is.

1C, the passive device chips 120a and 120b are inserted into the unthrough holes 113a and 113b formed in the portion where the passive device chips 120a and 120b are to be inserted.

In addition, as shown in FIG. 1D, an insulating material 131 or a disk 130 including one surface of the insulating material 131 and copper foil 132 is laminated, and the passive element chips 120a and 120b are printed circuit by heating and pressing under vacuum. It is embedded in the substrate.

Next, via holes 141 to 146 are processed to electrically connect electrodes of the passive device chips 120a and 120b embedded in the printed circuit board as shown in FIG. 1E, and are electrolessly formed on the sidewalls of the via holes 141 to 146. Copper plating and electrolytic copper plating are performed to form the plating layers 151 to 156.

In the process of forming the via holes 141 to 146, it is preferable to use a method of forming a via hole according to a predetermined position using a CNC drill (Computer Numerical Control Drill) or a laser.

The CNC drill method is suitable for forming via holes in double-sided printed circuit boards or through holes in multilayer printed circuit boards.

After processing the via hole or the through hole using the CNC drill, it is preferable to perform a deburring process to remove burrs of copper foil, dust on the inner wall of the via hole, and dust on the surface of the copper foil layer generated during drilling. Do. In this case, since a roughness is provided on the surface of the copper foil layer, there is an advantage in that adhesion to copper is improved in the copper plating process.

The method using a laser is suitable for forming micro via holes of a multilayer printed circuit board. By using such a laser, the copper foil layer and the insulating resin layer may be simultaneously processed using a Yttrium Aluminum Garnet (YAG) laser, or the insulating resin layer is etched using a carbon dioxide laser after etching the copper foil layer in the portion where the via hole is to be formed. Can also be processed.

In addition, after the via hole is formed, it is preferable to perform a desmear process of removing the smear generated on the sidewall of the via hole by melting the insulating resin layer of the disc due to the heat generated during the formation.

On the other hand, since the sidewall of the via hole of the disc is an insulating resin layer, electrolytic copper plating cannot be performed immediately after the via hole is formed. Therefore, electroless copper plating is performed to perform electrical connection and electrolytic copper plating of the formed via holes.

Since electroless copper plating is plating on an insulator, it cannot be expected to react with electrically ions. Electroless copper plating is achieved by precipitation reactions, which are facilitated by catalysts.

To deposit copper from the plating solution, a catalyst must be attached to the surface of the material to be plated. This indicates that electroless copper plating requires a lot of pretreatment.

In one embodiment, the electroless copper plating process includes a degreasing process, a soft etching process, a pre-catalyst process, a catalyst treatment process, an activation process, an electroless copper plating process, and an oxidation process. Prevention process.

In the degreasing process, oxides or foreign substances present on the surface of the copper foil layer, particularly oils and fats, are removed with a chemical containing an acid or an alkali surfactant, and then the surfactant is washed with water completely.

In the soft corrosion process, fine roughness (for example, about 1 μm to 2 μm) is formed on the surface of the copper foil layer to uniformly adhere copper particles in the plating step, and remove untreated contaminants during the degreasing process.

In the preliminary catalysis, the disc is immersed in a low concentration of the catalyst chemical to prevent contamination of the chemical used in the catalytic treatment step or the concentration change. Moreover, since the original plate is immersed in the chemical tank of the same component, there is an effect that the catalytic treatment is activated more. In this precatalyst, it is preferable to use a catalyst chemical diluted to 1% to 3%.

In the catalyst treatment process, the catalyst particles are coated on the copper foil layer and the insulating resin layer surface (for example, sidewalls of the via holes) of the original plate. And serves to facilitate binding to the plating-catalyst particle is preferred to use a Pd-Sn compound, a Pd-Sn compound grains of Cu ₂ + ₂ and Pd plated.

In the electroless copper plating process, the plating solution is preferably made of CuSO ₄ , HCHO, NaOH and other stabilizers. In order for the plating reaction to be continued, it is necessary to balance the chemical reaction. For this purpose, it is important to control the composition of the plating solution. In order to maintain the composition, proper supply of scarce components, mechanical agitation, and a purification system of the plating liquid should be well operated. A filtration device for the by-products generated as a result of the reaction is required, and the use time of the plating liquid can be extended by utilizing the same.

In the anti-oxidation process, the anti-oxidation film is coated on the entire surface to prevent the plating film from being oxidized due to the alkali component remaining after the electroless copper plating.

However, the above-mentioned electroless copper plating process is generally thinner because its physical properties are lower than those of electrolytic copper plating.

And after apply | coating a dry film (not shown) to copper foil 103 and 132, a dry film is exposed and developed using the art work film by which the predetermined | prescribed pattern was printed, and a dry film A predetermined pattern is formed on the copper foil, and the corrosion solution is sprayed to remove the copper foils 103 and 132 in the remaining regions except for the area protected by the dry film, and the dry film having played a role is peeled off to finally form the copper foils 103 and 132. Wiring pattern is formed.

In FIG. 1, the chip passive device may be inserted over two or more insulating layers instead of one insulating layer.

2A to 2E are flowcharts illustrating a method of manufacturing a printed circuit board having a passive element chip according to a second embodiment of the present invention.

2A to 2E is different from the first embodiment of FIGS. 1A to 1E, in which a chip is inserted into a core layer to form various patterns on a copper foil on a bottom where a passive element is to be inserted. Is that there is.

First, as shown in Figure 2a, to prepare the original plate 200, which is a copper foil laminated plate on which the copper foil layers 202 and 203 are coated on the insulating resin layer 201, and the non-through hole into which the passive element chips 220a and 220b are to be inserted ( In order to form 210a and 210b, it is preferable to remove a part of the copper foil layer 202 using an image forming process.

In addition, as shown in FIG. 2B, the non-through holes 210a and 210b into which the passive element chips 220a and 220b are to be inserted are formed in the disc 200, and are inserted into the bottom surfaces of the non-through holes 210a and 210b. It is preferable not to remove the copper foil 203 so that the passive device chips 220a and 220b do not fall down.

Then, as shown in FIG. 2C, the passive element chips 220a and 220b are inserted into the unthrough holes 210a and 210b, and the insulating layer 231 or the insulating layer 231 and one surface thereof are made of copper foil 232. The stack 230 is heated and pressurized in a vacuum to embed the passive device chips 220a and 220b.

As shown in FIG. 2D, it is preferable to form a circuit in the copper foil 203 which is the bottom surface of the non-through holes 210a and 210b by using an image forming process, and if necessary, to complete the circuit, and the insulating layer 241 thereon. ) Or an insulating layer 241 and a disk 240 made of copper foil 242 on one side are laminated and heated under vacuum.

Next, via holes 251 to 256 are processed to electrically connect the electrodes of the passive device chips 220a and 220b embedded in the printed circuit board as shown in FIG. 2E, and are electrolessly formed on the sidewalls of the via holes 251 to 256. Copper plating and electrolytic copper plating are performed to form plating layers 261-266. After applying a dry film (not shown), a predetermined pattern is formed on the dry film by exposing and developing the dry film using an art work film on which a predetermined pattern is printed. , Spraying the corrosion solution to remove the copper foil in the remaining area except the area protected by the dry film, and peels off the dry film that played a role to finally form a wiring pattern of the copper foil (232, 242).

In FIG. 2, the chip passive device may be inserted through two or more insulating layers instead of one insulating layer.

3A to 3D are flowcharts illustrating a method of manufacturing a printed circuit board having a passive element chip according to a third embodiment of the present invention.

As shown in FIG. 3A, a circuit pattern is formed on the copper foil 302 of the disc 300 forming the core layer by using an image forming process, and the insulating material 311 or the insulating material 311 and one surface thereof are formed of copper foil ( It is preferable to remove the part of the copper foil layer 312 by using an image forming process where the original plate 310 made of 312 is heated and pressurized in a vacuum, and where the passive device chips 320a and 320b are located.

Next, as shown in FIG. 3B, a portion into which the passive device chips 320a and 320b are to be inserted is formed through an image forming process, and the passive device chips 320a and 320b are inserted therein, and an insulating material 341 or insulation is placed thereon. A disk 340 formed of a material 341 and one surface of copper foil 342 is stacked. In this case, it is preferable to form a hole in the insulating material 341 so that the passive device chips 320a and 320b are easily embedded into the insulating material 341. However, the hole 343 is not necessarily formed in the insulating material 341. You don't have to.

And, as shown in FIG. 3c, the passive element chips 320a and 320b are placed at the portion where the chip is to be inserted, and the insulating material 341 or the insulating material 341 and the disk 340 made of copper foil 342 on one surface thereof. And the passive element chips 320a and 320b are built by heating and pressing under vacuum.

Next, as illustrated in FIG. 3D, via holes 351 to 354 are processed to electrically connect electrodes of the passive device chips 320a and 320b embedded in the printed circuit board, and the radio is disposed on the sidewalls of the via holes 351 to 354. The copper plating and electrolytic copper plating are performed to form plating layers 361 to 364. After applying a dry film (not shown), a predetermined pattern is formed on the dry film by exposing and developing the dry film using an art work film on which a predetermined pattern is printed. , By spraying the corrosion solution to remove the copper foil in the remaining area except the area protected by the dry film, and peels off the dry film that has played a role to finally form a wiring pattern of the copper foil (301, 342).

In FIG. 3, the chip passive device may be inserted over two or more insulating layers instead of one insulating layer.

4A to 4D are flowcharts illustrating a method of manufacturing a printed circuit board having a passive device chip according to a fourth embodiment of the present invention.

The fourth embodiment of FIGS. 4A to 4D differs from the third embodiment of FIGS. 3A to 3D in that the chip is inserted into the surface of the core layer.

First, as shown in Figure 4a, to prepare a master plate 400, which is a copper foil laminated plate on which the copper foil layers 402 and 403 are coated on the insulating resin layer 401, and image-forming the portion where the passive element chips (410a, 410b) are to be inserted It is formed through a process.

At this time, it is preferable to form a circuit on both sides of the copper foil layer 400 at the same time as the portion where the passive element chips 410a and 410b are to be inserted.

4B, the passive device chips 410a and 410b are inserted into the portion where the passive device chips 410a and 410b are to be inserted, and the insulating material 411 or the insulating material 411 and copper foil on one surface thereof. The disk 410 which consists of 412 is laminated | stacked. At this time, the hole 413 is formed in the insulating material 411 so that the passive element chips 410a and 410b can be easily embedded into the insulating material 411. However, the hole 413 in the insulating material 411 must be used. It is not necessary to form

And, as shown in FIG. 4C, the passive element chips 410a and 410b are placed at the portion where the chip is to be inserted, and the insulating material 411 or the insulating material 411 and one surface of the disc 410 made of copper foil 412 thereon. Covering the inside of the passive element chips (410a, 410b) by heating and pressurizing in a vacuum.

Next, as illustrated in FIG. 4D, via holes 431 to 434 are processed to electrically connect electrodes of the passive element chips 410 a and 410 b embedded in the printed circuit board, and the radio is disposed on the sidewalls of the via holes 431 to 434. Plating layers 441 to 444 are formed by performing copper plating and electrolytic copper plating. After applying a dry film (not shown), an artwork film having a predetermined pattern printed thereon is used. By exposing and developing the dry film to form a predetermined pattern on the dry film, spraying the corrosion solution to remove copper foil in the remaining areas except the area protected by the dry film, and finally peeling off the dry film that has played a role. Wiring patterns of the copper foils 412 and 422 are formed.

In FIG. 4, the chip passive device may be inserted over two or more insulating layers instead of one insulating layer.

5A through 5E are flowcharts illustrating a method of manufacturing a printed circuit board having a passive device chip according to a fifth embodiment of the present invention.

First, as shown in FIG. 5A, a circuit pattern is formed on the copper foils 502 and 503 of the disc 500 forming the core layer by using an image forming process, and the insulating material 511 or the insulating material 511 is formed thereon. The disk 510 made of copper foil 512 on one side is heated and pressed in a vacuum, and an image forming process is used to form the unthrough holes 520a and 520b into which the passive element chips 530a and 530b are to be inserted. It is preferable to remove a part of the copper foil layer 512.

As shown in FIG. 5B, the non-through holes 520a and 520b are formed in the portion where the passive element chips 530a and 530b are to be inserted, and a circuit pattern is formed on the copper foil layer 512 into which the chips are inserted through an image process. In this case, the copper foil 512 may be completely removed by spraying the corrosion solution on the lower portion of the holes 520a and 520b into which the passive element chips 530a and 530b are inserted. 512 may be left as it is in the formation of the circuit pattern.

As shown in FIG. 5C, the passive device chips 530a and 530b are inserted into the unthrough holes 520a and 520b formed in the portion where the passive device chips 530a and 530b are to be inserted.

Then, as shown in FIG. 5D, an insulating material 541 or an insulating material 541 and a disk 540 made of copper foil 542 are stacked, and the passive element chips 530a and 530b are printed by heating and pressing under vacuum. It is embedded in the substrate. In this case, a copper foil including bumps 543a to 543d that enables electrical contact with the passive element chips 530a and 530b is used.

Then, as shown in FIG. 5E, a wiring pattern of copper foil is finally formed by using an image forming process.

In FIG. 5, the chip passive device may be inserted over two or more insulating layers instead of one insulating layer.

6A to 6C are flowcharts illustrating a method of manufacturing a printed circuit board having a passive element chip according to a sixth embodiment of the present invention.

As shown in FIG. 6A, a circuit pattern is formed on the copper foils 602 and 603 of the original plate 600 using an image forming process, and the insulating material 611 or the insulating material 611 and one surface thereof are made of copper foil 612. It is preferable to remove the portion of the copper foil layer 612 by using an image forming process where the original plate 610 is heated and pressurized in a vacuum and the passive element chips 620a and 620b are positioned.

Next, as shown in FIG. 6B, a portion where the passive device chips 620a and 620b are to be inserted is formed through an image forming process, and the passive device chips 620a and 620b are inserted therein, and the insulating material 641 or insulation thereon is inserted therein. A disk 640 made of a material 641 and one surface of copper foil 642 is stacked. In this case, it is preferable to form a hole in the insulating material 641 so that the passive device chips 620a and 620b are easily embedded into the insulating material 641. However, it is not necessary to form a hole in the insulating material 641. In this case, a copper foil including bumps 644a to 644d for allowing electrical contact with the passive element chips 620a and 620b is used.

6C, the wiring patterns of the copper foils 603 and 642 are finally formed using an image forming process.

In FIG. 6, the chip passive device may be inserted over two or more insulating layers instead of one insulating layer.

Meanwhile, as shown in FIG. 7, the passive device chip 710 may have various patterns 702 formed on the bottom surface thereof. The pattern 702 also serves to reduce the difference in thermal expansion coefficient between the passive element chip and the insulator of the substrate, and at the same time, the pattern 702 may connect the pattern and the chip by using the connection materials 703a and 704a. An electrically conductive material can be electrically connected, and a non-electrically conductive material can be bonded to the chip and the pad of the bottom.

The electrode expansion absorption patterns 703a and 704b serve to absorb the expansion of the electrode by the passive device chip.

8A to 8D are diagrams showing examples of electrode expansion and absorption patterns formed on the lower copper foil layers used in FIGS. 1 to 6.

As shown in FIG. 8A, the electrode expansion absorption pattern may be formed in one of the lower copper foil layers.

As illustrated in FIGS. 8B to 8D, pads or patterns having various shapes may be formed.

Meanwhile, the passive device chip may be one of all types of passive devices that can be mounted on a printed circuit board.

Herein, while the present invention has been described with reference to the preferred embodiments, those skilled in the art can variously change the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that modifications and variations can be made.

According to the present invention as described above, compared to the existing SMT method by embedding the components to be attached to the surface of the surface surface area is increased, if the size of the substrate can be reduced by the increased area can be manufactured more circuit boards in the same area have.

In addition, according to the present invention, as the solder joint is eliminated as compared to the conventional SMT method, it is possible to reduce lead, which is an environmental target material, and signal noise is also reduced.

In addition, according to the present invention, many applications occur as the passive element having a large capacitance value, which is not realized as compared with the conventional sheet form, can be mounted inside the circuit board.

    In addition, according to the present invention, since the chip is designed not to fall out as compared to the existing chip embedded technology, handling is easy during the process.

     In addition, according to the present invention, as compared to the conventional chip embedded technology, the space for inserting the chip forms a non-through hole rather than a through hole, so that the copper foil layer supporting the chip below the hole into which the chip is inserted does not fall under the hole. Since the circuit and various images can be formed, the design freedom is greatly increased.

     In addition, according to the present invention, compared to the existing chip embedded technology, the insertion of the core or the surface of the core or the insulating resin layer above or below the core, so as to close the distance to the active chip to reduce the inductance electrical The performance can be improved.

     Further, according to the present invention, the signal noise is reduced and the characteristics of the high frequency are better as the active parts are formed closer.

     In addition, according to the present invention, before the chip is inserted, an electroconductive material is formed on one side of the contact point of the chip to be inserted, thereby forming a hole for the electrical contact at the same time as the electrical press at the same time or before the heating press. Can be reduced by%.

     In addition, according to the present invention, it is possible to insert a bulky part by inserting a chip after processing a plurality of layers to make a space to insert only a core layer in order to insert a large capacity chip.

     In addition, according to the present invention, the electrical contact with the chip using the bump can be formed only by the heating and pressing process.

    In addition, according to the present invention, there is an effect that can be inserted into the printed circuit board all parts having a possible thickness including a resistor in addition to the passive element chip.

     In addition, according to the present invention there is an effect that can be inserted not only the chip passive element of the general type having an external electrode at both ends in the longitudinal direction, but also any type of passive element that can be mounted on the printed circuit board.

Claims (30)

A first step of forming an unthrough hole for inserting a passive element chip in a raw material layer laminated on a disc forming a core layer; After the circuit pattern is formed on the copper foil of the raw material, a passive element chip is inserted into an unthrough hole, and an insulating layer or another raw material in which a copper foil layer is laminated on one surface of the insulating layer is laminated on both sides of the raw material into which the passive element chip is inserted. A second step of heating and pressing; A third step of processing a via hole for providing an electrical connection to an outside of the electrode of the passive device chip; And A fourth step of forming copper plating in the via hole and forming a circuit pattern outside Method of manufacturing a passive device chip embedded printed circuit board comprising a. The method of claim 1, And after the first step, further comprising a fifth step of removing the lower copper foil of the unthrough hole. The method of claim 1, In the stacking of the raw materials on the core layer of the first step, forming a pattern for electrical connection and binding including the function of absorbing thermal expansion stress on the copper foil of the position where the passive element chip of the core layer is embedded A method for manufacturing a printed circuit board having a passive element chip. The method of claim 1, After the first step, a passive element chip embedded printed circuit further comprising a fifth step of forming a pattern for electrical connection and binding including the function of absorbing thermal expansion stress on the lower copper foil of the non-through hole. Method of manufacturing a substrate. The method of claim 1, And a fifth step of applying a conductive material to a position where the electrode of the passive device chip is mounted after the first step. The method of claim 1, And the non-through hole penetrates through a plurality of insulating layers. The method according to any one of claims 1 to 6, The passive device chip is a manufacturing method of a passive device chip embedded printed circuit board, characterized in that one of all types of passive devices that can be mounted on a printed circuit board. A first step of forming a circuit pattern by forming an unthrough hole for inserting a passive device chip in the core layer and leaving a copper foil layer on the bottom surface of the unthrough hole; A second step of inserting a passive element chip into the unthrough hole and laminating a heating material by laminating an insulating layer or a raw material having a copper foil layer laminated on one surface of the insulating layer on a core into which the passive element chip is inserted; A third step of forming a pattern including a circuit on the copper foil layer on the bottom surface of the unperforated hole, and heating and pressing the insulating layer or the raw material having the copper foil layer laminated on one surface of the insulating layer; A fourth step of processing a via hole for providing an electrical connection to an outside of the electrode of the passive device chip; And A fifth step of forming copper plating in the via hole and forming a circuit pattern outside Method of manufacturing a passive device chip embedded printed circuit board comprising a. delete The method of claim 8, In the stacking of the raw materials on the core layer of the first step, forming a pattern for electrical connection and binding including the function of absorbing thermal expansion stress on the copper foil of the position where the passive element chip of the core layer is embedded A method for manufacturing a printed circuit board having a passive element chip. The method of claim 8, After the first step, a passive element chip embedded printed circuit further comprising a fifth step of forming a pattern for electrical connection and binding including the function of absorbing thermal expansion stress on the lower copper foil of the non-through hole. Method of manufacturing a substrate. The method of claim 8, And a fifth step of applying a conductive material to a position where the electrode of the passive device chip is mounted after the first step. The method of claim 8, And the non-through hole penetrates through a plurality of insulating layers. The method according to any one of claims 8 to 13, The passive device chip is a manufacturing method of a passive device chip embedded printed circuit board, characterized in that one of all types of passive devices that can be mounted on a printed circuit board. A first step of placing a passive element chip on a raw material stacked on a disc forming a core layer; A second step of heating and pressing the insulating resin on the raw material on which the passive device chip of the first step is stacked; A third step of processing a via hole for providing an electrical connection to an outside of the electrode of the passive device chip; And A fourth step of forming copper plating in the via hole and forming a circuit pattern outside Method of manufacturing a passive device chip embedded printed circuit board comprising a. The method of claim 15, After the first step, And a fifth step of forming a hole into which the passive device chip can be inserted into an insulating resin laminated on the raw material on which the passive device chip is placed. The method of claim 15, Before the first step, And a fifth step of removing the copper foil at the position where the passive element chip of the raw material is to be placed. The method of claim 15, Prior to the first step, the passive element chip embedded printing, characterized in that the copper foil at the position where the passive element chip of the raw material is embedded, including a pattern for electrical connection and binding including the function of absorbing thermal expansion stress Method of manufacturing a circuit board. The method of claim 15, Prior to the first step, a method of manufacturing a passive element chip-embedded printed circuit board further comprises a fifth step of applying a conductive material to the position where the electrode of the passive element chip is mounted. The method of claim 15, The raw material laminated on the core layer is a multilayer raw material, the passive device chip manufacturing method of a printed circuit board with a passive device chip, characterized in that penetrates through the multilayer. The method according to any one of claims 15 to 19, The passive device chip is a manufacturing method of a passive device chip embedded printed circuit board, characterized in that one of all types of passive devices that can be mounted on a printed circuit board. Placing a passive device chip on the core layer; A second step of heating and pressing an insulating resin on a core layer in which the passive device chips of the first step are stacked; A third step of processing a via hole for providing an electrical connection to an outside of the electrode of the passive device chip; And A fourth step of forming copper plating in the via hole and forming a circuit pattern outside Method of manufacturing a passive device chip embedded printed circuit board comprising a. The method of claim 21, After the first step, And a fifth step of forming a hole into which the capacity chip can be inserted into an insulating resin laminated on the core layer on which the passive device chip is placed. . The method of claim 21, Before the first step, And a fifth step of removing the copper foil at the position where the passive element chip of the core layer is to be placed. The method of claim 21, Prior to the first step, the passive element chip embedded type comprising a pattern for electrical connection and binding including the function of absorbing thermal expansion stress on the copper foil of the position where the passive element chip of the core layer is embedded Method of manufacturing a printed circuit board. The method of claim 21, Prior to the first step, a method of manufacturing a passive element chip-embedded printed circuit board further comprises a fifth step of applying a conductive material to the position where the electrode of the passive element chip is mounted. The method of claim 21, The raw material stacked on the core layer is a multilayer raw material, the passive element chip manufacturing method of a passive element chip embedded printed circuit board, characterized in that penetrates through the multilayer. 27. The method of any of claims 21 to 26, The passive device chip is a manufacturing method of a passive device chip embedded printed circuit board, characterized in that one of all types of passive devices that can be mounted on a printed circuit board. A first step of forming an unthrough hole for inserting a passive element chip in a raw material layer laminated on a disc forming a core layer; A second step of forming a circuit pattern on the copper foil of the raw material and inserting a passive element chip into an unthrough hole; A third step of laminating a raw material having a copper foil layer having conductive bumps formed thereon on the raw material into which the passive device chip is inserted and heating and pressing the raw material; And Fourth step of forming a circuit pattern on the outside Method of manufacturing a passive device chip embedded printed circuit board comprising a. A first step of placing a passive element chip on a raw material stacked on a disc forming a core layer; A second step of laminating a raw material having a copper foil layer having conductive bumps formed thereon on the raw material where the passive device chip is located and heating and pressing the raw material; And Third step of forming a circuit pattern on the outside Method of manufacturing a passive device chip embedded printed circuit board comprising a.

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