US20110050334A1 - Integrated Voltage Regulator with Embedded Passive Device(s) - Google Patents

Integrated Voltage Regulator with Embedded Passive Device(s) Download PDF

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US20110050334A1
US20110050334A1 US12552321 US55232109A US2011050334A1 US 20110050334 A1 US20110050334 A1 US 20110050334A1 US 12552321 US12552321 US 12552321 US 55232109 A US55232109 A US 55232109A US 2011050334 A1 US2011050334 A1 US 2011050334A1
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Prior art keywords
voltage regulator
packaging substrate
die
voltage
active portion
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Abandoned
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US12552321
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Yuancheng Christopher Pan
Lew G. Chua-Eoan
Zhi Zhu
Junmou Zhang
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Qualcomm Inc
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Qualcomm Inc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of H01L27/00 - H01L49/00 and H01L51/00, e.g. forming hybrid circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/642Capacitive arrangements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/645Inductive arrangements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0254High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0262Arrangements for regulating voltages or for using plural voltages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. IMC (insert mounted components)
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit

Abstract

A semiconductor packaging system has a packaging substrate into which inductors and/or capacitors are partially or completely embedded. An active portion of a voltage regulator is mounted on the packaging substrate and supplies regulated voltage to a die also mounted on the packaging substrate. Alternatively, the active portion of the voltage regulator is integrated into the die the voltage regulator supplies voltage to. The voltage regulator cooperates with the inductors and/or capacitors to supply voltage to the die. The inductors may be through vias in the packaging substrate. For additional inductance, through vias in a printed circuit board on which the packaging substrate is mounted may couple to the through vias in the packaging substrate.

Description

    TECHNICAL FIELD
  • The present disclosure generally relates to integrated circuits (ICs). More specifically, the present disclosure relates to manufacturing integrated circuits.
  • BACKGROUND
  • Integrated circuits (ICs) are fabricated on wafers. Commonly, these wafers are semiconductor materials, such as silicon, and singulated to form individual dies. Through efforts of research and development, the size of the transistors making up the ICs has decreased to 45 nm and will soon decrease to 32 nm. As transistor size decreases, the supply voltage to the transistors decreases. The supply voltage is conventionally smaller than wall voltages available in most countries or battery voltages used in portable devices. For example, an IC may operate at 1.25 Volts whereas the wall voltage is 120V or 240V. In a portable device, such as cellular phone, the battery voltage may range from 6V at full charge to 3V at near empty charge.
  • A semiconductor die may be coupled to a voltage regulator that converts available voltages at wall outlets or batteries to lower voltages used by the die. The voltage regulator ensures a constant voltage supply is provided to the die. This is an important function, because the ability of transistors to tolerate voltages under or over the target voltage is small. Only tenths of a volt lower may create erratic results in the die; only tenths of a volt higher may damage the die.
  • Dies are mounted on a packaging substrate, and the packaging substrate is mounted on a printed circuit board (PCB) approximately 1-2 mm thick during assembly. Conventionally, the voltage regulator is located on the PCB with the die to which the voltage regulator supplies voltage. Placing the voltage regulator on the PCB separate from the die results in a voltage drop between the voltage regulator and the die that the voltage regulator supplies. For example, at a supply voltage of 1.125 Volts, a voltage drop of 0.100V may occur between the voltage regulator and the die as the voltage passes through the PCB, packaging substrate, and die. As the supply voltage decreases with shrinking transistor size, the voltage drop becomes a significant fraction of the supply voltage. Additionally, placing the voltage regulator on the PCB requires the use of pins on the die to allow the die to communicate with the voltage regulator. The die may send commands to the voltage regulator such as sleep or wake-up for scaling up or scaling down the voltage supply. The additional pins consume space on the die that could otherwise be eliminated.
  • Reducing the voltage drop from the voltage regulator to the die improves performance of the die. Maximum frequency of a die scales proportionally with supply voltage. For example, eliminating a voltage drop of 0.100V may increase a maximum frequency (fmax) of the die by 100 MHz. Alternatively, if the voltage drop is reduced and maximum frequency not increased, power consumption in the die is reduced. Power consumption is proportional to capacitance multiplied by a square of the supply voltage. Thus, reducing the supply voltage may result in significant power savings.
  • Further, conventional voltage regulators have slow response times due to the distance between the voltage regulator and the die. In the event the current transients are too fast for the voltage regulator to respond, decoupling capacitors provide additional power to the die. Voltage regulators located on the PCB often have response times in the microsecond range. Thus, large decoupling capacitors are placed on the packaging substrate to compensate for slow response times. The large decoupling capacitors occupy a large area. One conventional arrangement includes a bulk capacitor of microFarads and a multi-layer chip capacitor (MLCC) having hundreds of nanoFarads along with the voltage regulator on the PCB. The combination of the bulk capacitor and the MLCC supplies voltage to the die while the voltage regulator responds to the current transient.
  • Attempts have been made to place voltage regulators on the dies. However, voltage regulators include passive components such as inductors and capacitors that are also embedded in the dies. Passive devices consume die area, which increases manufacturing cost. For example, a die manufactured using 45 nm technology has a capacitance density of 10 femtoFarads/μm2. At this density a suitable amount of capacitance may consume over 2.5 mm2. Providing inductance to the voltage regulator conventionally uses an on-die inductor or a discrete inductor mounted on the packaging substrate. In addition to consuming large areas on a die, conventional on-die inductors have a low quality factor.
  • A quality factor for passive components embedded in a die is low because the passive components are manufactured thin to fit in the die. As the amount of conducting material shrinks, conductive or magnetic losses increase and degrade the quality factor. The quality factor is defined by the energy stored in a passive component versus energy dissipated in the passive component, for a passive component embedded in a die is low.
  • Thus, there is a need for a voltage regulator that is in close proximity to the die without consuming large amounts of die area.
  • BRIEF SUMMARY
  • According to one aspect of the disclosure, a voltage regulator has a passive portion at least partially embedded in a packaging substrate. The voltage regulator also has an an active portion fabricated in a die coupled to the passive portion.
  • According to another aspect of the disclosure, a method of supplying voltage to a die mounted on a packaging substrate includes mounting an active portion of a voltage regulator on the packaging substrate. The method also includes coupling the active portion of the voltage regulator to at least one passive component at least partially embedded in the packaging substrate. The method further includes coupling the die to the at least one passive component.
  • According to yet another aspect of the disclosure, a method of supplying power to a die includes providing a supply voltage to an active portion of a voltage regulator mounted on a packaging substrate mounted on a printed circuit board. The method also includes passing the supply voltage from the active portion of the voltage regulator to at least one inductor at least partially embedded in the packaging substrate. The method further includes passing the supply voltage from the at least one inductor to at least one capacitor at least partially embedded in the packaging substrate. The method also includes passing the supply voltage from the at least one capacitor to the die.
  • According to a further aspect of the disclosure, a semiconductor packaging system includes a packaging substrate into which at least one means for storing energy is at least partially embedded. The semiconductor packaging system also includes means for regulating voltage mounted on the packaging substrate. The regulating voltage means cooperating with the energy storing means.
  • The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the technology of the disclosure as set forth in the appended claims. The novel features which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.
  • FIG. 1 is a block diagram showing an exemplary wireless communication system in which an embodiment of the disclosure may be advantageously employed.
  • FIG. 2 is a block diagram illustrating a design workstation used for circuit, layout, and logic design of the disclosed semiconductor IC package.
  • FIG. 3 is a cross-sectional view illustrating a conventional voltage regulator on a printed circuit board.
  • FIG. 4 is a block diagram illustrating an exemplary voltage regulator on a die according to a first embodiment.
  • FIG. 5 is a cross-sectional view illustrating an exemplary voltage regulator on a die with an embedded parasitic inductance according to a second embodiment.
  • FIG. 6 is a cross-sectional view illustrating an exemplary voltage regulator on a packaging substrate according to a third embodiment.
  • FIG. 7A is a cross-sectional view illustrating an exemplary voltage regulator on a packaging substrate with a parasitic inductance according to a fourth embodiment.
  • FIG. 7B is a cross-sectional view illustrating an exemplary voltage regulator with a wirebond inductance according to a fifth embodiment.
  • FIGS. 8A-C are block diagram illustrating paths through a packaging substrate and printed circuit board that may provide inductance.
  • DETAILED DESCRIPTION
  • FIG. 1 is a block diagram showing an exemplary wireless communication system 100 in which an embodiment of the disclosure may be advantageously employed. For purposes of illustration, FIG. 1 shows three remote units 120, 130, and 150 and two base stations 140. It will be recognized that wireless communication systems may have many more remote units and base stations. Remote units 120, 130, and 150 include IC devices 125A, 125B and 125C, as disclosed below. It will be recognized that any device containing an IC may also include semiconductor components having the disclosed features and/or components manufactured by the processes disclosed here, including the base stations, switching devices, and network equipment. FIG. 1 shows forward link signals 180 from the base station 140 to the remote units 120, 130, and 150 and reverse link signals 190 from the remote units 120, 130, and 150 to base stations 140.
  • In FIG. 1, the remote unit 120 is shown as a mobile telephone, the remote unit 130 is shown as a portable computer, and the remote unit 150 is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be a device such as a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer. Although FIG. 1 illustrates remote units according to the teachings of the disclosure, the disclosure is not limited to these exemplary illustrated units. The disclosure may be suitably employed in any device which includes semiconductor components, as described below.
  • FIG. 2 is a block diagram illustrating a design workstation for circuit, layout, and design of a semiconductor part as disclosed below. A design workstation 200 includes a hard disk 201 containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation 200 also includes a display to facilitate design of a semiconductor part 210 that may include a circuit and semiconductor dies. A storage medium 204 is provided for tangibly storing the semiconductor part 210. The semiconductor part 210 may be stored on the storage medium 204 in a file format such as GDSII or GERBER. The storage medium 204 may be a CD-ROM, DVD, hard disk, flash memory, or other appropriate device. Furthermore, the design workstation 200 includes a drive apparatus 203 for accepting input from or writing output to the storage medium 204.
  • Data recorded on the storage medium 204 may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. Providing data on the storage medium 204 facilitates the design of the semiconductor part 210 by decreasing the number of processes for designing circuits and semiconductor dies.
  • FIG. 3 is a cross-sectional view illustrating a conventional voltage regulator on a printed circuit board. An IC product 300 includes a printed circuit board (PCB) 310 that supports packaging substrates and provides communication between packaging substrates on the PCB 310. A packaging substrate 320 is coupled to the PCB 310 through a packaging connection 322 such as bumps or pillars and includes through vias 324 to enable communications between the PCB 310 and a die 330. The die 330 is coupled to the packaging substrate 320 through an interconnect structure 332 such as bumps or pillars.
  • A voltage regulator 340 is coupled to the PCB 310 through a packaging connection 342. The voltage regulator 340 conventionally couples to discrete passive components such as inductors and capacitors mounted on the PCB 310. Low inductance passes (not shown) provide power from the voltage regulator 340 to the die 330. The low inductance passes are restricted in location on the PCB 310, which also restricts location of the voltage regulator 340. Thus, the distance between the voltage regulator 340 and the die 330 has a fixed minimum based on the PCB 310.
  • For the reasons discussed above including large voltage drop between the voltage regulator and the die, slow response times due to distance from the die to the voltage regulator, increased PCB size, the use of large decoupling capacitors, and the use of additional pins on the die to communicate with the voltage regulator, locating a voltage regulator on the PCB separate from the packaging substrate may not provide sufficient voltages to the die for proper operation. If the supply voltage drops below an acceptable level, the circuits on the die may output incorrect results or stop working completely.
  • According to one embodiment, a voltage regulator may be integrated into the die. An integrated voltage regulator in the die does not use additional pins for communicating with the die. Instead, communication occurs through interconnects in the die. The integrated voltage regulator is also closer to the die resulting in quicker response times to current transients and smaller decoupling capacitors to filter the output of the voltage regulator. Furthermore, passive components may be embedded in the packaging substrate to reduce area on the die occupied by the voltage regulator.
  • Passive components may be embedded in a packaging substrate or a PCB. Embedding the passive components maintains a short path having low inductance from the voltage regulator to the die. Further, the voltage regulator control loop bandwidth is increased by the higher switching frequency and shortened feedback path between the voltage regulator and the die.
  • Larger inductance values are achieved by embedding passive components in comparison to conventional parasitic air-core inductors in packaging substrate routing or PCB routing. Embedding passive components also reduces die size by reducing or eliminating discrete passive components of the voltage regulator, which may otherwise be located side-by-side with the die.
  • FIG. 4 is a cross-sectional view illustrating an exemplary voltage regulator on a die according to a first embodiment. An IC product 400 includes a packaging substrate 420 coupled to a PCB 410 through a packaging connection 422 such as bumps or pillars. The packaging substrate 420 includes embedded passive components that may store energy in magnetic or electric form. For example, an embedded inductor 450 and an embedded capacitor 460 are at least partially embedded in the packaging substrate 420. The embedded inductor 450 and/or the embedded capacitor 460 may use embedded die substrate (EDS) technology. In one embodiment, the embedded capacitor 460 may have capacitance values in the hundreds of nanoFarads and provide decoupling capacitance to a die 430. The die 430 is coupled to the packaging substrate 420 through an interconnect structure 432 such as bumps or pillars.
  • Manufacturing the embedded inductor 450 and the embedded capacitor 460 in the packaging substrate 420 may use a lamination process according to one embodiment. For example, the packaging substrate 420 may start as a core with two internal layers separated by a thick dielectric layer. Holes are placed in the substrate using a laser drilling process and tape placed on a backside of the core. The holes are filled to form the embedded inductor 450 and the embedded capacitor 460, and a top side of the core is laminated. The embedded inductor 450 may be, for example, non air-core inductors to obtain higher inductance values than air-core inductors. Next, tape is peeled off the back side of the core, and the back side of the core is laminated. The inductance of the embedded inductor 450 and the capacitance of the embedded capacitor 460 are selected, in part, from parameters including a supply voltage of the die 430 and an operating frequency of the die 430. Passive components located in the packaging substrate 420 may use thicker copper than passive components located in a die and thus have smaller losses and a higher quality (Q) factor.
  • An active portion of a voltage regulator 440 is fabricated on the die 430 and includes, for example, a driver stage, a feedback stage, and/or a digital controller. The active portion of the voltage regulator 440 communicates with the embedded inductor 450 through an electrical path 426. An electrical path 427 couples the embedded inductor 450 to the embedded capacitor 460. An electrical path 428 couples the embedded capacitor 460 to the die 430. An electrical path 424 enables communication from the die 430 to the PCB 410. The electrical path 424 may be used, for example, to provide voltage to the active portion of the voltage regulator 440. That is, regulated voltage provided to the die 430 passes through the electrical path 424 to the active portion of the voltage regulator 440, then to the embedded inductor 450, and the embedded capacitor 460.
  • In one embodiment, the active portion of the voltage regulator 440 is integrated in the die 430. Thus, the active portion of the voltage regulator 440 responds quickly to current transients that occur in the die 430. According to one embodiment, the active portion of the voltage regulator 440 has a response frequency of approximately 200 MHz. Additionally, embedded passive components such as the embedded inductor 450 and the embedded capacitor 460 in the packaging substrate 420 reduce area on the die 430 that would otherwise be occupied by passive components. The voltage regulator 440 with embedded passive components as described above may, according to one embodiment, provide currents of several amps to the die 430.
  • In an alternative configuration, some of the embedded passive components may be replaced with vias in the packaging substrates. FIG. 5 is a cross-sectional view illustrating an exemplary voltage regulator on a die with an embedded parasitic inductance according to a second embodiment.
  • The packaging substrate 420 includes vias 526 having a parasitic inductance used by the active portion of the voltage regulator 440 as inductors for supplying voltage to the die 430. The vias 526 may be through vias, which extend the entire height of the packaging substrate 420. The through vias 526 may be coupled through the packaging connection 422 to through vias 516 in the PCB 410 if a larger inductance is desired than obtained with the through vias 526 alone. The use of parasitic inductance in through vias within the packaging substrate as a passive component simplifies semiconductor manufacturing by reducing a number of processes to embed inductors in the packaging substrate.
  • According to a third embodiment, an active portion of a voltage regulator may be separated from the die and mounted on the packaging substrate. FIG. 6 is a cross-sectional view illustrating an exemplary voltage regulator on a packaging substrate according to a third embodiment. An IC product 600 includes a packaging substrate 620 coupled to a PCB 610 through a packaging connection 622 such as bumps or pillars. A die 630 is coupled to the packaging substrate 620 through an interconnect structure 632 such as bumps or pillars. Additionally, an active portion of a voltage regulator 640 is coupled to the packaging substrate 620 through an interconnect structure 642 such as bumps or pillars. Inside the packaging substrate 620 is an embedded inductor 650 and an embedded capacitor 660.
  • The embedded capacitor 660 is coupled to the die 630 through an electrical path 628 and to the embedded inductor 650 through an electrical path 627. The embedded inductor 650 is coupled to the active portion of the voltage regulator 640 by an electrical path 626. Voltage is provided to the active portion of the voltage regulator 640 by an electrical path 624 from the PCB 610 through the packaging connection 622, the electrical path 624, and the interconnect structure 642.
  • The voltage regulator of FIG. 6 is an off-die voltage regulator coupled to the same packaging substrate as the die to which the voltage regulator supplies voltage. Locating the active portion of the voltage regulator on the packaging substrate but separate from the die allows different processes to be used for manufacturing the active portion of the voltage regulator and the die. For example, the die may be fabricated with 32 nm or 45 nm processes while the active portion of the voltage regulator may be fabricated with 0.18 μm processes. Additionally, the active portion of the voltage regulator may be manufactured at a different fabrication site than the die.
  • Turning now to a fourth embodiment, some of the embedded passive components may be replaced with vias in the packaging substrates. FIG. 7A is a cross-sectional view illustrating an exemplary voltage regulator on a packaging substrate with a parasitic inductance according to a fourth embodiment. An IC product 700 includes vias 726 in the packaging substrate 620 having a parasitic inductance that act as a filter for voltage provided from the active portion of the voltage regulator 640. Additional vias 716 in the PCB 610 may couple to the vias 726 through the packaging connection 622, if additional inductance is desired. The vias 716 are coupled through a conducting layer 730 on the PCB 610. The vias 716 or the vias 726 may be through vias, which extend the entire height of the PCB 610 or the packaging substrate 620, respectively.
  • Voltage is provided to the active portion of the voltage regulator 640, for example, through the electrical path 624. Regulated voltage is then output to the vias 726 and the vias 716. An electrical path 727 couples one of the vias 726 to the embedded capacitor 660, which is coupled to the die 630 through the electrical path 628.
  • According to a fifth embodiment, inductance is provided by wirebonds. FIG. 7B is a cross-sectional view illustrating an exemplary voltage regulator with a wirebond inductance. A wirebond 750 couples the active portion of the voltage regulator 640 to one of the vias 716. The wirebond 750, the vias 716 and the conducting layer 730 provide inductance to the active portion of the voltage regulator 640.
  • Embedded passives in which through vias provide inductance for a voltage regulator will now be described in further detail. FIGS. 8A-C are block diagrams illustrating paths through a packaging substrate and PCB that may provide inductance. FIG. 8A is a block diagram illustrating a path 800 through a packaging substrate and PCB according to one embodiment. A top conductive layer 802 and a bottom conductive layer 810 of a packaging substrate are shown. Inner layers 804, 806 of the packaging substrate are also shown. A through via 805, couples the top conductive layer 802 and the bottom conductive layer 810. A packaging connection 812 may be a bump of a ball grid array and couples the bottom conductive layer 810 to a top conductive layer 820 of a PCB. A through via 822 couples the top conductive layer 820 to a bottom conductive layer 830. The bottom conductive layer 830 may be an interconnect that couples to another through via in the PCB. The amount of inductance in the path 800 is proportional to a length of the path 800.
  • FIG. 8B is a block diagram illustrating a path 840 having a longer length than the path 800. A bottom conductive layer 842 couples the through via 822 to another through via in the PCB. The bottom conductive layer 842 includes extra length, for example in a coil, which increases the inductance of the path 840.
  • FIG. 8C is a block diagram illustrating a path 850 having a longer length than the path 830. An inductor coil 852 mounted on a back side of the PCB couples the through via 822 to another through via in the PCB. In this embodiment, a coiled wire 854 wraps around a block 852 to extend the length of the path 850.
  • A voltage regulator with passives embedded in packaging maintains a short and low inductive path from the voltage regulator to the die. Additionally, increased voltage regulator control loop bandwidth increases operating frequency and shortens a feedback path to the voltage regulator. Passive components embedded in the packaging substrate allows increased inductance and capacitance values. Further, the embedded passive components reduce packaging substrate top side area consumed by passive components.
  • Although the terminology “through silicon via” includes the word silicon, it is noted that through silicon vias are not necessarily constructed in silicon. Rather, the material can be any device substrate material.
  • Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the technology of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims (22)

1. A voltage regulator, comprising:
a passive portion at least partially embedded in a packaging substrate; and
an active portion fabricated in a die coupled to the passive portion.
2. The voltage regulator of claim 1, in which the passive portion comprises at least one capacitor.
3. The voltage regulator of claim 2, in which the at least one capacitor is an embedded die.
4. The voltage regulator of claim 1, in which the die is mounted on the packaging substrate.
5. The voltage regulator of claim 4, further comprising:
a second die mounted on the packaging substrate to which the active portion supplies voltage.
6. The voltage regulator of claim 1, in which the passive portion comprises at least one inductor.
7. The voltage regulator of claim 6, in which the passive portion further comprises at least one capacitor.
8. The voltage regulator of claim 6, in which the at least one inductor comprises a first plurality of through vias in the packaging substrate.
9. The voltage regulator of claim 8, in which the at least one inductor further comprises a second plurality of through vias in a printed circuit board that couples to the first plurality of through vias in the packaging substrate.
10. The voltage regulator of claim 9, further comprising a coil that couples the second plurality of through vias.
11. The voltage regulator of claim 10, in which the coil comprises an inductor coil mounted on a back side of the printed circuit board, the inductor coil wrapping a core.
12. The voltage regulator of claim 1, integrated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.
13. A method of supplying voltage to a die mounted on a packaging substrate, the method comprising:
mounting an active portion of a voltage regulator on the packaging substrate; and
coupling the active portion of the voltage regulator to at least one passive component at least partially embedded in the packaging substrate; and
coupling the die to the at least one passive component.
14. The method of claim 13, in which mounting the active portion of the voltage regulator comprises mounting the die on the packaging substrate, the die including the active portion of the voltage regulator.
15. The method of claim 13, in which coupling the active portion of the voltage regulator to at least one passive component comprises coupling the active portion of the voltage regulator to at least one through via that provides inductance to the active portion of the voltage regulator.
16. The method of claim 13, in which coupling the active portion of the voltage regulator to at least one passive component comprises:
coupling the active portion of the voltage regulator to at least one capacitor at least partially embedded in the packaging substrate; and
coupling the active portion of the voltage regulator to at least one inductor at least partially embedded in the packaging substrate.
17. A method of supplying power to a die, the method comprising:
providing a supply voltage to an active portion of a voltage regulator mounted on a packaging substrate mounted on a printed circuit board;
passing the supply voltage from the active portion of the voltage regulator to at least one inductor at least partially embedded in the packaging substrate;
passing the supply voltage from the at least one inductor to at least one capacitor at least partially embedded in the packaging substrate; and
passing the supply voltage from the at least one capacitor to the die.
18. The method of claim 17, in which passing the supply voltage to at least one inductor comprises passing the supply voltage to a first plurality of through vias in the packaging substrate.
19. The method of claim 18, further comprising:
passing the supply voltage from the first plurality of through vias in the packaging substrate to a second plurality of through vias in the printed circuit board; and
passing the supply voltage from the second plurality of through vias in the printed circuit board to the first plurality of through vias in the packaging substrate.
20. A semiconductor packaging system, comprising:
a packaging substrate into which at least one means for storing energy is at least partially embedded; and
means for regulating voltage mounted on the packaging substrate and cooperating with the energy storing means.
21. The semiconductor packaging system of claim 20, further comprising:
a first die mounted on the packaging substrate into which the voltage regulating means is integrated; and
a second die mounted on the packaging substrate, the second die receiving regulated voltage from the voltage regulating means.
22. The semiconductor packaging system of claim 20, in which the energy storing means stores at least one of magnetic energy and electric energy.
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US13108335 US20110215863A1 (en) 2009-09-02 2011-05-16 Integrated Voltage Regulator with Embedded Passive Device(s)
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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110108947A1 (en) * 2009-11-12 2011-05-12 Guzek John S Microelectronic device and method of manufacturing same
US20110215863A1 (en) * 2009-09-02 2011-09-08 Qualcomm Incorporated Integrated Voltage Regulator with Embedded Passive Device(s)
WO2013148932A1 (en) * 2012-03-30 2013-10-03 Advanced Micro Devices, Inc. Circuit board with integrated voltage regulator
US20140217547A1 (en) * 2012-03-29 2014-08-07 Adel A. Elsherbini Semiconductor package with air core inductor (aci) and magnetic core inductor (mci)
US20140268615A1 (en) * 2013-03-14 2014-09-18 Qualcomm Incorporated Two-stage power delivery architecture
GB2520149A (en) * 2013-09-27 2015-05-13 Intel Corp Die package with superposer substrate for passive components
US9048112B2 (en) 2010-06-29 2015-06-02 Qualcomm Incorporated Integrated voltage regulator with embedded passive device(s) for a stacked IC
CN104916623A (en) * 2014-03-12 2015-09-16 联发科技股份有限公司 Semiconductor package and method for fabricating base for semiconductor package
US20150271913A1 (en) * 2014-03-18 2015-09-24 Texas Instruments Deutschland Gmbh Electronic device package with vertically integrated capacitors
US20160095225A1 (en) * 2014-09-26 2016-03-31 Qualcomm Incorporated Inductor system for multi-phase power management integrated circuits
US20170178786A1 (en) * 2015-12-17 2017-06-22 William J. Lambert Helical plated through-hole package inductor
US10096582B2 (en) 2016-07-08 2018-10-09 Cisco Technology, Inc. Enhanced power distribution to application specific integrated circuits (ASICS)
EP3257079A4 (en) * 2015-02-11 2018-11-21 Chaoyang Semiconductor Jiangyin Technology Co., Ltd. Switched power stage with integrated passive components

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9035194B2 (en) * 2012-10-30 2015-05-19 Intel Corporation Circuit board with integrated passive devices
US20140167900A1 (en) * 2012-12-14 2014-06-19 Gregorio R. Murtagian Surface-mount inductor structures for forming one or more inductors with substrate traces
US20140225706A1 (en) * 2013-02-13 2014-08-14 Qualcomm Incorporated In substrate coupled inductor structure
US9343418B2 (en) * 2013-11-05 2016-05-17 Xilinx, Inc. Solder bump arrangements for large area analog circuitry
US20150237732A1 (en) * 2014-02-18 2015-08-20 Qualcomm Incorporated Low-profile package with passive device
US9847323B1 (en) * 2015-08-19 2017-12-19 Xilinx, Inc. Integrated circuit package having voltage regulation circuitry
WO2017210279A1 (en) * 2016-05-31 2017-12-07 The Regents Of The University Of Colorado, A Body Corporate Smart cable and methods thereof
US10083922B2 (en) * 2016-11-23 2018-09-25 Intel Corporation Inductor interconnect

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6777818B2 (en) * 2001-10-24 2004-08-17 Intel Corporation Mechanical support system for a thin package
US6930381B1 (en) * 2002-04-12 2005-08-16 Apple Computer, Inc. Wire bonding method and apparatus for integrated circuit
US20060071649A1 (en) * 2004-09-30 2006-04-06 Gerhard Schrom Apparatus and method for multi-phase transformers
US20070013080A1 (en) * 2005-06-29 2007-01-18 Intel Corporation Voltage regulators and systems containing same
US20070114651A1 (en) * 2005-10-29 2007-05-24 Stats Chippac Ltd. Integrated circuit stacking system with integrated passive components
US20080001698A1 (en) * 2006-06-29 2008-01-03 Peter Hazucha Integrated inductors
US20080002380A1 (en) * 2006-06-29 2008-01-03 Peter Hazucha Integrated inductor
US7378733B1 (en) * 2006-08-29 2008-05-27 Xilinx, Inc. Composite flip-chip package with encased components and method of fabricating same
US20080169896A1 (en) * 2007-01-11 2008-07-17 Fuji Electric Device Technology Co., Ltd. Microminiature power converter
US7435619B2 (en) * 2006-02-14 2008-10-14 Stats Chippac Ltd. Method of fabricating a 3-D package stacking system
US7667320B2 (en) * 2004-04-26 2010-02-23 Intel Corporation Integrated circuit package with improved power signal connection

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100243991B1 (en) 1995-08-29 2000-02-01 히로스케 다카후지 Height-adjustable folding chair
US6809421B1 (en) * 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
WO2004089049A1 (en) * 2003-03-28 2004-10-14 Tdk Corporation Multilayer substrate and method for producing same
JP4202902B2 (en) * 2003-12-24 2008-12-24 太陽誘電株式会社 Designing method of a multilayer substrate, a plurality of types of laminated substrate, and co-sintered multilayer substrate
JP4865197B2 (en) * 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US20060071650A1 (en) * 2004-09-30 2006-04-06 Narendra Siva G CPU power delivery system
US7449381B2 (en) * 2005-07-05 2008-11-11 Endicott Interconect Technologies, Inc. Method of making a capacitive substrate for use as part of a larger circuitized substrate, method of making said circuitized substrate and method of making an information handling system including said circuitized substrate
US7807505B2 (en) * 2005-08-30 2010-10-05 Micron Technology, Inc. Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods
US7742314B2 (en) * 2005-09-01 2010-06-22 Ngk Spark Plug Co., Ltd. Wiring board and capacitor
US7843302B2 (en) * 2006-05-08 2010-11-30 Ibiden Co., Ltd. Inductor and electric power supply using it
US7685441B2 (en) * 2006-05-12 2010-03-23 Intel Corporation Power control unit with digitally supplied system parameters
WO2008084841A1 (en) * 2007-01-11 2008-07-17 Nec Corporation Semiconductor device
US7872356B2 (en) * 2007-05-16 2011-01-18 Qualcomm Incorporated Die stacking system and method
US8222079B2 (en) * 2007-09-28 2012-07-17 International Business Machines Corporation Semiconductor device and method of making semiconductor device
US8270137B2 (en) * 2007-10-15 2012-09-18 International Rectifier Corporation Interposer for an integrated DC-DC converter
US7952160B2 (en) * 2007-12-31 2011-05-31 Intel Corporation Packaged voltage regulator and inductor array
US8582333B2 (en) * 2008-06-30 2013-11-12 Intel Corporation Integration of switched capacitor networks for power delivery
US8723302B2 (en) * 2008-12-11 2014-05-13 Stats Chippac Ltd. Integrated circuit package system with input/output expansion
US20110050334A1 (en) * 2009-09-02 2011-03-03 Qualcomm Incorporated Integrated Voltage Regulator with Embedded Passive Device(s)
US9048112B2 (en) * 2010-06-29 2015-06-02 Qualcomm Incorporated Integrated voltage regulator with embedded passive device(s) for a stacked IC

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6777818B2 (en) * 2001-10-24 2004-08-17 Intel Corporation Mechanical support system for a thin package
US6930381B1 (en) * 2002-04-12 2005-08-16 Apple Computer, Inc. Wire bonding method and apparatus for integrated circuit
US7667320B2 (en) * 2004-04-26 2010-02-23 Intel Corporation Integrated circuit package with improved power signal connection
US20060071649A1 (en) * 2004-09-30 2006-04-06 Gerhard Schrom Apparatus and method for multi-phase transformers
US20070013080A1 (en) * 2005-06-29 2007-01-18 Intel Corporation Voltage regulators and systems containing same
US20070114651A1 (en) * 2005-10-29 2007-05-24 Stats Chippac Ltd. Integrated circuit stacking system with integrated passive components
US7435619B2 (en) * 2006-02-14 2008-10-14 Stats Chippac Ltd. Method of fabricating a 3-D package stacking system
US20080001698A1 (en) * 2006-06-29 2008-01-03 Peter Hazucha Integrated inductors
US20080002380A1 (en) * 2006-06-29 2008-01-03 Peter Hazucha Integrated inductor
US7378733B1 (en) * 2006-08-29 2008-05-27 Xilinx, Inc. Composite flip-chip package with encased components and method of fabricating same
US20080169896A1 (en) * 2007-01-11 2008-07-17 Fuji Electric Device Technology Co., Ltd. Microminiature power converter

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110215863A1 (en) * 2009-09-02 2011-09-08 Qualcomm Incorporated Integrated Voltage Regulator with Embedded Passive Device(s)
US8692368B2 (en) 2009-09-02 2014-04-08 Qualcomm Incorporated Integrated voltage regulator method with embedded passive device(s)
US9999129B2 (en) * 2009-11-12 2018-06-12 Intel Corporation Microelectronic device and method of manufacturing same
US20110108947A1 (en) * 2009-11-12 2011-05-12 Guzek John S Microelectronic device and method of manufacturing same
US9349692B2 (en) 2010-06-29 2016-05-24 Qualcomm Incorporated Integrated voltage regulator with embedded passive device(s) for a stacked IC
US9048112B2 (en) 2010-06-29 2015-06-02 Qualcomm Incorporated Integrated voltage regulator with embedded passive device(s) for a stacked IC
US20140217547A1 (en) * 2012-03-29 2014-08-07 Adel A. Elsherbini Semiconductor package with air core inductor (aci) and magnetic core inductor (mci)
WO2013148932A1 (en) * 2012-03-30 2013-10-03 Advanced Micro Devices, Inc. Circuit board with integrated voltage regulator
US20130257525A1 (en) * 2012-03-30 2013-10-03 Stephen V. Kosonocky Circuit board with integrated voltage regulator
US20140268615A1 (en) * 2013-03-14 2014-09-18 Qualcomm Incorporated Two-stage power delivery architecture
US9101068B2 (en) * 2013-03-14 2015-08-04 Qualcomm Incorporated Two-stage power delivery architecture
US10039188B2 (en) 2013-03-14 2018-07-31 Qualcomm Incorporated Two-stage power delivery architecture
GB2520149A (en) * 2013-09-27 2015-05-13 Intel Corp Die package with superposer substrate for passive components
GB2520149B (en) * 2013-09-27 2018-05-16 Intel Corp Die package with superposer substrate for passive components
US10115604B2 (en) 2014-03-12 2018-10-30 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
CN104916623A (en) * 2014-03-12 2015-09-16 联发科技股份有限公司 Semiconductor package and method for fabricating base for semiconductor package
US10104764B2 (en) * 2014-03-18 2018-10-16 Texas Instruments Incorporated Electronic device package with vertically integrated capacitors
US20150271913A1 (en) * 2014-03-18 2015-09-24 Texas Instruments Deutschland Gmbh Electronic device package with vertically integrated capacitors
US20160095225A1 (en) * 2014-09-26 2016-03-31 Qualcomm Incorporated Inductor system for multi-phase power management integrated circuits
EP3257079A4 (en) * 2015-02-11 2018-11-21 Chaoyang Semiconductor Jiangyin Technology Co., Ltd. Switched power stage with integrated passive components
US20170178786A1 (en) * 2015-12-17 2017-06-22 William J. Lambert Helical plated through-hole package inductor
US10163557B2 (en) * 2015-12-17 2018-12-25 Intel Corporation Helical plated through-hole package inductor
US10096582B2 (en) 2016-07-08 2018-10-09 Cisco Technology, Inc. Enhanced power distribution to application specific integrated circuits (ASICS)

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US20120293972A1 (en) 2012-11-22 application
US20110215863A1 (en) 2011-09-08 application

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