JP5715334B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5715334B2 JP5715334B2 JP2009238499A JP2009238499A JP5715334B2 JP 5715334 B2 JP5715334 B2 JP 5715334B2 JP 2009238499 A JP2009238499 A JP 2009238499A JP 2009238499 A JP2009238499 A JP 2009238499A JP 5715334 B2 JP5715334 B2 JP 5715334B2
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- wiring
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- interposer
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- semiconductor device
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
以下に、図面を参照しつつ、本発明の第1の実施形態について説明する。
続いて、本発明の第2の実施形態について説明する。
続いて、本発明の第3の実施形態について説明する。
2 第1チップ
3 第2チップ群
4 封止体
5 外形保持部材
6 第1インターポーザ
7 第2インターポーザ
8 外部電極
9 第1チップ第2配線
10 第1チップ第1配線
11 配線
12 第2チップ外部配線
13 第2チップ外部接続配線
14 貫通ヴィア
15 貫通電極
16 第2チップ貫通配線
17 支持体
19 チップ積層体
20 凹部
21 回路形成面
22 導体層
23 導体層
24 搭載部品
25 電極
Claims (13)
- 回路素子が形成された第1主面と、前記第1主面とは反対側の第2主面と、前記回路素子に電気的に接続され前記第1主面から前記第2主面を貫通する第1貫通電極とを含む第1半導体チップと、
前記第1半導体チップの前記第1主面と接する表面と、前記表面とは反対側で第1外部電極および第2外部電極が配置された裏面とを含む第1インターポーザと、
第3主面と前記第3主面とは反対側の第4主面を有し、前記第3主面と前記第4主面を貫通する第1貫通配線とを含む第2半導体チップと、
前記第1半導体チップの前記第1主面と前記第2半導体チップの前記第3主面との間に配置され、一端が前記第1主面上の前記回路素子へ電気的に接続され、他端が前記第3主面より露出した前記第1貫通配線へ電気的に接続された貫通ヴィアを含む第2インターポーザと
を具備し、
前記第1インターポーザは、前記表面上に前記第1半導体チップが設置された第1領域と、前記第1領域以外の第2領域とを有し、前記第2領域において前記第2インターポーザと接触し、一端が前記第1貫通電極を介して前記第1主面の前記回路素子へ電気的に接続され、他端が前記第1外部電極に電気的に接続された第1の配線と、一端が前記第2外部電極と電気的に接続され、他端が前記第2領域に露出する第2の配線とを含み、
前記第2インターポーザは、一端が前記第1半導体チップの前記第1主面上の前記回路素子へ電気的に接続され、他端が前記第2領域に露出する前記第2配線と機械的および電気的に接続された第3配線を含み、
前記第2インターポーザの前記第3の配線は、断面視において前記貫通ヴィアより前記第2インターポーザの外周側に配置され、
前記第1インターポーザの前記第2の配線は、断面視において前記第1の配線より前記第1インターポーザの外周側に配置された
半導体装置。 - 請求項1に記載された半導体装置であって、
前記第2インターポーザは、有機絶縁体層の内部および表面に、金属配線および金属ヴィアを用いて配線を形成した
半導体装置。 - 請求項1または請求項2に記載された半導体装置であって、
前記第2半導体チップは、前記第3主面と前記第4主面を貫通する第2貫通配線を含み、
前記第1インターポーザは、裏面に配置された第3外部電極と、一端が前記第3外部電極と電気的に接続され、他端が前記第2領域に露出する第4の配線を含み、
前記第2インターポーザは、一端が前記第3主面より露出した前記第2貫通配線へ電気的に接続され、他端が前記第2領域より露出した前記第4の配線へ電気的に接続された第5の配線を含む
半導体装置。 - 請求項1乃至請求項3の何れかに記載された半導体装置であって、
前記第2インターポーザの前記第3配線は、前記第1半導体チップの前記第1主面に設置された前記回路素子の信号端子へ電気的に接続され、
前記第1インターポーザの前記第1の配線は、前記第1半導体チップの前記第1主面に設置された前記回路素子の電源端子に接続されている
半導体装置。 - 請求項1乃至請求項4の何れかに記載された半導体装置であって、
第5主面と前記第5主面とは反対側の第6主面を有し、前記第5主面と前記第6主面を貫通する第3貫通配線とを含む第3半導体チップを備え、
前記第5主面に露出した前記第3貫通配線と前記第4主面に露出した前記第1貫通配線が電気的に接続されている
半導体装置。 - 請求項1乃至請求項5の何れかに記載された半導体装置であって、
前記第1インターポーザは、断面視において、前記第2領域の厚みは前記第1領域の厚みより厚い
半導体装置。 - 請求項1乃至請求項6の何れかに記載された半導体装置であって、
前記第1インターポーザは、断面視で凹部を有する
半導体装置。 - 請求項1乃至請求項7の何れかに記載された半導体装置であって、
前記第1半導体チップには、ロジック機能を有する回路が形成されており、
前記第2半導体チップには、メモリ機能を有する回路が形成されている
半導体装置。 - 請求項5に記載された半導体装置であって、
前記第3半導体チップには、メモリ機能を有する回路が形成されている半導体装置。 - 請求項3に記載された半導体装置であって、
断面視において、前記第1外部電極が前記第1インターポーザの裏面の中央部に配置され、前記第3外部電極が前記第1インターポーザの外周部に設置され、前記第2外部電極が前記第1外部電極と前記第3外部電極の間に位置する
半導体装置。 - 請求項10に記載された半導体装置であって、
断面視において、前記第1の配線が前記第1インターポーザの中央部に配置され、前記第4の配線が前記第1インターポーザの外周部に設置され、前記第2の配線が前記第1の配線と前記第2の配線の間に位置する
半導体装置。 - 請求項3に記載された半導体装置であって、
断面視において、前記貫通ヴィアが前記第2インターポーザの中央部に配置され、前記第5の配線が前記第2インターポーザの外周部に設置され、前記第3の配線が前記貫通ヴィアと前記第5の配線の間に位置する
半導体装置。 - 請求項3に記載された半導体装置であって、
第5主面と前記第5主面とは反対側の第6主面を有し、前記第5主面と前記第6主面を貫通する第3貫通配線とを含む第3半導体チップを備え、
前記第5主面に露出した前記第3貫通配線と前記第4主面に露出した前記第1貫通配線が電気的に接続され、
前記第3半導体チップは、前記第5主面と前記第6主面を貫通する第4貫通配線を備え、
前記第5主面に露出した前記第4貫通配線と前記第4主面に露出した前記第2貫通配線が電気的に接続されている
半導体装置。
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