JP4865197B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP4865197B2 JP4865197B2 JP2004194690A JP2004194690A JP4865197B2 JP 4865197 B2 JP4865197 B2 JP 4865197B2 JP 2004194690 A JP2004194690 A JP 2004194690A JP 2004194690 A JP2004194690 A JP 2004194690A JP 4865197 B2 JP4865197 B2 JP 4865197B2
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- semiconductor device
- semiconductor element
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Description
図1は、本実施形態に係る半導体装置の構成を模式的に示す断面図である。図1に示した半導体装置100は、平板状の配線体101と、配線体101の一方の面に設けられた第一の半導体素子113と、配線体101の第一の半導体素子113の設けられた側の面および第一の半導体素子113の側面を被覆する絶縁樹脂119と、配線体101の他方の面に、第二の半導体素子111に対向配置させて設けられた第二の半導体素子111と、を有する。
図1に示した半導体装置100において、配線体101は、絶縁膜107、シリコン層105および配線層103がこの順に積層された構造になっている。そして、配線層103中の導電体およびこれに接続して設けられた導体ヴィア109により構成される貫通電極が配線体101を貫通した構成となっている。また、配線体101の両面に第一の半導体素子113および第二の半導体素子111が対向して接合されている。
第一の実施形態に記載の半導体装置100(図1)は、配線層103、シリコン層105、絶縁膜107がこの順に積層された構成の配線体101を備えていたが、配線体101は、配線層103およびシリコン層105の積層体からなる構成としてもよい。図7は、本実施形態に係る半導体装置110の構成を模式的に示す断面図である。
以上の実施形態に記載の半導体装置において、配線体101が配線層103のみから構成されていてもよい。図8は、本実施形態に係る半導体装置120の構成を模式的に示す断面図である。
第一の実施形態に記載の半導体装置100において、配線体101の配線層103の側に接合された第一の半導体素子113が、複数の半導体素子の積層体であってもよい。図11は、本実施形態に係る半導体装置の構成を模式的に示す断面図である。図11に示した半導体装置の基本構成は第一の実施形態に記載の半導体装置100(図1)と同様であるが、第一の半導体素子113に代えて複数の半導体素子149が面の法線に沿って積層された構成である点が異なる。
以上の実施形態に記載の半導体装置において、配線体101の一つの面に複数の半導体素子が平面配置されていてもよい。以下、第四の実施形態に記載の半導体装置(図11)の場合を例に説明する。図13は、本実施形態に係る半導体装置の構成を模式的に示す断面図である。
以上の実施形態に記載の半導体装置において、配線体101中に設けられている導体ヴィア109を導体ワイヤとの接続部材として利用することもできる。また、配線体101の絶縁樹脂119形成面と対向する面に接着材により積層された複数の半導体素子が接続され、そのうち少なくとも1つの半導体素子が、ワイヤを介して、配線体101に電気的に接続された構成とすることができる。図14は、本実施形態に係る半導体装置の構成を模式的に示す断面図である。
図15(a)および図15(b)は、本実施形態に係る半導体装置の構成を模式的に示す断面図である。図15(a)は、図15(b)に示した半導体装置のボンディング前の状態を示す図である。図15(a)に示した半導体装置は、第三の実施形態に記載の配線層103からなる配線体101の一方の面に第一の半導体素子113が接合され、他方の面に第二の半導体素子111が配設された構成を有する。第一の半導体素子113は、配線体101上を覆う絶縁樹脂119中に埋設されている。なお、絶縁樹脂119を貫通する導体スルーホール121および導体スルーホール121に接続する電極端子123は、図15(a)においては設けられていない。
図17(a)および図17(b)は、本実施形態に係る半導体装置の構成を模式的に示す断面図である。図17(a)に示した半導体装置は、配線層103からなる平板状の配線体と、配線層103の一方の面に設けられた第一の半導体素子と、一方の面および第一の半導体素子の側面を被覆する絶縁樹脂119と、絶縁樹脂119を貫通する導体スルーホール121と、配線層103の他方の面に設けられた第二の半導体素子111と、を有する。
101 配線体
103 配線層
105 シリコン層
107 絶縁膜
109 導体ヴィア
110 半導体装置
111 半導体素子
113 半導体素子
115 電極
117 電極
119 絶縁樹脂
120 半導体装置
121 導体スルーホール
123 電極端子
125 アンダーフィル樹脂
127 アンダーフィル樹脂
129 基板
131 導体ポスト
133 シリコン基板
135 絶縁樹脂
137 シード層
139 接続電極
141 絶縁樹脂膜
143 開口部
145 ヴィアプラグ
147 配線
149 半導体素子
150 半導体装置
151 導体スルーホール
153 接着剤
155 ワイヤ
157 導体パッド
159 導体パッド
161 サポートリング
163 テープ基板
165 配線層
167 インナーリード封止樹脂
169 インナーリード
171 ヒートスプレッダ
173 配線基板
175 パッド
177 樹脂止めパターン
179 メモリ通信用電極
181 メモリ電極
183 外部入出力用電極
185 半導体装置
187 半導体装置
Claims (29)
- 平板状の配線体と、
前記配線体の一方の面に設けられた第一の半導体素子と、
前記一方の面の全面および前記第一の半導体素子の側面を被覆する封止樹脂と、
前記封止樹脂により被覆された後の前記配線体に接続され、前記配線体の他方の面に前記第一の半導体素子に対して少なくとも一部が対向する位置に設けられた第二の半導体素子と、を有し、
前記配線体は、
前記一方の面側に設けられ、前記第一の半導体素子と接続しており、前記配線体から露出した全面が前記封止樹脂によって被覆されている配線層と、
前記配線層の前記第一の半導体素子が接続されていない側に積層され、前記配線層を支持する支持層と、
前記支持層を貫通し、前記配線層と接続している貫通電極と、を備え、
前記配線体を介して前記第一の半導体素子と前記第二の半導体素子とが電気的に接続されており、
前記第二の半導体素子は前記他方の面に電極を介して接続されており、
前記貫通電極と前記電極とが前記配線体の面に対し、略垂直に一直線に接続され、
前記支持層がシリコン、セラミック、および珪ホウ酸ガラスからなる群から選択される一種以上の材料からなることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記支持層はシリコンからなり、
前記配線体は前記他方の面側に絶縁膜をさらに備え、
前記貫通電極は前記支持層および前記絶縁膜を貫通して設けられていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記支持層はセラミックまたは珪ホウ酸ガラスからなることを特徴とする半導体装置。 - 請求項1乃至3いずれか1項に記載の半導体装置において、
前記貫通電極は、前記配線層を貫通することを特徴とする半導体装置。 - 請求項1乃至4いずれか1項に記載の半導体装置において、
平面視で前記第一の半導体素子と前記第二の半導体素子とが重なる部分において、前記第一の半導体素子と前記第二の半導体素子とが前記貫通電極を介して電気的に接続されていることを特徴とする半導体装置。 - 請求項1乃至5いずれか1項に記載の半導体装置において、
前記第一の半導体素子は、前記配線体の前記一方の面に第一の電極を介して接続され、
前記第二の半導体素子は、前記配線体の前記他方の面に第二の電極を介して接続されており、
前記第一の電極と前記貫通電極と前記第二の電極とが、前記配線層の面に対して略垂直に一直線に接続していることを特徴とする半導体装置。 - 請求項1乃至6いずれか1項に記載の半導体装置において、
前記第一の半導体素子は、前記配線体の前記一方の面に第一の電極を介して接続され、
前記第二の半導体素子は、前記配線体の前記他方の面に第二の電極を介して接続されており、
前記第一の電極及び前記第二の電極のすべてが、平面視で前記第一の半導体素子の内側の領域に配置されていることを特徴とする半導体装置。 - 請求項1乃至7いずれか1項に記載の半導体装置において、
前記貫通電極は、格子状に平面配置されていることを特徴とする半導体装置。 - 請求項8に記載の半導体装置において、
前記貫通電極は、正方格子状に平面配置されていることを特徴とする半導体装置。 - 請求項8に記載の半導体装置において、
前記貫通電極は、斜格子状に平面配置されていることを特徴とする半導体装置。 - 請求項1乃至10いずれか1項に記載の半導体装置において、
前記支持層は、能動素子が形成されたシリコン層であることを特徴とする半導体装置。 - 請求項1乃至11いずれか1項に記載の半導体装置において、
前記配線体は、絶縁膜と、前記支持層と、前記配線層とがこの順に積層された構成を有し、前記第一の半導体素子が前記配線層に接続され、前記第二の半導体素子が前記絶縁膜側に接続されていることを特徴とする半導体装置。 - 請求項1乃至12いずれか1項に記載の半導体装置において、
前記封止樹脂を貫通する貫通プラグを備えることを特徴とする半導体装置。 - 請求項1乃至13いずれか1項に記載の半導体装置において、
前記配線層が多層配線層であることを特徴とする半導体装置。 - 請求項1乃至14いずれか1項に記載の半導体装置において、
前記第一の半導体素子が前記封止樹脂に埋設されていることを特徴とする半導体装置。 - 請求項1乃至15いずれか1項に記載の半導体装置において、前記貫通電極は、前記配線体の前記他方の面に対し凸状に張り出していることを特徴とする半導体装置。
- 請求項1乃至16いずれか1項に記載の半導体装置において、前記貫通電極は、複数の導電体を積層して形成されていることを特徴とする半導体装置。
- 基板上に形成された支持層を貫通する導体ヴィアを形成する工程と、
前記基板上に前記導体ヴィアと接続し、前記支持層により支持される配線層を形成する工程と、
前記配線層と第一の半導体素子とを接続させる工程と、
前記配線層の前記配線体から露出した全面および前記第一の半導体素子の側面を封止樹脂により被覆する工程と、
前記基板の前記配線層の形成面の裏面から前記基板を薄化する工程と、
前記基板を薄化する前記工程の後に前記配線層を介して第二の半導体素子の少なくとも一部を前記第一の半導体素子に対向させ、前記導体ヴィアを介して前記第一の半導体素子と前記第二の半導体素子とを電気的に接続する工程と、
を含み、
前記配線層の表面および前記第一の半導体素子の側面を封止樹脂により被覆する前記工程は、前記基板上に形成された前記配線層の表面の全面を前記封止樹脂により覆う工程を含み、
前記第一の半導体素子と前記第二の半導体素子とを電気的に接続する前記工程において、前記支持層側の表面に露出させた前記導体ヴィアに電極を介して前記第二の半導体素子を接続し、前記導体ヴィアと前記電極とを前記配線層の面に対し、略垂直に一直線に接続させ、
前記支持層がシリコン、セラミック、および珪ホウ酸ガラスからなる群から選択される一種以上の材料からなることを特徴とする半導体装置の製造方法。 - 請求項18に記載の半導体装置の製造方法において、
導体ヴィアを形成する前記工程は、シリコンからなる前記支持層との間に絶縁層が形成された前記基板の前記絶縁層及び前記支持層に前記導体ヴィアを貫通させることを特徴とする半導体装置の製造方法。 - 請求項18に記載の半導体装置の製造方法において、
導体ヴィアを形成する前記工程は、セラミックまたは珪ホウ酸ガラスからなる前記支持層に前記導体ヴィアを貫通させることを特徴とする半導体装置の製造方法。 - 請求項18乃至20いずれか1項に記載の半導体装置の製造方法において、
前記第一の半導体素子と前記第二の半導体素子とを電気的に接続する前記工程は、平面視で前記第一の半導体素子と前記第二の半導体素子とが重なる部分において、前記導体ヴィアを介して前記第一の半導体素子と前記第二の半導体素子とを電気的に接続させる工程を含むことを特徴とする半導体装置の製造方法。 - 請求項18乃至21いずれか1項に記載の半導体装置の製造方法において、
前記第一の半導体素子と前記第二の半導体素子とを電気的に接続する前記工程は、前記第一の半導体素子を前記配線層の一方の面に第一の電極を介して接続し、前記第二の半導体素子を前記配線層の他方の面に第二の電極を介して接続し、前記第一の電極と前記導体ヴィアと前記第二の電極とを前記配線層の面に対して略垂直に一直線に接続させる工程を含むことを特徴とする半導体装置の製造方法。 - 請求項18乃至22いずれか1項に記載の半導体装置の製造方法において、
基板を薄化する前記工程は、前記基板を除去し、前記導体ヴィアの表面を露出させる工程を含むことを特徴とする半導体装置の製造方法。 - 請求項18乃至23いずれか1項に記載の半導体装置の製造方法において、
配線層を形成する前記工程は、
表面に絶縁膜と前記配線層を支持する支持層とがこの順に積層された前記基板を準備する工程と、
前記支持層上に前記配線層を設ける工程と、
を含むことを特徴とする半導体装置の製造方法。 - 請求項18乃至24いずれか1項に記載の半導体装置の製造方法において、
前記導体ヴィアは、格子状に平面配置されていることを特徴とする半導体装置の製造方法。 - 請求項25に記載の半導体装置の製造方法において、
前記導体ヴィアは、正方格子状に平面配置されていることを特徴とする半導体装置の製造方法。 - 請求項25に記載の半導体装置の製造方法において、
前記導体ヴィアは、斜格子状に平面配置されていることを特徴とする半導体装置の製造方法。 - 請求項18乃至27いずれか1項に記載の半導体装置の製造方法において、
前記基板がシリコン基板であることを特徴とする半導体装置の製造方法。 - 請求項18乃至28いずれか1項に記載の半導体装置の製造方法において、
前記配線層の表面および前記第一の半導体素子の側面を封止樹脂により被覆する前記工程は、
前記配線層の表面の全面を前記封止樹脂により封止することにより前記第一の半導体素子を埋設する工程と、
前記第一の半導体素子を埋設する前記工程の後に、前記封止樹脂を薄化して前記第一の半導体素子の表面を露出させる工程と、
を含むことを特徴とする半導体装置の製造方法。
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US10991673B2 (en) | 2018-01-04 | 2021-04-27 | Kabushiki Kaisha Toshiba | Electronic device |
US11791311B2 (en) | 2018-01-04 | 2023-10-17 | Nagase & Co., Ltd. | Electronic device |
KR20200031322A (ko) | 2018-09-14 | 2020-03-24 | 삼성전기주식회사 | 전자 소자 모듈 및 그 제조 방법 |
US10820456B2 (en) | 2018-09-14 | 2020-10-27 | Samsung EIectro-Mechanics Co., Ltd. | Electronic component module and manufacturing method thereof |
US11337346B2 (en) | 2018-09-14 | 2022-05-17 | Samsung Electro-Mechanics Co., Ltd. | Electronic component module and manufacturing method thereof |
Also Published As
Publication number | Publication date |
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US20060063312A1 (en) | 2006-03-23 |
US8541874B2 (en) | 2013-09-24 |
US9324699B2 (en) | 2016-04-26 |
US8193033B2 (en) | 2012-06-05 |
US20160204092A1 (en) | 2016-07-14 |
US20100314749A1 (en) | 2010-12-16 |
US8207605B2 (en) | 2012-06-26 |
US20130334705A1 (en) | 2013-12-19 |
US7795721B2 (en) | 2010-09-14 |
JP2006019433A (ja) | 2006-01-19 |
US8890305B2 (en) | 2014-11-18 |
US20190229104A1 (en) | 2019-07-25 |
US20080265434A1 (en) | 2008-10-30 |
US20120248620A1 (en) | 2012-10-04 |
US10672750B2 (en) | 2020-06-02 |
US20150041978A1 (en) | 2015-02-12 |
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