JP5143451B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP5143451B2 JP5143451B2 JP2007066408A JP2007066408A JP5143451B2 JP 5143451 B2 JP5143451 B2 JP 5143451B2 JP 2007066408 A JP2007066408 A JP 2007066408A JP 2007066408 A JP2007066408 A JP 2007066408A JP 5143451 B2 JP5143451 B2 JP 5143451B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 200
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 229920005989 resin Polymers 0.000 claims abstract description 42
- 239000011347 resin Substances 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000010410 layer Substances 0.000 claims description 64
- 239000011241 protective layer Substances 0.000 claims description 15
- 230000002950 deficient Effects 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 235000019589 hardness Nutrition 0.000 claims description 9
- 238000007689 inspection Methods 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 3
- 238000000926 separation method Methods 0.000 abstract 1
- 230000035882 stress Effects 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 239000003518 caustics Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004132 cross linking Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L22/10—Measuring as part of the manufacturing process
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L23/3135—Double encapsulation or coating and encapsulation
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- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
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- H01L2224/05573—Single external layer
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- H01L2224/061—Disposition
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- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
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- H01L2224/13001—Core members of the bump connector
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- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
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- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Description
4b 第2の半導体チップ 4c 第3の半導体チップ 5 デバイス素子
6 貫通孔 7 貫通電極 8 導電端子 10 保護層
11 第1の樹脂層 12 第2の樹脂層 13 導電端子
20 半導体装置 21 配線層 22 第2の半導体チップ
23 貫通電極 24 導電端子 25 ダミーチップ
26 第3の半導体チップ 27 貫通電極 28 導電端子
30 半導体装置 31 配線チップ 32 貫通電極 33 導電端子
34 半導体チップ 40 半導体装置 100 半導体装置
101 第1の半導体チップ 102 第2の半導体チップ
103 第3の半導体チップ 104 半導体基板 105 デバイス素子
106 貫通孔 107 貫通電極 108 導電端子 109 半導体基板
Claims (4)
- 配線層を備えるベース基板と、
前記ベース基板上に積層され、前記配線層と電気的に接続された複数のチップと、
硬度が異なる複数の樹脂層を含んで前記複数のチップを被覆する保護層とを備え、
前記複数のチップは、第1のチップと、前記第1のチップの直上に配置された第2のチップとを少なくとも含み、
前記第1のチップと前記第2のチップの少なくともいずれか一方のチップの側面の一部が、他方のチップの側面よりも内側に配置され、
前記一方のチップと前記他方のチップとが重畳しない領域に、前記一方のチップに隣接する第3のチップを備え、
前記第1のチップ及び前記第2のチップは、それぞれ、その表面から裏面にかけて貫通する貫通孔と、前記貫通孔内に形成された貫通電極とを有し、
前記第1のチップの表面には、パターニングされた金属層からなり前記第1のチップの前記貫通電極及び前記第2のチップの前記貫通電極と電気的に接続された金属配線層が配置されることを特徴とする半導体装置。 - 前記第3のチップの直上に配置される第4のチップとを備え、
前記第3のチップは、前記第4のチップと前記配線層との電気的な接続を介在する導電層を備えることを特徴とする請求項1に記載の半導体装置。 - 前記第3のチップの側面と前記他方のチップの側面とが実質的に同一直線状に配置されていることを特徴とする請求項1または請求項2に記載の半導体装置。
- チップの検査工程と、
前記検査工程で良品と判定されたチップを用いて、ウェハ状のベース基板上に前記チップを複数個積層する工程と、
前記積層されたチップを被覆する第1の樹脂層を形成する工程と、
前記第1の樹脂層と硬度が異なり、前記第1の樹脂層を被覆する第2の樹脂層を形成する工程と、
所定のラインに沿って前記ベース基板を切削する工程とを有し、
前記積層されたチップは、第1のチップと、前記第1のチップの直上に配置された第2のチップとを少なくとも含み、
前記第1のチップ及び前記第2のチップは、それぞれ、その表面から裏面にかけて貫通する貫通孔と、前記貫通孔内に形成された貫通電極とを有し、前記第1のチップの表面には、パターニングされた金属層からなり前記第1のチップの前記貫通電極及び前記第2のチップの前記貫通電極と電気的に接続された金属配線層が配置され、
前記第1のチップと前記第2のチップの少なくともいずれか一方のチップの側面の一部を、他方のチップの側面よりも内側に配置し、前記一方のチップと前記他方のチップとが重畳しない領域に、前記一方のチップに隣接した第3のチップを配置する工程を有することを特徴とする半導体装置の製造方法。
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US12/048,861 US8373278B2 (en) | 2007-03-15 | 2008-03-14 | Semiconductor device having stacked dice disposed on base substrate |
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