JP5609144B2 - 半導体装置および貫通電極のテスト方法 - Google Patents
半導体装置および貫通電極のテスト方法 Download PDFInfo
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- JP5609144B2 JP5609144B2 JP2010035350A JP2010035350A JP5609144B2 JP 5609144 B2 JP5609144 B2 JP 5609144B2 JP 2010035350 A JP2010035350 A JP 2010035350A JP 2010035350 A JP2010035350 A JP 2010035350A JP 5609144 B2 JP5609144 B2 JP 5609144B2
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
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Description
貫通電極は、その名の通り半導体基板を厚さ方向に貫くものであるが、その使用形態としては、集積回路の端子を、それが形成された基板面と反対の側(いわゆる裏面側)に引き出すためのものである。あるいは、TSV(スルーシリコンビア)と呼ばれ、電源電圧や他の電圧を上層チップに送るための貫通電極もある。そのうち、数的に多いのが半導体集積回路の端子を裏面から取り出すための貫通電極である。
1.電極位置を示す平面および断面の半導体装置構造。
2.形成方法の例。
3.テストを含む実装工程。
図1は、本発明の実施形態に関わる半導体装置の概念的な断面及び平面図である。
図1に示すように、“半導体基板”としてのシリコン基板1の第1主面側(いわゆる表面側)に集積回路2が形成されている。この一方面側とは、図1では下方側である。
そのため、表面(図の下面)側に集積回路2を形成した後、表面にサポート材として例えば支持基板100が貼られている。図1は、支持基板100をひっくり返してシリコン基板1の他方面(裏面)を上方に位置させたときの断面図と裏面平面図である。
一方、貫通電極3の上面に接するようにシリコン基板1の裏面に電極接続配線4が形成されている。この電極接続配線4は、裏面側からのウェハプロセスにおける配線形成技術で形成される。
絶縁膜5はマイクロバンプ(μBump)電極10の形成箇所と、テストパッド電極の形成箇所が開口している。マイクロバンプ電極10は、本発明の“バンプ電極”の一形態である。
同じ面側にあればマイクロバンプ電極10とテストパッド電極11との相対位置関係は、図示のものには限らず任意である。
また、プローブの押当によるダメージが入りにくいのであれば、貫通電極3が下面で接触する箇所の上面を含む箇所にテストパッド電極11の位置を規定してもよい。
さらに、図1ではマイクロバンプ電極10が形成された状態を示すが、テスト自体は貫通電極3の導通テスト(オープン、ショート不良のテスト)であるため、このテストをマイクロバンプ電極10の形成前に行うこともできる。その場合、マイクロバンプ電極10の形成箇所を含むようにテストパッド電極11の開口を形成してよい。
また、電極接続配線4を覆う絶縁膜5の開口でテストパッド電極11の範囲を規定する必要もない。絶縁膜5がテストプローブの接触に必要な箇所をもっていれば、マイクロバンプでは、そのような広い箇所は裏面配線にないのが普通であるから、そのような広い面積箇所をもってテストパッド領域とみなしてよい。
通常の裏面メタルは、貫通電極3とマイクロバンプ電極10の位置をずらすためだけに用いられるため、図1のような広い箇所(本発明が非適用な場合は無駄な領域となるメタル部分)は形成しない。このことから、電極接続配線4の大きさや平面形状で本発明の適用と非適用が峻別できる。
このように大きな製造コストの増加なしに本発明の電極構造が形成可能である。
図3は、断面で示す工程フロー図である。フロー図には、裏面貫通電極付近の拡大図が用いられている。
まず、図3(a)は、貫通電極3が裏面に現れるところまで形成された状態を示す。シリコン基板1に深い孔を表面加工時に形成し、その内部に薄い絶縁膜を被膜し、内部を導電材料で埋め込む。図3(a)は、支持基板100で支持された状態で裏面から基板をCMP等で削ってこのプラグの底を頭出しした状態を示す。裏面全域にも薄い絶縁膜が被膜しされているために貫通電極3の上面だけが露出している。これより前段階の工程フローは図示を省略している。
次の図3(c)は、貫通電極3からマイクロバンプ電極10の接続部、テストパッド電極11となるテストパッド部を形成するようにパッド用メタル配線を加工し、図1の電極接続配線4を形成した状態を示す。
このように裏面のテストパッド電極11の数(および位置、さらには大きさ)を、表面の他のテストで用いられるテストパッド電極と合わせるのは、表面と裏面とも共通のプローブカードを使用可能とするためである。プローブカードは調整コスト等が高く高価であり、消耗するため、このように表裏面でプローブカードを共通化できることは大きなコスト削減につながる。
テストパッド電極11の位置を合わせることを優先した場合に、テストに用いられることがない裏面と表面の片側だけにしか用いられないテストパッド電極11(ダミー電極)が発生することは許される。このようなテストパッド電極11は、使用しないテストから見ると無駄なダミーパッドである。ただし、テストパッド電極11を仮になくしても、そこは元々配線がない場所であるため無駄が生じているとは言えない。さらに、テストパッド電極11は、一括プロセスで形成されるため製造コスト増も発生しない。むしろ、上記したプローブカードの経費削減効果が大きく全体としては大幅なコスト削減ができる。
さらに、特に図示しないが、裏面ウェハテストを行う際に、テスト用アライメントマークが必要であり、これをマスク作成時に組み込んでおくようにしてもよい。
なお、半導体基板に複数の貫通電極が設けられている場合、その全ての貫通電極が、その両端に少なくとも1つのテストパッドが接続されていることが望ましい。
図4にテストを含む実装工程のフローを、適宜断面を含めた図により示す。
図4(A)は、ウェハ完成後の断面を示す。この図では上面が表面側(第1主面側)であり、その表面側に集積回路が形成され、集積回路の下(裏面)側に基板ボディ領域が存在する。ウェハプロセス途中では簡単なDCテストやプロセスチェックを行うが、その工程は図示を省略している。
但し、全ての貫通電極3に対して接続不良が検出できるとは限らない。ここでのテストは基本的に集積回路2を介したテストであるため、非動作時の回路でも電気的に導通チェックができる回路内経路を含む貫通電極3同士のテストとなる。あるいは、電極接続配線4に複数の貫通電極3が接続されていれば、電極接続配線4を通したテストも可能である。その場合、集積回路2と貫通電極3の接続不良は検出できない。
一方、図4(D)の発明によって導入可能となるテストを行わないと(図5参照)、製造コストが跳ね上がる自体の可能性もゼロではない。このことについては、次に、比較例を示して説明する。
<4.比較例>
図5では、図4(D)が存在しない。図2のようにテストパッド電極11を有しないと裏面テストは不可能である。
図5(B)のウェハテストからのファイナルテスト(図5(G))まで接続不良は顕在化しないで最終形状まで組み立てられる。その場合、たった1つの接続不良があるだけで、図5(F)に示す完成品が破棄され、大きな歩留まり低下が発生する可能性がある(図5(G))。
よって、このテスト情報はウェハ面内分布等の情報が抽出でき、その情報が歩留まり改善に寄与し、なによりも製造コスト(原材料および人的コスト)の大幅な上昇を防止することが可能となる。
(1)半導体基板1の第1主面側に集積回路2を形成し回路テスト(ウェハテスト)を行う。
(2)その後、当該第1主面側に支持基板100を貼って第2主面側から半導体基板1に前記集積回路2と電気的に接続される複数の貫通電極3を形成する。
(3)各貫通電極3に電極接続配線4を介して電気的に接続されるテストパッド電極11を前記第2主面側に複数形成する。
(4)この状態で貫通電極のテストを行う。具体的には、形成した複数のテストパッド電極間を、テスタプローブと接触させて電極間配線、貫通電極、集積回路、他の貫通電極、他の電極間配線を経由した経路に電流を流す。これにより、通電極と集積回路、および、貫通電極と電極間配線の導通テストが可能となる。
Claims (9)
- 半導体基板と、
前記半導体基板の第1主面側に形成された集積回路と、
前記半導体基板の第1主面側に形成され、前記集積回路の良否をテストするための複数の第1テストパッド電極と、
前記半導体基板の第1主面と第2主面との間を貫通して一端が前記集積回路と電気的に接続された複数の貫通電極と、
前記半導体基板の第2主面側に形成され、それぞれが、対応する貫通電極の他端と電気的に接続された複数のバンプ電極と、
前記半導体基板の第2主面側に形成され、それぞれが、対応する貫通電極とバンプ電極に電気的に接続され、前記複数の第1テストパッド電極を用いたテストにより良品と判断された集積回路に対し、貫通電極を介してテストを行うことによって、当該貫通電極の接続状態をテストするための複数の第2テストパッド電極と、
を有する半導体装置。 - 前記第1主面側からみた前記複数の第1テストパッド電極の数および位置が、前記第2主面側からみた前記複数の第2テストパッド電極の数および位置と同じである、
請求項1記載の半導体装置。 - 互いに電気的に接続された前記バンプ電極と前記第2テストパッド電極は、前記第2主面側からみて異なる位置に配置されている、
請求項1または2に記載の半導体装置。 - 前記複数の貫通電極の各々と電気的接続がとられる複数の電極接続配線を有し、
前記複数の電極接続配線の各々は、前記貫通電極と接続された面と厚さ方向に対向する他面に前記バンプ電極と前記第2テストパッド電極が形成されている、
請求項1または2に記載の半導体装置。 - 互いに電気的に接続された前記バンプ電極と前記第2テストパッド電極は、前記電極接続配線の前記他面において異なる位置に形成されている、
請求項4に記載の半導体装置。 - 前記電極接続配線は前記第2テストパッド電極より幅が広い配線層であり、
前記第2テストパッド電極は、前記電極接続配線の一部を開口する保護膜の開口によって大きさが規定されている、
請求項5に記載の半導体装置。 - 前記半導体基板の第1主面側の複数の第1テストパッド電極は、その一部の第1テストパッド電極が前記集積回路に接続されないためテストには使用されないダミー電極である、
請求項1から6の何れか一項に記載の半導体装置。 - 半導体基板の第1主面側に、集積回路と、当該集積回路に接続された複数の第1テストパッド電極とを形成する工程と、
前記複数の第1テストパッド電極から前記集積回路の良否をテストする第1のテスト工程と、
前記半導体基板の第1主面側に支持基板を貼って、第2主面側から前記半導体基板に前記集積回路と電気的に接続される複数の貫通電極を形成する工程と、
各貫通電極に電極接続配線を介して電気的に接続される複数の第2テストパッド電極を前記半導体基板の第2主面側に形成する工程と、
前記第1のテスト工程で前記複数の第1テストパッド電極を用いたテストにより良品と判断された集積回路に対し、前記複数の第2テストパッド電極から複数の貫通電極を介してテストを行うことによって、当該複数の貫通電極の接続状態をテストする第2のテスト工程と、
を有する貫通電極のテスト方法。 - 前記複数の第1テストパッド電極と前記複数の第2テストパッド電極を、前記第1主面側からみた前記複数の第1テストパッド電極の数および位置が前記第2主面側からみた前記複数の第2テストパッド電極の数および位置と同じになるように形成し、
前記第1のテスト工程と前記第2のテスト工程では、同じプローブカードを用いてテストを行う、
請求項8に記載の貫通電極のテスト方法。
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2010
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- 2010-12-15 US US12/926,879 patent/US8691601B2/en not_active Expired - Fee Related
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2011
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US11127713B2 (en) | 2019-12-20 | 2021-09-21 | Samsung Electronics Co., Ltd. | High bandwidth memories and systems including the same |
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CN102169870A (zh) | 2011-08-31 |
US8691601B2 (en) | 2014-04-08 |
US20110204357A1 (en) | 2011-08-25 |
JP2011171607A (ja) | 2011-09-01 |
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