JP4345798B2 - 積層型半導体装置及びそのテスト方法 - Google Patents
積層型半導体装置及びそのテスト方法 Download PDFInfo
- Publication number
- JP4345798B2 JP4345798B2 JP2006279131A JP2006279131A JP4345798B2 JP 4345798 B2 JP4345798 B2 JP 4345798B2 JP 2006279131 A JP2006279131 A JP 2006279131A JP 2006279131 A JP2006279131 A JP 2006279131A JP 4345798 B2 JP4345798 B2 JP 4345798B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- semiconductor device
- test
- stacked semiconductor
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
- G01R31/318513—Test of Multi-Chip-Moduls
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5006—Current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
11 半導体基板の主面
12 半導体基板の裏面
13 貫通電極
14 チップ間接合部
15 絶縁膜
16a,16b 配線
17a,17b コンタクト
20 積層型半導体装置
30 搭載基板
100,200,300 積層型半導体装置
101,102,103,104・・・ 内部回路
111,112,113,114・・・ 貫通電極
121,122,123,124・・・ スイッチ(第1のスイッチ)
130 測定用パッド
130a テスト配線
131,132,133,134・・・ スイッチ(第2のスイッチ)
190 制御回路
191 インバータ
290 リセット回路
291 トランジスタ
292 抵抗
293 インバータ
360 プリチャージ回路
361 NAND回路
362 トランジスタ
370 検出回路
371 ラッチ部
372 トランスファゲート
380 出力回路
390 制御回路
391 NOR回路
392 インバータ
Claims (14)
- 半導体基板に形成された内部回路と、前記半導体基板を貫通して設けられた貫通電極と、テスト配線と、前記貫通電極と前記内部回路との間に設けられた第1のスイッチと、前記貫通電極と前記テスト配線との間に設けられた第2のスイッチと、前記第1及び第2のスイッチを排他的にオンさせる制御回路とを備え、
テスト時には、前記半導体基板に基板電位が印加され、前記制御回路により前記第1のスイッチがオフとなると共に前記第2のスイッチがオンとなり、前記テスト配線に前記基板電位と異なる所定の電位が印加され、前記貫通電極と前記半導体基板との間のショートの有無が検出されることを特徴とする積層型半導体装置。 - 前記貫通電極は、信号の入力及び/又は出力を行うための信号電極であることを特徴とする請求項1に記載の積層型半導体装置。
- 前記貫通電極を複数備え、前記第1及び第2のスイッチが前記複数の貫通電極ごとに設けられていることを特徴とする請求項1又は2に記載の積層型半導体装置。
- 前記テスト配線は前記複数の貫通電極に対して共通に設けられており、これにより前記複数の第2のスイッチがオンすると前記複数の貫通電極が前記テスト配線に対して共通接続されることを特徴とする請求項3に記載の積層型半導体装置。
- 前記テスト配線に接続された測定用パッドをさらに備えることを特徴とする請求項1乃至4のいずれか一項に記載の積層型半導体装置。
- 前記制御回路は、前記測定用パッドの電位に基づいて前記第1及び第2のスイッチを排他的にオンさせることを特徴とする請求項5に記載の積層型半導体装置。
- 前記測定用パッドの電位を所定の電位に固定させる手段をさらに備えることを特徴とする請求項6に記載の積層型半導体装置。
- 半導体基板に形成された内部回路と、前記半導体基板を貫通して設けられた貫通電極と、テスト時において基板電位とは異なる所定の電位が供給されるテスト配線と、前記貫通電極と前記内部回路との間に設けられた第1のスイッチと、前記貫通電極と前記テスト配線との間に設けられた第2のスイッチと、前記第1及び第2のスイッチを排他的にオンさせる制御回路と、前記テスト配線をプリチャージするプリチャージ回路と、前記テスト配線の電位を検出する検出回路とを備えることを特徴とする積層型半導体装置。
- 前記制御回路は、前記プリチャージ回路が活性状態から非活性状態に変化した後、前記検出回路が活性化する前の少なくとも一部の期間において、前記第2のスイッチをオンさせることを特徴とする請求項8に記載の積層型半導体装置。
- 基板電位が印加された半導体基板に形成された内部回路と、前記半導体基板を貫通して設けられた貫通電極とを備える積層型半導体装置のテスト方法であって、
前記貫通電極と前記内部回路とを切断した状態で、前記貫通電極に前記基板電位とは異なる所定の電位を供給する第1のステップと、前記貫通電極に電流が流れるか否かを判断する第2のステップとを備えることを特徴とする積層型半導体装置のテスト方法。 - 前記第1のステップは、複数の貫通電極を短絡させた状態で行うことを特徴とする請求項10に記載の積層型半導体装置のテスト方法。
- 前記第1のステップは、測定用パッドを介して前記所定の電位を外部から印加することにより行うことを特徴とする請求項10又は11に記載の積層型半導体装置のテスト方法。
- 前記第2のステップは、前記測定用パッドに流れる電流を検出することにより行うことを特徴とする請求項12に記載の積層型半導体装置のテスト方法。
- 半導体基板に形成された内部回路と、前記半導体基板を貫通して設けられた貫通電極とを備える積層型半導体装置のテスト方法であって、
前記貫通電極と前記内部回路とを切断した状態で、前記貫通電極に基板電位とは異なる所定の電位を供給する第1のステップと、前記貫通電極に電流が流れるか否かを判断する第2のステップとを備え、
前記第1のステップは前記貫通電極を前記所定の電位にプリチャージすることにより行い、前記第2のステップは前記貫通電極の電位が所定量変化したか否かを検出することにより行うことを特徴とする積層型半導体装置のテスト方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006279131A JP4345798B2 (ja) | 2006-10-12 | 2006-10-12 | 積層型半導体装置及びそのテスト方法 |
US11/870,550 US8847221B2 (en) | 2006-10-12 | 2007-10-11 | Stacked semiconductor device and method of testing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006279131A JP4345798B2 (ja) | 2006-10-12 | 2006-10-12 | 積層型半導体装置及びそのテスト方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008096312A JP2008096312A (ja) | 2008-04-24 |
JP4345798B2 true JP4345798B2 (ja) | 2009-10-14 |
Family
ID=39379301
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006279131A Expired - Fee Related JP4345798B2 (ja) | 2006-10-12 | 2006-10-12 | 積層型半導体装置及びそのテスト方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8847221B2 (ja) |
JP (1) | JP4345798B2 (ja) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7750660B2 (en) * | 2006-03-30 | 2010-07-06 | Qualcomm Incorporated | Integrated circuit with improved test capability via reduced pin count |
JP2009139273A (ja) * | 2007-12-07 | 2009-06-25 | Elpida Memory Inc | 積層型半導体装置および導通テスト方法 |
WO2010097899A1 (ja) * | 2009-02-25 | 2010-09-02 | セイコーインスツル株式会社 | パッケージ製品の製造方法、圧電振動子の製造方法、発振器、電子機器および電波時計 |
US8653645B2 (en) | 2009-09-14 | 2014-02-18 | Hitachi, Ltd. | Semiconductor device comprising stacked LSI having circuit blocks connected by power supply and signal line through vias |
JP2012078332A (ja) * | 2009-10-09 | 2012-04-19 | Elpida Memory Inc | 半導体装置、半導体装置の試験方法、及びデータ処理システム。 |
JP5609144B2 (ja) | 2010-02-19 | 2014-10-22 | ソニー株式会社 | 半導体装置および貫通電極のテスト方法 |
KR101201860B1 (ko) | 2010-10-29 | 2012-11-15 | 에스케이하이닉스 주식회사 | 반도체 장치와 그 테스트 방법 및 제조방법 |
KR101218096B1 (ko) * | 2010-12-17 | 2013-01-03 | 에스케이하이닉스 주식회사 | 반도체 장치의 테스트 방법 및 반도체 장치의 테스트 시스템 |
KR101242614B1 (ko) * | 2010-12-17 | 2013-03-19 | 에스케이하이닉스 주식회사 | 반도체 집적회로 |
JP5167335B2 (ja) * | 2010-12-22 | 2013-03-21 | 株式会社日立製作所 | 半導体装置 |
US8614584B2 (en) * | 2011-03-02 | 2013-12-24 | Sandisk Technologies Inc. | System and method for bonded configuration pad continuity check |
US9322868B2 (en) | 2011-04-27 | 2016-04-26 | SK Hynix Inc. | Test circuit and method of semiconductor integrated circuit |
KR101212777B1 (ko) * | 2011-04-27 | 2012-12-14 | 에스케이하이닉스 주식회사 | 반도체 집적회로의 테스트 회로 및 방법 |
TWI455222B (zh) * | 2011-08-25 | 2014-10-01 | Chipmos Technologies Inc | 半導體元件堆疊結構測試方法 |
JP6054029B2 (ja) | 2011-12-22 | 2016-12-27 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体チップおよび半導体装置 |
KR101902938B1 (ko) * | 2012-02-14 | 2018-11-13 | 에스케이하이닉스 주식회사 | 반도체 집적회로 |
JP5980556B2 (ja) * | 2012-04-27 | 2016-08-31 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9472284B2 (en) | 2012-11-19 | 2016-10-18 | Silicon Storage Technology, Inc. | Three-dimensional flash memory system |
JP5967713B2 (ja) * | 2012-12-13 | 2016-08-10 | 国立研究開発法人産業技術総合研究所 | 積層型lsiチップの絶縁膜の検査方法及び積層型lsiチップの製造方法 |
JP6295863B2 (ja) * | 2014-07-16 | 2018-03-20 | 富士通株式会社 | 電子部品、電子装置及び電子装置の製造方法 |
CN113097180B (zh) * | 2019-12-23 | 2024-01-02 | 爱思开海力士有限公司 | 层叠式半导体器件及其测试方法 |
JP7357288B2 (ja) * | 2020-03-06 | 2023-10-06 | 本田技研工業株式会社 | 半導体装置の製造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0299877A (ja) | 1988-10-07 | 1990-04-11 | Hitachi Ltd | 集積回路部品及びその接続検査方法 |
JP2001067898A (ja) * | 1999-08-30 | 2001-03-16 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2002289623A (ja) | 2001-03-28 | 2002-10-04 | Toshiba Corp | 半導体装置及びその製造方法 |
JP4419049B2 (ja) | 2003-04-21 | 2010-02-24 | エルピーダメモリ株式会社 | メモリモジュール及びメモリシステム |
JP3896112B2 (ja) | 2003-12-25 | 2007-03-22 | エルピーダメモリ株式会社 | 半導体集積回路装置 |
JP4421957B2 (ja) | 2004-06-29 | 2010-02-24 | 日本電気株式会社 | 3次元半導体装置 |
-
2006
- 2006-10-12 JP JP2006279131A patent/JP4345798B2/ja not_active Expired - Fee Related
-
2007
- 2007-10-11 US US11/870,550 patent/US8847221B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2008096312A (ja) | 2008-04-24 |
US20080290341A1 (en) | 2008-11-27 |
US8847221B2 (en) | 2014-09-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4345798B2 (ja) | 積層型半導体装置及びそのテスト方法 | |
US5138427A (en) | Semiconductor device having a particular structure allowing for voltage stress test application | |
KR100817343B1 (ko) | 반도체 집적회로장치 | |
JP5932324B2 (ja) | 半導体装置及びその試験方法 | |
US10438681B2 (en) | Test structures and test pads in scribe lane of semiconductor integrated circuit | |
JP4103010B2 (ja) | 半導体ウエハ | |
US7107467B2 (en) | Semiconductor memory device having a circuit for removing noise from a power line of the memory device using a plurality of decoupling capactors | |
JP2020126705A (ja) | 積層型半導体装置及びその製造方法 | |
US20060176070A1 (en) | Semiconductor chip and method of testing the same | |
JP2001210098A (ja) | 半導体記憶装置及び半導体記憶装置のワード線欠陥検出方法 | |
JP2004028885A (ja) | 半導体装置、半導体パッケージ及び半導体装置の試験方法 | |
US6741510B2 (en) | Semiconductor memory device capable of performing burn-in test at high speed | |
US7701789B2 (en) | Semiconductor device | |
JP2005283432A (ja) | 半導体ウエハおよびその半導体ウエハを用いた半導体装置の製造方法 | |
US8576647B2 (en) | Semiconductor device | |
WO2014045993A1 (ja) | 半導体装置、半導体ウェハ、および半導体ウェハの試験方法 | |
JP2004152399A (ja) | 半導体記憶装置 | |
KR100520165B1 (ko) | 반도체 메모리 소자의 병렬 테스트 장치 | |
US8120976B2 (en) | Line defect detection circuit for detecting weak line | |
JP2003270302A (ja) | 半導体装置 | |
US11682465B2 (en) | Reliable through-silicon vias | |
JPH07320498A (ja) | 半導体記憶装置及び半導体記憶装置のショート検出方法 | |
JP2001168196A (ja) | 半導体装置 | |
JP2005339588A (ja) | 半導体記憶装置の検査方法と半導体記憶装置 | |
KR100195194B1 (ko) | 반도체 메모리 장치를 위한 번인스트레스회로 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080916 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20081113 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090623 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090706 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120724 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120724 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130724 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |