TWI234244B - Paired stack-gate flash cell structure and its contactless NAND-type flash memory arrays - Google Patents

Abstract

A paired stack-gate flash cell structure of the present invention comprises a pair of scalable word-line regions being formed between a pair of first interconnect source/drain regions and a scalable second interconnect source/drain region being formed between the pair of scalable word-line regions, wherein each of the pair of scalable word-line regions and the scalable second interconnect source/drain region can be made to be smaller than a minimum feature size of technology used. The paired stack-gate flash cell structure can be fabricated to have a steep floating-gate structure, a single taper-sided floating-gate structure or a double taper-sided floating-gate structure and is used to implement different contact-less NAND-type flash memory arrays with a scalable unit cell size of a string being smaller than 4F<2> and less critical masking photoresist steps.

Description

1234244 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a commonly used stacked gate flash memory cell and its flash memory array, and particularly to a paired stacked gate flash. The structure of flash cells is related to the non-contact non-connection type (NAND) flash memory array. [Previous Technology] A stack gate flash cell is often used in today's non-volatile semiconductor memory systems based on its small cell size. Generally, the stacked gate flash memory cells can form various array structures based on basic logic functions, such as non-or (N 0 R) type, non-and (NAND) type, and non-and (AND) type. For a non-OR flash memory array, the stack gate flash memory cell is usually written by the channel hot electron injection (C C EI) method, which has a large writing power and a high writing efficiency. Lower, but its read speed is faster. For a non-flash type flash memory array, the stacked gate flash memory cell system passes electrons through an isolation floating gate layer and a semiconductor by the Fuller-Nordheim (F Ν) penetration method. The writing and scrubbing are performed between the substrates, so the writing power is smaller than that of the channel hot electron injection method, but due to the serial connection of the flash memory cells of the stack gate, the reading speed is slower. The above-mentioned NOR flash memory array is suitable for storage of codes due to its fast random access speed, such as personal computer's B I 0 S, mobile phone, and digital video player (D V D). However, due to its high density, lower cost per bit, and lower power consumption,

1234244 V. Description of the invention (3) Floating gate layer; a rigorous mask photoresist step is used to form (pa 11 er η) the gate stack (WL, SSL, GSL); a rigorous mask photoresist step system 1 0 9 is used to form the common source conductive pipeline; a rigorous mask photoresist step is used to form the bit line contact hole (BC) 1 1 1; and a rigorous mask photoresist step is used to form the Metal bit line (BL) 11 2. The above detailed process steps can be found in an article published in IEEE IEDM 2000 Tech. Dig., Pp. 767, entitled "0 · 15 micron non-flash type technology has a π square micron cell size As a 1 G bit flash memory, according to Figure 1A, the unit cell size A cs of a standard non-flash memory array can be expressed as

Acs: 4 (l + 2 / n) F2 (1, where F represents a minimum line width of the technology used and ^ represents the number of flash cell cells in a stack of gates. For example, if η = 1 6 , A cs = 4 5 F2; if n = 32 'Acs = 4.25F2; and Acs = 4F2. Obviously, when η increases from 16 to 32, the reduction of the unit cell size A cs is equivalent. Slowly. Stray series resistance Rp along a string can be expressed as

Rp (l + n) Rd + nRc + 2Rsg (2) where Rd represents the resistance of a source / diffusion region; represents the channel resistance of a stacked gate flash cell; and Rsg represents an alternative

Page 9 1234244 V. Description of the invention (4) Channel resistance of the transistor. Obviously, as η increases, the stray series resistance Rp increases linearly. According to formulas (1) and (2), it can be clearly seen that when a minimum line width of the technology used is fixed, the read speed of a non-flash memory array follows a stack within a string. The number of brake cells increases more slowly. Therefore, a main object of the present invention is to provide a paired stacked gate flash cell structure of an inaccessible flash memory array. When a minimum line width of a used technology is fixed, a string of The number of flash cells in the stack gate can be increased without reducing the read speed. Another object of the present invention is to provide a flash memory cell of an incompatible flash memory array, which has a miniaturizable cell size smaller than 4F2. A further object of the present invention is to provide various floating gate structures with a high coupling ratio to form a high-density stacked gate non-type flash memory array. [Summary of the Invention] A dual-stack stacked flash cell structure of the present invention is formed on a semiconductor substrate of a first conductivity type and has a self-aligned shallow groove (ST I) structure with a high coupling ratio. At least one pair of micronizable word line regions (WL) is formed between a pair of first connection source / drain regions (ISD1) and one micronizable second connection source / drain region (I SD 2) is formed in the pair Micronizable word

1234244 V. Description of the invention (5) Between the lines (WL), wherein each of the pair of micronizable word line regions (WL) is formed on a side wall adjacent to the first connection source / drain region A first side wall dielectric spacer is defined from top to bottom including at least the first side wall dielectric cushion layer, a composite control gate conductive layer, an inter-gate dielectric layer, and a complex integration Floating gate structure, wherein each of the plurality of integrated floating gate structures includes at least one main floating gate layer formed on a penetrating dielectric layer and two extended floating gate layers formed on sides of the main floating gate layer On the wall and on a side portion adjacent to the etched back first protruding field oxide layer. Each of the above-mentioned complex integrated floating gate structures utilizes anisotropic afterglows to form a steep floating gate structure, a single taper-sided floating gate structure, or a double inclined side (double taper-sided) structure. Each of the pair of first connection source / drain regions includes at least a second conductive type multiple first connection source / drain diffusion region formed on a surface portion of the semiconductor substrate within the plurality of active regions (AA) and A first planarizing oxide layer is formed on top of it. The aforementioned scalable second connection source / drain region includes at least a plurality of second connection source / drain diffusion regions of the second conductivity type formed within the plurality of active regions XAA), a surface portion of the semiconductor substrate, and a first A two-planarized oxide layer is formed on top of it. A non-contact flash memory array of the present invention is formed on a semiconductor substrate having a first conductivity type (we 11) formed on a semiconductor substrate within a well region of a second conductivity type. A plurality of memory string regions (MS R) are alternately formed on the semiconductor substrate, and the above-mentioned plurality of memory string regions (MSR) are formed in a string selection region (SSR) and an interface.

Page 11 1234244 V. Description of the invention (6) Sitting between the GSR, the Z-a isolation zone (STI) and the complex main g = 3 = t-plates, and less complex residue groove areas (MSR) Perpendicular to each other. F, + movable £ qe becomes formed and the complex notation relies: said plurality of memory strings region (MSR) Yi string containing at least a plurality of even fast inter-stack; each to the coupling of the stack gate ^ memory A run A flash cell structure is formed, in which the above-mentioned pluralized word line area (WL) is formed at -5: one containing at least one pair of micro-controllable compound word line area (WL) ;; The area (ISD2) is formed in the pair of ^ J and at least includes a second Π ::: word line (WL) for each ... gate conductive layer, a gate-to-gate dielectric; s and, Γ = 2, Layer, the above-mentioned complex product integration drift I; Body: floating structure, where the floating gate layer is formed on the plurality of main two :: f contains less than one main drifting dielectric layer and two extensions H (ρI2 = within-a penetrating W A / No, the pre-gate layer is formed on the entire edge of the main floating gate layer and is placed on the side adjacent to the etched back first oxide field oxide layer. The pair of first connection source / drain regions ( ISD1) each includes at least a plurality of first connection source / drain diffusion regions of a first conductivity type formed on a surface portion of the semiconductor substrate and a first planarizing oxide within the plurality of motion regions (AA) A layer is formed on top of it. The aforementioned miniaturizable second connection source / drain region (ISD2) includes at least a plurality of second connection source / drain diffusion regions of the second conductivity type formed within the multiple active region (AA). A surface portion of the semiconductor substrate and a second planarized oxide layer are formed on top of it. The above-mentioned string / ground selection area (SSR / GSR) includes at least a pair of string / ground selection line areas (SSL / GSL) And a miniaturizable common sink / source region (CDR / CSR) formed between the pair of string / ground select line regions (SSL / GSL) ' Medium pair / ground

Page 12 of 1234244 V. Description of the invention (7). Each of the selected line areas (SSL / GSL) is defined by a second side wall dielectric cushion layer from top to bottom including at least one second side wall dielectric An electric cushion layer, a conductive layer of a string / ground selection line, an inter-gate dielectric layer, and a plurality of integrated floating gate structures, wherein the above-mentioned multiple integrated floating gate structure includes at least one main floating gate layer formed on the plurality of active A penetrating dielectric layer within the area (AA) and two extended floating gate layers are formed adjacent to the side edges of the etch-back first protruding field oxide layer within the parallel shallow groove isolation ST I area Share. The above-mentioned miniaturizable common drain / source region (CDR / CSR) includes at least a complex highly doped drain / source diffusion region of the second conductivity type formed in the complex common drain / source diffusion region of the first conductivity type and A pair of third side wall dielectric layers formed on the surface portion of the semiconductor substrate formed within the plurality of active regions (AA) are formed on the sides of the pair of string / ground selection line regions (SSL / GSL) An etch-back second protruding field oxide layer above the side wall and within each of the plurality of parallel shallow groove isolation regions (ST I) and the penetration within each of the plurality of active regions The dielectric layer is alternately composed on a flat surface. A common source conductive line is formed between the pair of third side wall dielectric pads and is disposed by an etch-back third protrusion within each of the plurality of parallel shallow groove isolation regions (ST I) A field oxide layer and a flat bed alternately formed by the highly doped source diffusion region within each of the plurality of active regions, and a third planarized oxide layer are formed on the pair of third side walls Dielectric pads are placed between the common source conductive lines within the miniaturizable common source region (CSR). A plurality of common-drain conductive islands are formed between the pair of third side wall dielectric pads and are disposed on the plurality of highly doped drain diffusion regions. The plurality of metal bit lines together with the plurality of collectively drained conductive islands are aligned at the same time by a mask photoresist step.

Page 13 1234244 V. Description of the invention (8) It is formed on the complex active area and is perpendicular to the complex digital line (WL) composed of the conductive layer of the complex control gate. [Embodiment] According to FIG. 1B, a plurality of memory string regions (MSR) are alternately formed on a semiconductor substrate 300, wherein each of the above-mentioned plurality of memory string regions (MSR) is formed in a string selection region (SSR). ) And a ground selection area (GSR) include at least a complex digital line area (WL) and each of the complex digital line areas (wL) is formed between the first connection source / drain area (ISD 1). FIG. 2 a (a) and FIG. 2 A (b) show a first type string / ground selection area (SSR / GSR) of the present invention including at least a pair of first connection source / drain area (ISD1), a pair of strings / A ground selection line area (SSL / GSL) is formed between the pair of first connection source / segment areas (I $ d 1), and a miniaturizable common sink / source area (CDR / CSR) is formed on the pair of string / ground Select between line areas (SSL / GSL). Each of the pair of first connection source / injection regions (Is D 丨) includes at least one second connection type first connection source / drain diffusion region 311a formed in the semiconductor substrate within a plurality of active regions (AA). A surface portion and a first planarized oxide layer 3 1 2 a are formed on top of it. Each of the pair of string / ground selection line areas (SSL / GSL) from top to bottom ^ includes a second side bile dielectric pad 3 1 6 a to define the pair of string / ground selection line areas (SSL / GSL), a string / ground selection line conductive layer 3 0 9 d / 3 0 8 d, an inter-gate dielectric layer 3 0 7 d, a complex integrated floating gate structure 3 0 2 e, and The middle part of the remaining first protruding field oxide layer (3 0 4 b) (not shown) between the integrated floating gate structure 3 0 2 e, wherein

Page 14 1234244 V. Description of the invention (9) '' Each of the above-mentioned plural integrated floating gate structures 3 0 2e includes at least one main floating gate layer 3 0 2a (not shown) formed in a penetrating dielectric Above layer 301b and two extended floating gate layers 3 0 5 a (c) (not shown) are formed on the side wall of the main floating gate layer 3 0 2 a and are placed adjacent to the first etchback field On the oxide layer 3 0 4b. The above-mentioned miniaturizable common drain / source region (CDR / CSR) includes at least one type of complex highly doped drain / source diffusion region of a second conductivity type 3 1 7b formed in a complex type of common drain / source diffusion region of a first conductivity type A surface portion of the semiconductor substrate 3 0 0 within 3 1 7a and formed within the plurality of active regions (AA), a pair of third side wall dielectric pads 3 2 0 a are formed on the pair of strings / Above the side wall of the ground selection line (SSL / GSL) and placed alternately by the penetrating dielectric layer 30 lb and the etch back second protruding field oxide layer 3 0 4c (not shown) On a flat surface, one of the common source conductive lines 3 1 9 b is formed between the pair of third side wall dielectric pads 3 1 8 a and is placed by the highly doped source diffusion region 31 7b And a flat bed alternately composed of an etch-back third protruding field oxide layer 3 0 4d (not shown) and a third planarized oxide layer 3 2 0 a are formed on the pair of third side walls A dielectric pad layer 3 1 8 a is placed on the common source conductive pipeline 3 1 9b; a plurality of common drain conductive islands 3 1 9c are alternately formed on the pair of third side wall dielectric pad layers 31 8a of And disposed within the plurality of active regions (AA) of the plurality of highly doped drain on the diffusion region 3 1 7b. FIG. 2B (a) and FIG. 2B (b) are schematic cross-sectional views of a second type string / ground selection area (SSR / GSR) according to the present invention, in which the pair of first connection source / drain areas (ISD1) Each of the integrated floating gate structures 3 2 g within each is anisotropically etched to form a beveled side structure and is located in each of the plurality of first connection source / drain diffusion regions 3 1 1 a Impurity distribution within one

Page 15 1234244 V. Description of the invention (10) Due to the relationship between the angled side wall structure, it becomes a horizontally graded change. It can be clearly seen here that Figure 2B (a) and Figure 2B (b) are the same as Figure 2A (a) and Figure 2A (b) except for the beveled side wall structure, so detailed For explanation, reference may be made to the description of FIG. 2A (a) and FIG. 2A (b). It is worth noting here that the beveled side wall structure of Figure 2B (a) and Figure 2B (b) provides a string / ground selection transistor with a longer channel to reduce the punch-through effect ° Figures 3A to 3C show the flash cell structure of three different pairs of stacked gates of the present invention, of which Figure 3A shows the flash cell structure of a first type of paired stacked gates; Figure 3B shows A flash cell structure of a second type dual stack gate; and FIG. 3C shows a flash cell structure of a third type dual stack gate. FIG. 3A shows that a pair of cell regions (PCR) includes at least a pair of word line regions (WL) formed between a pair of first connection source / drain regions (ISD1) and a scaleable second connection source / drain Region (ISD 2) is formed between the pair of word line regions (w L), where the pair of first connection source / drain regions (ISD 1) are as described with FIG. 2A (a) and FIG. 2A (b) The same; each of the pair of word line regions (WL) from top to bottom includes at least one first side wall dielectric cushion layer 3 1 3 a, a composite control gate conductive layer 3 0 9 c / 3 0 8c, An inter-gate dielectric layer 3007c and a plurality of integrated floating gate structures 3 002d and an etch-back first protruding field oxide layer 3 04b (not shown) located between the adjacent integrated floating gate structures 3 002d (not shown) ), In which the above-mentioned integrated floating gate structures 3 0 2 d each include at least one main floating gate layer 3 0 2 a (not shown) formed in a penetrating dielectric layer 3 〇1 b Above and two extending floating gate layers 3 5a (b) (not shown) are formed on the side wall of the main floating 3 2a and placed adjacent to the first etched back oxide layer

1234244 V. Description of the invention (11), (not shown) on the side part; the above-mentioned micronizable second connection source / and region (ISD2) includes at least a plurality of second connection source / sink diffusion regions 314a. Above the surface portion of the semiconductor substrate 300 within the plurality of active regions (AA) and a second planarized oxide layer 3a-5a is formed on top of it. FIG. 3B shows a flash cell structure of a second type dual-pair stack gate, in which the complex integrated floating floating structure 3 0 2 f is anisotropic and is located within each of the e-pair sub-line regions (). Etched into a complex double-sloping edge-stacked single floating gate structure 302. It can be clearly seen here that the above second ί = = ί = ^ The flasher cell structure provides the double-sloped edge-stacked floating gate structure. There is a large surface area between 302 f and the semiconductor substrate 300 for writing and scrubbing. Figure 3C shows a third type of complex integrated floating gate structure with a single inclined edge integrated floating gate wall structure formed on the flash cell structure of the first pair of stacked gates, 3 0 2 h is engraved non-isotropically to form a complex structure 3 0 2 h and each has an oblique side source / drain region (ISD1)

^ Figure 4A shows a first type non-flash memory array of the present invention using the string / ground selection area (SSR / GSR) and the figure shown in Figure 2A (a) / Figure 2A (b) The flash cell structure of the pair of stacked gates shown in three a is composed.

^ Figure 4B shows a second type of non-flash memory array of the present invention using the string / ground selection area (s SR / G s R shown in Figure 2B (a) / Figure 2B (b). ) And the flash cell structure of the paired stack gate shown in Figure 3B

1234244 V. Description of the invention (12) Figure 4C shows a third type of non-flash memory array of the present invention using the string / ground selection area shown in Figure 2B (a) / Figure 2B (b) (SSR / GSR) and the flash cell structure of the paired stack gate shown in Figure 3B. FIG. 5A shows a first type of non-contact flash memory array of the present invention, in which a plurality of metal bit lines 3 2 1 a together with the plurality of conductive islands 3 1 9 c shown in FIG. 4A Aligning above the plurality of active areas (AA) for simultaneous forming. FIG. 5B shows a second type of non-contact flash memory array of the present invention, in which a plurality of metal bit lines 3 2 1 a together with the plurality of conductive islands 3 1 9 c shown in FIG. 4B Aligning above the plurality of active areas (AA) for simultaneous forming. FIG. 5C shows a third type of contactless non-flash memory array of the present invention, in which a plurality of metal bit lines 3 2 1 a together with the plurality of conductive islands 3 1 9 c shown in FIG. 4C Aligning above the plurality of active areas (AA) for simultaneous forming. Please refer to FIGS. 6A to 6F, which show the manufacturing steps and cross-sectional views of a first type integrated floating gate structure for manufacturing the non-contact flash memory array of the present invention. FIG. 6A shows that a penetrating dielectric layer 301 is formed on a semiconductor substrate 300 of a first conductivity type; then, a first conducting layer 3 0 2 is formed on the penetrating dielectric layer 301. Over; then, a covering dielectric layer 303 is formed on the first conductive layer 302. The above-mentioned penetrating dielectric layer 301 is a thermal dioxide layer or a nitrided layer.

Page 18 1234244 V. Description of the invention (13) The first conductive layer 302 of a thermal silicon dioxide layer having a thickness between 70 angstroms and 120 angstroms is deposited by a chemical vapor deposition (LpcVD) method. (Doped) a polycrystalline silicon layer or a doped amorphous silicon layer with i between 500 angstroms and 2 angstroms. The above-mentioned covering dielectric layer 303 is a nitride nitride layer deposited by a chemical vapor deposition method and its thickness is between 1000 ^ $ 300 angstroms. It is worth noting here that the semiconductor substrate 300 is composed of a well region of the first conductivity type formed in a well region of a second conductivity type and a shallow buried layer of the second conductivity type ( A buried) ion implantation region (not shown) may be formed on a surface portion of the semiconductor substrate 300.

FIG. 6B shows that a plurality of parallel shallow groove isolation regions (ST I) are alternately formed in the semiconductor substrate 300 through a mask photoresist (PR1) step (not shown); then, a plane A chemical field oxide layer (FOx) 304a is formed in each of the plurality of parallel shallow trench isolation regions (STI). The above-mentioned planarized field oxide layer (F 0 X) 3 0 4 a is composed of silicon dioxide, P-glass or boro-phosphorus glass (BP-glass) and uses a high-density plasma (HDP) ) CVD, plasma-enhanced (PE) CVD or LPCVD methods, a thick oxide layer 3 0 4 (not shown) is first deposited to fill the plurality of parallel shallow groove isolation regions (ST I). Each void is then planarized by chemical-mechanical polishing (CMP) and the patterned dielectric layer 303a is used as a polishing stop. FIG. 6C shows the planarized field oxide layer 3 0 4 a located within each of the plurality of parallel shallow groove isolation regions (ST I) using anisotropic dry etching or buffered hydrofluoride. Acid or dilute hydrofluoric acid #

Page 19, 1234244 V. Description of the invention (14) Etching back and forth to a level of about 300 angstroms above a top level of the forming penetrating dielectric layer 3 0 1 a to form the plurality of parallel grooves An etch-back first raised field oxide layer 3 in each of the isolation regions 3 04b ° FIG. 6D shows that the shaped overlying dielectric layer 303 a is added using non-isotropic dry etching or high temperature phosphoric acid. Then, a pair of conductive side edge pad layers (叩 8 ^ 1 *) 3 0 5 &amp; are formed on the adjacent shaped first conductive layer 3〇2_ ^ ΐf. The pair of conductive side wall pads 305 are doped with polycrystalline silicon or doped and stacked using LPCVD method. A conductive 'i, :) is first deposited on the surface of a formed structure and returned. One thickness of the V electric layer 30 5 stacked. As shown in Figure ^ shown = an intergate dielectric layer 30 7 is formed on the gate of one person / face; then, a second conductive layer is electrically covered, and a conductive layer 30 is covered. 7 series one-af electric said above 308. The above inter-gate dielectric layer ^ ^ ^ ^: Τν!);; I ^ (0N0) ^ ^ ^ ^ Angstrom and 300 Angstrom. ) ,,, ° structure and the thickness of the silicon dioxide / effect silicon dioxide is between 70 layers and LPCVD is used to pile up the doped polycrystalline spar—a high-dose doped TiO 2 is implanted with The second conductivity type. The above-mentioned covered conductive banks (Q and Z) are between 150 Angstroms and 2500 Angstroms and use the LPCVD method; or 3,000 Angstroms consisting of the town (W) or tungsten silicide (WSi 2). between. / ′ ′ ′ And its thickness is between 15 0 0 Angstroms and Figure 6F shows that a mask dielectric layer 31 is formed on the cover conductive layer

1234244 V. Description of the invention (15)-ϊ3 = ΐ) ί 爽 i ί 之 ϊ ί The dielectric layer 310 is composed of nitrided stones and stacked using LPCVD to thicken the f; f is between 9 π n pua 5 ,,,,, main core 4 ^ _ ^ 丨, 00 Angstroms and 5000 Angstroms. Here two I: q Μ: / λ 'a main drift gate layer 3 0 2a together with two conductive sides The side ^ f Integralized floating gate structure 3 0 2a / 3 0 5 a to a large ^ = 3 Ϊ 3 flash cell cell consumption ratio (Coupling ratio). % &amp; 5: I μ ^^ A to Figure 7C, which shows a step-by-step diagram of a second-type integrated floating gate structure for manufacturing the non-connected ri i memory / row of the present invention, and the interstitial of c Process steps and sectional views.导电 Ϊ 1 ί f A ## conductive layer 305b is formed on the plurality of parallel 2 1 Φ ® / covering; 丨 on the side wall between the electrical layers 3 0 3 a. The above-mentioned LP ^ decision is composed of doped polycrystalline silicon or doped amorphous silicon and is used to deposit / deposit a thick conductive layer 305 (not shown) to fill in 1J with C; MP , A is formed to cover each gap between the dielectric layers 303a and then ^ 1 IS adds the stacked thick conductive layer 305 to planarization and uses the forming ΐ2T ^ 3〇3 &amp; as a The stop layer was ground to form a planarized guide (i.e., lead 1 (not shown)), and then the planarized conductive layer 30 5a was etched back to 30 fa. # 电 电 层 302_ A surface level. The pair of side wall dielectric pads is composed of a dielectric Wi / f and is stacked using LPCV ^, which is first stacked and then θ Γ Γ (not shown on a surface of the formed structure and the rest One thickness of the stacked dielectric layers 306. One, seven, B shows the pair of side wall dielectric pads 3 0 6a within each of the plurality of parallel shallow groove isolation regions (STI). Etch-back conductive layer

1234244 V. Description of the invention (16) 3 0 5b is anisotropically etched to form a beveled side wall structure and the forming covering dielectric layer 303 a is used together with the pair of side wall dielectric layers 3 0 6 a Addition of high-temperature humic acid or non-isotropic dry etching. It can also be clearly seen here that a main floating gate layer 3 0 2 a together with two extended floating gate layers 3 0 5 c form an integrated floating gate structure 3 0 2a / 3 0 5c to greatly increase a stacked gate. The coupling ratio of flash cytokines. Similarly, an inter-gate dielectric layer 307, a second conductive layer 308, an overlying conductive layer 309, and a mask dielectric layer 3 1 0 are sequentially formed as shown in FIG. 7B. On the surface of a formed structure. A cross-sectional view along a line C-C 'as shown in FIG. 7C or an F-F' line as shown in FIG. 6F is shown in FIG. It can be clearly seen here that compared with the two critical mask photoresist steps used in the prior art, the present invention only needs one stringent mask photoresist (PR 1) step to form FIG. 6F or FIG. An automatic alignment integrated floating gate structure shown in 7C is 3 2a / 3 0 5a (c). Please refer to FIG. 8A to FIG. 8K, which show the manufacturing steps and cross-sectional views of the first type of non-contact type flash memory array of the present invention as shown in FIG. 5A. FIG. 8A shows a cross-sectional view of a multilayer structure along each of the plurality of active areas (A A) of FIG. 6F or FIG. 7C. FIG. 8B shows a plurality of virtual gate areas (VG3) within each of the plurality of memory string areas (MSR), and a first virtual gate area (VG1) within each of the string selection areas (SSR). ) And a second virtual gate area (VG 2) within each of the ground selection areas (GSR) are formed by a mask photoresist (PR2) step (not shown), wherein the above-mentioned plural The third virtual gate area (VG3), the aforementioned second virtual gate area (VG2), and the aforementioned first virtual gate

Page 22, 1234244 V. Description of the invention (17) Area (VG 1) is formed between the first connection source / drain area (丨 sd 1) and each of the first connection source / drain area (I SD1) The width can be defined using a minimum line width (F) of the technology used. FIG. 8B also shows the mask dielectric layer 310, the cover conductive layer 3 0 9, the second conductive layer 3 08, and the gate between each of the first connection source / drain regions (ISD1). The dielectric layer 3 0 7 and the complex integrated structure 3 0 2a / 3 0 5a (c) (see Figure 6F and Figure 7C) are sequentially added and removed by non-isotropic dry money engraving. ; Then, performing ion implantation in an automatic alignment manner to form the plurality of first connection sources / drain diffusion regions of the second conductivity type 3 1 1 a in each of the first connection source / drain regions (丨 SD 丨); A surface portion of the semiconductor substrate 300 of the plurality of active regions (AA) within one. Each of the plurality of first connection source / drain diffusion regions 3 1 1 a is a highly doped diffusion region. It is worth mentioning here that the penetrating dielectric layer 3a located within each of the plurality of first connection source / drain regions (I SD 1) can be removed or retained after ion implantation. Fig. 8C shows that a first planarized oxide layer 3 1 2 a is formed in each gap of the f-th second connection source / drain region (I SD1); then, a non-Yan Jin mask light The resist (pr 3 A) step forms a mask photoresist pr 3 a on each of the string / ground selection area (SSR / GSR); then, 彳 = on the third virtual gate area ( The formation within each of VG3), the layer 3 1 0 af is additionally removed using an anisotropic dry etching method. The above-mentioned two-plane planar oxide layer 3 1 2a is composed of silicon dioxide, phosphor glass, or boron disk. F is deposited using HDPCVD, PECVD, or LPCVD, and is first borrowed: (solid / Lti? Layer 312 (not (Pictured) to fill the gaps in the mother of the plurality of first connected sources / drain (1), and then use CMP method to stack

1234244 V. Description of the invention (18) The thick oxide layer 312 is planarized and the formed mask dielectric layers 310b, 3 1 0a are used as a smoothing stop layer. FIG. 8D shows that the mask photoresist pr 3 A is first removed; then, a pair of first side wall dielectric pads 3 1 3 a are formed adjacent to the first planarized oxide layer 31 2a. A pair of micronizable word line regions (WL) located within each of the plurality of third virtual gate regions (VG3) and located on the side wall and above the molded covering conductive layer 3 0a is defined. A minimizable second connection source / drain region (I SD2) between the minimizable word line regions (wl) (see FIG. 8F); then, a dielectric spacer on the first side wall pair The shaped covering conductive layer 3 9 a between 3 1 3 a, the shaped second conductive layer 3 0 8 a, the inter-gate dielectric layer 3 7 a, and the complex integrated floating gate structure 3 02b are used The non-isotropic dry etching method is sequentially removed; the plurality of second connection sources / drain diffusion regions of the second conductivity type are formed in an auto-aligned manner at the scaleable second connection source / drain region. (I SD2) a surface portion of the semiconductor substrate 3 0 0 of the plurality of active regions within each of them; then, a second planarized oxide layer 3 1 5a becomes Side wall dielectric pads 3 丨 each empty between 5 仏 The first side wall dielectric pads 3 1 3a are lost by nitride stone or dioxide dioxide, stacked using LPC ^ method First, a dielectric layer 3 1 3 (the second connection source / secondary layer is a thick diffused complex area as described above. Each of the above-mentioned \ 314a contains at least one highly doped and bumped ten-coffee layer. The semi-smooth planarized oxide layer 3 1 5a is composed of SiO 2 grabbing the total soil ^ Xiao and can be miniaturized by HDPCVD, PECVD or LPCVD !; a thick oxide layer 315 ( (Not shown) to fill the gaps within each of the force bars you / drain (ISD2)

1234244 V. Description of the invention (19), the CMP method is used to planarize the deposited thick oxide layer 3 1 5 and the formed mask dielectric layer 3 1 0 b is used as a smoothing stop layer. Figure 8B also shows that if the pair of first side wall dielectric pads 3 1 3 a is composed of silicon nitride, a non-rigid mask photoresist (PR3B) step is performed to convert a mask photoresist ( PR3B) is formed on the complex memory string region (MSR). It is worth noting here that the mask photoresistor PR3B can be a reversed tone of the mask photoresistor PR3A. Figure 8E shows that it is within each of the string / ground selection area (SSR / GSR). The formed mask dielectric layer 3 1 0 b is removed by non-isotropic dry etching, and then the mask photoresist PR3B is removed. FIG. 8F shows a pair of second side wall dielectric pads 3 1 6 a formed on the side wall adjacent to the first planarized oxide layer 3 1 2 a and placed in the string / ground selection area (SSR / GSR) over each of the side portions of the shaped overlay conductive layer 309b to define a pair of string / ground selection line regions (SSL / GSL). The pair of second side wall dielectric pads 31 6a is composed of silicon nitride deposited by LPCVD method, and a dielectric layer 3 1 6 (not shown) is first deposited on a formed structure surface. Then return to a thickness of the stacked dielectric layer 3 1 6. It can be clearly seen here that the string / ground selection line area (SSL / GSL) is defined by a pad width of the pair of second side wall dielectric pads 3 1 6 a and can therefore be miniaturized. FIG. 8G shows the shaped covering conductive layer 3 0 9b between the pair of second side wall dielectric pads 3 1 6 a within each of the string / ground selection regions (SSR / GSR). The second conductive layer 3 0 8b, the shaped inter-gate dielectric layer 3 7b, and the complex integrated floating gate structure 3 0 2c are formed by using anisotropic stem.

Page 25 1234244 V. Description of the invention (20)

Equation # Carved method to sequentially add and remove; then, a variety of different ion implantation processes are performed in an auto-aligned manner to form the second conductive type of the highly doped drain / source diffusion region 3 1 7 b in the A surface portion of the semiconductor substrate 300 of the plurality of active regions (AA) within the plurality of common sink / source diffusion regions 317a of the first conductivity type and within each of the string / ground selection regions (SSR / GSR) Serving. Each of the plurality of common source / drain diffusion regions 3 1 7a described above is a lightly-doped diffusion region or a moderately-doped diffusion region. It is worth mentioning here that after removing the extended floating gate layer 3 0 5 b (d) (not shown), the etch-back section located between the pair of second side wall dielectric cushion layers 3 1 6 a A protruding field oxide layer 3 0 4 b is etched back to a surface level of the penetrating dielectric layer 301 a to form a second protruding field oxide from the penetrating dielectric layer 3 0 1 a and an etch back. A flat surface composed alternately of the physical layer 3 04 c (not shown).

Figure 8A shows a pair of third side wall dielectric pads 3 丨 8a formed on the side walls of the pair of string / ground selection line areas (SSL / GSL) and placed in the string / ground selection area ( SSR / GSR) on each of the flat surfaces; then the penetrating dielectric layer 3 0 1 a together with the etch-back second protruding field oxide layer 3 0 4c is simultaneously etched to form A flat bed consisting of a highly doped drain / source diffusion region 3b 7b and an etched back third protruding field oxide layer 304d (not shown); then, a planarized third conductive layer 319a is formed on the flat bed between the pair of third side wall dielectric pads 3118a and placed within each of the string / ground (mSSR / GSR). The pair of third f pp pads 3 and 8 are composed of silicon dioxide or silicon nitride and are stacked using the LPCVD method. A dielectric layer 318 (not shown) is first deposited on one

Page 1212244

5. Description of the invention (21) on the surface of the structure formed, and then etch back a thickness deposited. The above-mentioned planarized third conductive &gt; 31q _ 318 Ding Baozeng d 1 9 a is composed of doped zirconium work and is stacked using LPCVD method, and a third ^: 3 1 9 (not shown) (Shown) to fill the gaps in the pair of third side wall dielectric pads 3, and then use the CMP method to planarize the third conductive layer stacked and use the pair of first / second side walls Dielectric pad layer 313 &amp; / 3ΐ8_ ^ A flat stop layer is formed to form the planarized third conductive layer 3 1 ga. 'Figure VIII shows that a non-rigid mask photoresist (PR4) step is performed to form a mask photoresist PR4 on each of the string selection regions (SSR); then' located in the far ground selection region (GSR) The planarized second conductive layer 3 1 9 a within each is etched back to a predetermined thickness to form a common source conductive line 319 b located within each of the ground selection regions (GSR). FIG. 8J shows that a third planarized oxide layer 3 2 0 a is formed between the pair of third side wall dielectric pads 3 1 8 a and is placed in each of the ground selection regions (gs R). Within the common source conductive line 319b. The third planar oxide layer 3 2 0 a is composed of silicon dioxide, phosphor glass, or borophospho glass and is deposited by HDPCVD, PECVD, or LPCVD. A thick oxide layer 3 2 0 ( (Not shown) to fill a gap between the pair of third side wall dielectric pads 3 1 8 a, and then use the CMP method to force the deposited thick oxide layer 3 2 0 to a plane And using the pair of first / second side wall dielectric pads 3 1 3 a / 3 1 8 a as a smoothing stop layer. It is worth mentioning here that the above-mentioned planarized third conductive layer 319 a can be replaced by a planarized tungsten (W) layer lined with a barrier metal layer to form a plurality of the second conductive type. Deeper high blending

Page 27 1234244 V. Description of the invention (22) The impurity / drain diffusion region (not shown) can be implanted with ions after forming the third side wall dielectric pad 3 1 8 a. In addition, the planarized doped polycrystalline silicon layer 3 1 9 a located within each of the common drain regions (CDR) and the back #planarized doped silicon located within each of the common source regions (CSR) The heteropolycrystalite layer 3 1 9 b may further implant a high-dose dopant of the second conductivity type; then, a third plane within each of the common source regions (CSR) is not formed Before the oxide layer 320a is formed, a self-aligned silicidation process is used to add the lithography to form a metal disilicide layer. FIG. 8K shows that a metal layer 3 2 1 (not shown) is formed on a flat surface shown in FIG. 8J and is aligned with the complex through a mask photoresist (PR5) step (not shown). The active area (AA) is pre-formed to form a plurality of metal bit lines 3 2 1 a integrated with the plurality of collective conductive islands 3 1 9 c. The metal layer 321 is formed by a tungsten (W), copper (Cu), or aluminum (A1) layer on a barrier metal layer, such as a titanium nitride (T i N) or nitride button (TaN) layer. . It can be clearly seen here that compared with the six rigorous mask photoresist steps used in the prior art, only three of the first type of contactless non-flash type 5 flash memory arrays of the present invention need to be manufactured. Rigorous mask photoresist steps (p R 1, PR2 and PR5). In addition, the auto-alignment technology is used to form a flash memory cell structure that can be miniaturized, and a miniaturizable string / ground selection line area (SSL / GSL). It can be made smaller than 4F 2. Furthermore, for a minimum line width (F) of the technology used, the divergent series resistance of a string of the present invention is greater than that of the prior art.

1234244 V. Description of the invention (23) '-; ^ Please refer to FIG. 9A to FIG. 9C, which show the simplified manufacturing steps and cross-sectional views of the manufacture of a first-type contactless non-flash memory array according to the present invention. / 、 Figure 9A shows the complex integrated floating gate structure 302a / 3〇5a (c) located within each of the plurality of first connection source / drain regions (丨 SD 丨) (see Figure 6I And FIG. 7C) is anisotropic etching to form a beveled side wall structure; and then, the ion implantation is performed in an automatic alignment manner to form the second having a laterally doped distribution. The conductive type pile = diffusion area; then, a first planarized oxide is filled with each of the plurality of voids in the source / drain area (丨 SD 丨). Fig. 9B shows a complex integrated floating within each of the plurality of scaleable second connection source / drain regions (丨 SD2) located between a pair of first side wall dielectric pads 3 丨 3a The gate structure 3 0 2b / 3 0 5b (d) (not shown) is also not isotropically ground to form a complex double taper-sided integrated floating gate structure 3 0 2 f; then, Ion implantation is performed in an auto-alignment manner to form a plurality of second connection source / drain diffusion regions 3 1 4a of the second conductivity type having a laterally inclined doping distribution; then, a second planarized oxide layer 3 1 5a fills every gap in the plurality of scaleable second connection source / drain regions ([SD2]). FIG. 9C shows that according to the same process steps shown in FIG. 8E to FIG. 8K, a second type of non-contact and non-type flash memory of the present invention can be obtained. It can be clearly seen here that the first Type 2 without contact

Page 29 1234244 V. Description of the invention (24) Flash memory array can also be manufactured by three rigorous mask photoresistance steps and the equivalent cell size of a string can be made smaller than 4 F 2 . In addition, the equivalent surface area required for writing and scrubbing between a double-slope floating gate structure 3 2 f of a stacked gate flash cell and the semiconductor substrate 300 is higher than the first The type of non-contact non-type flash memory array is larger and the stray series resistance of the first / second connection source / sink diffusion region 31 la / 314a is larger than that of the first type of non-contact non-type flash memory. Small memory array. In addition, the gate length of the string / ground selection transistor is longer than that of the first type of non-contact type flash memory array to reduce the puncture effect. Referring now to FIGS. 10A to 10C, there are shown simplified manufacturing steps and sectional views for manufacturing a third type of contactless non-flash memory array of the present invention. FIG. 10A shows the same process steps as shown in FIG. 9A, in which the complex integrated floating gate structure located within each of the plurality of first connection source / drain regions (I SD 1) 3 0 2a / 3 0 5a (c) is anisotropic etching to form a beveled side wall structure. FIG. 10B shows that the complex integrated floating gate structure within each of the plurality of scaleable second connection source / drain regions (I SD2) 3 0 2a / 3 0 5a (c) (not shown) is non-equal A plurality of sing 1 etaper-sided integrated floating gate structures were formed in the ground to the ground for 3 2 h; then, ion implantation was performed in an automatic alignment manner to form a plurality of the second conductive type. The connection source / drain diffusion regions 3 1 4a; then, a second planarized oxide layer 3 1 5a fills one of each of the plurality of scaleable second connection source / drain regions (I SD2). A gap between the first side wall dielectric pads 3 1 3 a.

Page 30 1234244 V. Description of the invention (25) Fig. 10C shows that according to the same process steps shown in Fig. 8E to Fig. 8K, a third type of contactless non-flash memory array of the present invention can be obtained. It can also be clearly seen here that the equivalent cell size of a string can be further reduced due to a narrow, micronizable second connection source / drain region (I SD2). However, the effective surface area of writing and scrubbing between a single tilted edge integrated floating gate structure 302 h and the semiconductor substrate 300 is also reduced. The other features and advantages of the third type non-contact non-flash memory array are the same as those of the second type non-contact non-flash memory array. According to the above description, the features and advantages of the present invention can be summarized as follows: (a) The non-contact non-type flash memory array of the present invention with a micronizable dual-stack stacked flash cell structure can provide a ratio of 4F 2 A smaller string is equivalent to the cell size. (b) The non-contact non-flash memory array with the flashable cell structure of the miniaturizable dual-stacked stack gate of the present invention can be manufactured with fewer rigorous mask photoresist steps. (c) The non-contact non-flash memory array with a microcell structure capable of reducing the size of the dual-stack stack gate of the present invention can provide a plurality of automatic alignment of common conductive islands for bit line contact and an automatic The common source conductive line is aligned as a ground wire to further reduce the equivalent cell size of a string.

1234244 V. Description of the invention (26) (d) The non-contact non-flash memory array of the present invention with a miniaturizable dual-stack stack flash cell structure can provide a string / ground selection transistor The miniaturized co-drain / source region has a double-diffusion drain / source-diffusion region to further reduce the equivalent cell size of a string without having to worry about the punch-through effect. (e) The non-contact non-flash memory array of the present invention provides a miniaturizable dual-stack stacked flash cell structure with a single inclined edge or double inclined edge floating gate structure to increase the single inclined edge or double The effective surface area between the inclined-side floating gate structure and the semiconductor substrate and the first / the miniaturizable second connection source / drain diffusion region further reduce the stray series resistance. (f) The non-contact flash memory array of the present invention provides a miniaturizable dual-stack stacked flash cell structure with a single inclined edge or double inclined edge floating gate structure to increase string / ground selection transistors Channel length and further mitigates the puncture effect. Although the present invention is particularly illustrated and described with reference to the attached examples or connotations, it is only a representative statement and not a limitation. Furthermore, the present invention is not limited to the listed details. Those skilled in the art can also understand that changes of various shapes or details can be made without departing from the true spirit and scope of the present invention, but also belong to the present invention. The category of invention.

Page 1234244 Brief description of the drawings Figure 1A and Figure 1B show a schematic diagram of a conventional non-flash memory array, of which Figure 1A shows a brief top-view layout diagram; Figure 1B shows Figure 1A Shown is a brief cross-sectional view along an AA 'line. FIG. 2A and FIG. 2B are schematic cross-sectional views of various string / ground selection regions according to the present invention. FIG. 2A (a) and FIG. 2A (b) respectively show a first type_selection region (SSR) and A schematic cross-sectional view of a type 1 ground selection area (GSR); Figures B (a) and (B) show a Type 2 ground selection area (SSR) and a Type 2 ground selection area (GSR), respectively ). FIG. 3A to FIG. 3C are schematic cross-sectional views of flash cell structures of various pairs of stacked gates of the present invention, and FIG. 3A shows a schematic view of the flash cell structures of a first type of paired stack gates. Sectional view; Figure 3B shows a brief cross-sectional view of the flash cell structure of a second type dual-pair stack gate, and Figure 3C shows a brief cross-section view of the flash cell structure of a third-type dual pair stack gate. Sectional view. FIGS. 4A to 40 are schematic cross-sectional views of various non-flash memory arrays of the present invention that are not combined according to FIGS. 2A, 2B, and 3A to 3C. FIG. 4A shows A schematic cross-sectional view of a first type flash memory array; FIG. 4B shows a schematic cross-sectional view of a second type flash memory array; and FIG. 4C shows a third type flash memory array. A brief cross-sectional view of a flash memory array. 5A to 5C are schematic cross-sectional views of various non-contact flash memory arrays of the present invention, and FIG. 5A shows a brief view of a first type of non-contact flash memory array. Sectional view; FIG. 5B shows a schematic cross-sectional view of a second type of non-contact flash memory array

Page 34 1234244 is a brief description of the diagram; and Fig. 5c shows a schematic cross-sectional view of a third type of non-contact non-type flash memory array. Figures 6A to 6F show the process steps and cross-sectional views of a first type integrated floating gate structure for manufacturing various non-contact non-type flash memory arrays of the present invention. Figures 7A to 7C show the manufacturing steps and cross-sectional views of a second type integrated floating gate structure for manufacturing various non-contact non-type flash memory arrays of the present invention.

FIGS. 8A to 8K show the process steps and cross-sectional views of the first type of non-contact non-type flash memory array in accordance with the present invention, which are subsequent to FIG. 6F or FIG. 7C. FIGS. 9A to 9C show the simplified process steps and cross-sectional views of FIG. 8A, which are continuations of manufacturing a second type of contactless non-flash memory array of the present invention. Fig. 10A to Fig. 10C show the simplified process steps and cross-sectional views of Fig. 8A, which is a continuation of the manufacture of a third type of contactless non-type flash memory array of the present invention. Representative drawing number description:

3 0 0 Semiconductor substrate 301 penetrating dielectric layer 301a forming penetrating dielectric layer 301b forming penetrating dielectric layer 3 0 2 first conductive layer 302a forming first conducting layer 3 0 2b integrated floating gate structure (cell element Area)

Page 34 1234244 Schematic description of 3 0 2 c integrated floating gate structure (selection gate area) 3 0 2 d steep integrated floating gate structure (cell element area) 3 0 2 e steep integrated floating gate structure (Selected gate area) 3 0 2 f double-inclined edge integrated floating gate structure (cell element area) 3 0 2 g single beveled edge integrated floating gate structure (selected gate area) 3 0 2h single inclined side integrated Floating gate structure (cell area) 303 Overlaying dielectric layer 303a Forming overlying dielectric layer 3 0 4 a Planarized field oxide layer 304b Back to the first worm field oxide layer 3 0 4c Back to etch back second field oxide Physical layer

3 0 4d etch back the third protruding field oxide layer 305a side wall conductive pad layer 305c extended conductive layer 3 0 6 a side wall dielectric pad layer 3 0 7 inter-gate dielectric layer 3 0 7a / 3 0 7c Inter-dielectric layer (cell area) 3 0 7b / 3 0 7d Inter-gate dielectric layer (selection area) 3 0 8a / 3 0 8c Control gate conductive layer (cell area) 3 0 8b / 3 0 8d Control gate Conductive layer (selective area) 3 0 9a / 3 0 9c cover conductive layer (cellular area) 309b / 309d cover conductive layer (selective area) 310 mask dielectric layer 310a mask dielectric layer (cell area)

3 1 Ob mask dielectric layer (selection area) 3 1 1 a first connection source / diffusion region 312a first planarized oxide layer 31 3a first side wall dielectric pad layer 3 1 4 a second connection Source / drain diffusion region 3 1 5 a Second planarized oxide layer 316 a Second sidewall spacer dielectric pad 317 a Common source / drain diffusion region

Page 1234244

Page 36

Claims (1)

1234244 6. Scope of patent application 1. A pair of stacked gate flash cell structure including at least: a pair of micronizable word line regions (WL) formed in a semiconductor including at least one well region of a first conductivity type Above the substrate ', wherein a plurality of active regions (AA) and a plurality of parallel shallow groove isolation regions (ST I) are alternately formed on the semiconductor substrate and are perpendicular to the pair of micronizable word line regions (WL). A miniaturizable second connection source / drain region (I SD2) is formed between the pair of micronizable word line regions (WL), wherein the pair of micronizable word line regions is formed at a pair of first connection source Between the drain region (I SD 1); each of the pair of first connection sources / drain region (I SD 1) includes at least one second conductive type complex first connection source / drain diffusion region formed on the plurality of active A surface portion of the semiconductor substrate within a region (AA) and a first planarized oxide layer are formed on top of the semiconductor substrate; the micronizable second connection source / drain region (I SD2) includes at least the second conductive A plurality of second connection source / drain diffusion regions of the type are formed in the plurality of active regions (AA) The surface portion of the semiconductor substrate and a second type planarizing oxide layer are formed on top of it; and each of the pair of micronizable word line regions includes at least one first side from top to bottom A wall dielectric layer is formed on a side wall of the first planarized oxide layer, a composite control gate conductive layer, an inter-gate dielectric layer, and a complex integrated floating gate structure, wherein the complex integrated body Each of the floating gate structures includes at least one main floating gate layer formed within each of the plurality of active regions, a penetrating dielectric layer and two extended floating gate layers formed on side walls of the main floating gate layer. Above and placed on the side portions of the first protruding field oxide layer adjacent to the parallel shallow groove isolation region (ST I). Page 37 1234244 6. Scope of patent application 2. The dual-pair stack gate flash cell structure described in item 1 of the scope of patent application, wherein the above-mentioned semiconductor substrate includes at least the well region of the first conductivity type formed in Within a well region of the second conductivity type and a shallow buried ion implantation layer of the second conductivity type is formed on a surface portion of the semiconductor substrate. 3. The flash cell structure of the dual-pair stack gate as described in item 1 of the patent application scope, wherein each of the two extended floating gate layers is a conductive side wall cushion layer or an extended conductive layer by A sidewall spacer is defined and etched anisotropically to form a beveled sidewall structure. 4. The flash cell structure of the dual-pair stack gate as described in item 1 of the scope of the patent application, wherein each of the above-mentioned integrated floating gate structures is formed into a steep integrated floating gate structure and a double tilt Side-integrated floating gate structure or a single inclined side-integrated floating gate structure. 5. The dual-pair stack gate flash cell structure described in item 1 of the patent application scope, wherein each of the pair of first connection source / drain regions is defined by a minimum line width of the technology used and the Each of the miniaturizable word line regions is defined by the first sidewall spacer. 6. A non-contact non-flash memory array comprising at least: a semiconductor substrate including at least one well region of a first conductivity type Page 38 1234244 6. Scope of patent application, in which a plurality of parallel shallow groove isolation regions (STI) and a plurality of active regions (AA) are alternately formed on the semiconductor substrate, and a plurality of memory string regions (MSR) are alternately formed. Formed on the semiconductor substrate, wherein each of the plurality of memory string regions is formed between a string selection region (SSR) and a ground selection region (GSR); a plurality of pairs of stacked gate flash cell structures are formed Within each of the plurality of memory string regions (MSRs), wherein each of the plurality of even-pair stacked gate flash cell structure includes at least a pair of miniaturizable word line regions (WL) formed in a pair of first Between the connection source / drain regions (I SD 1) and a miniaturizable second connection source / drain region (ISD2) are formed between the pair of miniaturizable word line regions (WL); the pair of miniaturizable word lines Each of the regions (WL) from top to bottom includes at least one first side wall dielectric layer formed on a side wall of the first connection source / drain region, a composite control gate conductive layer, and a gate. Inter-dielectric layer and complex integrated floating gate structure, wherein the complex number Each of the integrated floating gate structures includes at least one main floating gate layer formed on a penetrating dielectric layer and two extended floating gate layers formed on a side portion of the oxide layer adjacent to the etch-back first protruding field Above; each of the pair of first connection source / drain regions (I SD 1) includes at least a plurality of first connection source / drain diffusion regions of a second conductivity type formed within the plurality of active regions (AA) A surface portion of the semiconductor substrate and a first planarized oxide layer are formed on top of the semiconductor substrate; the miniaturizable second connection source / drain region (I SD2) includes at least a plurality of second connection sources of the second conductivity type / A drain diffusion region is formed on a surface portion of the semiconductor substrate of the plurality of active regions (AA) and a second planarizing oxide Page 39 1234244 6. The patent application scope layer is formed on top of it; the string / ground selection area (SSR / GSR) contains at least a pair of scalable string / ground selection line areas (SSL / GSL) formed on the pair A series of test source / drain regions (ISD1) and a scaleable common drain / source region (CDR / Csi) are formed between the pair of scaleable string / ground selection line regions (SSL / GSL); the pair Each of the miniaturizable string / ground selection line area (SSL / GSL) includes at least one second side wall dielectric pad from top to bottom formed on one of the first connection source / drain area (I SD 1) Above the side wall, a conductive layer of the string / ground selection line, an inter-gate dielectric layer, and a plurality of integrated floating gate structures, wherein each of the plurality of integrated floating gate structures includes at least one main floating gate layer. Above the penetrating dielectric layer and two extended floating gate layers are formed on the side portions adjacent to the etched back first protruding field oxide layer; the miniaturizable common source / drain region (CSR / CDR) A plurality of common source / drain diffusion regions including at least the first conductivity type are formed on the pair of miniaturizable ground / string selection lines (GSL / SSL), the surface portion of the semiconductor substrate within the plurality of active areas (AA), and a pair of third side wall dielectric pads are formed in the miniaturizable ground / string selection line area ( GSL / SSL) on a side wall and on a flat surface composed of the penetrating dielectric layer and an etch-back second protruding field oxide layer alternately and a plurality of the second conductivity type A highly doped source / drain diffusion region is formed within the plurality of common sources / &gt; between the pair of third side wall dielectric pads and a diffusion region, and a common source conductive pipeline is formed on the pair of third side edges Between the wall dielectric pads and between each of the plurality of highly doped source diffusion regions and an etch-back third protruding field oxide layer located within the micronizable common source region (CSR) Page 40 1234244 VI. A flat bed composed of alternating patent applications, in which a third planarized oxide layer is formed between the pair of third side wall dielectric pads and placed in the common source conduction Over the pipeline; a plurality of common-drain conductive islands are formed between the pair of third side wall dielectric pads within the miniaturizable common-drain region (CDR) and are positioned within the plurality of common-drain diffusion regions The plurality of highly doped drain diffusion regions; and a plurality of metal bit lines along with the plurality of common drain conductive islands located within the scalable common drain region (CDR) are aligned with the active active region (AA) Come up and shape at the same time. 7. The non-contact non-flash memory array according to item 6 of the scope of patent application, wherein the semiconductor substrate includes at least the well region of the first conductivity type formed in a well region of the second conductivity type A shallow buried ion implantation layer within the second conductivity type is formed on a surface portion of the semiconductor substrate. 8. The non-contact non-type flash memory array as described in item 6 of the scope of the patent application, wherein the complex integrated floating gate within each of the above-mentioned multiple even-pair stacked gate flash cell cell structures The structure is anisotropically etched to form a steep integrated floating gate structure, and each of the plurality of first / second connection sources / drain diffusion regions is doped across the through-hole by an automatic alignment. A dielectric layer is implanted into a surface portion of the semiconductor substrate within each of the plurality of active regions (AA). Page 41 1234244 6. Scope of patent application 9. The non-contact non-flash memory array as described in item 6 of the scope of patent application, wherein the above-mentioned plural pairs of each of the stack gate flash cell structure The complex integrated floating gate structure inside is etched anisotropically to have a beveled side wall structure located in the first / micronizable second connection source / drain region (ISD1 / ISD2) respectively. Double-sloping edge floating gate structure and each of the plurality of first / second connection source / drain-diffusion regions passes the dopant across the beveled side wall structure and the penetrating dielectric by means of automatic alignment. A layer is implanted into a surface portion of the semiconductor substrate within each of the plurality of active regions (AA) to form a laterally tilted impurity exchange distribution. 10. The non-contact non-type flash memory array as described in item 6 of the scope of the patent application, wherein the complex integration floats within each of the above-mentioned multiple even-pair stacked gate flash cell structure. The gate structure is non-isotropically etched to have a beveled side wall structure formed in each of the pair of first connection source / drain regions as a single inclined side-integrated floating gate structure and the plurality of first Each of the connection source / drain diffusion regions is implanted with dopants across the beveled sidewall structure and the penetrating dielectric layer into each of the plurality of active regions (AA) by an automatic alignment method. A surface portion of the semiconductor substrate inside to form a laterally inclined doping profile. 1 1 · The non-contact non-type flash memory array as described in item 6 of the scope of patent application, wherein the complex integral floatation within the above-mentioned miniaturizable string / ground selection line area (SSL / GSL) The gate structure is anisotropically etched into a steep floating gate structure composed of doped polycrystalline silicon or doped amorphous silicon. Page 42 1234244 VI. Patent application scope Selection of line conductive layer The second side wall dielectric pad layer is used to define at least one tungsten (W) or tungsten silicide (WS i 2) layer placed in a highly doped layer Above the polycrystalline silicon layer. 1 2. The non-contact non-flash memory array as described in item 6 of the patent application scope, wherein the plurality of floats within each of the pair of miniaturizable string / ground selection line area (SSL / GSL) The gate structure is anisotropically etched into a single oblique integrated floating gate structure, which is formed adjacent to the first connection source / drain region (I SD 1) and is made of doped polycrystalline silicon or doped amorphous silicon. The string / ground selection line conductive layer is defined by the second side wall dielectric pad layer to contain at least one tungsten (W) or tungsten silicide (WS i 2) layer placed on a highly doped polycrystalline silicon layer Above. 1 3. The non-contact non-flash memory array described in item 6 of the scope of patent application, wherein the first side wall dielectric pad is used to define the pair of micronizable word line regions ( The composite control gate conductive layer within each of WL) and the composite control gate conductive layer includes at least one tungsten (W) or tungsten silicide (WSi2) layer on top of a highly doped polycrystalline silicon layer. 1 4. A non-contact non-flash memory array comprising at least: a semiconductor substrate including at least one well region of a first conductivity type formed in a well region of a second conductivity type, wherein a plurality of parallel shallow A groove isolation region (STI) and a plurality of active regions (AA) are alternately formed on the semiconductor substrate; a plurality of memory string regions (MSR) are alternately formed on the semiconductor substrate 1234244 6. Scope of patent application, wherein each of the plurality of memory string regions (MSR) is located between a string selection region (SSR) and a ground selection region (GSR) and contains at least a plurality of pairs of stacked gate flash cell structures Each of the plurality of pairs of stacked gate flash cell structures includes at least a pair of micronizable word line regions (WL) formed by a pair of first side wall dielectric chirp layers adjacent to the first connection source / A drawable area (I SD 1) is defined on the side wall of the drawable area and a scaleable second connection source / draw area (I SD2) is formed between the pair of scaleable word line areas (WL). Each of the miniaturized word line regions (WL) from top to bottom includes at least one first side wall dielectric layer, a composite control gate conductive layer, an inter-gate dielectric layer, and a complex integrated floating gate structure. Each of the plurality of integrated floating gate structures includes at least one main floating gate layer formed on a penetrating dielectric layer and two extended floating gate layers formed on a side adjacent to the etched back first protruding field oxide layer. Above the edge; the first / scalable second connection The / Drain region (ISD1 / ISD2) includes at least the first / second connection source / Diver diffusion region of the second conductivity type, wherein the plurality of first / second source / Diver diffusion regions are automatically aligned. The dopant crosses a beveled side wall structure and the penetrating dielectric layer is implanted into the surface portion of the semiconductor substrate within the plurality of active regions to form a laterally inclined doping profile; the string / ground selection Area (SSR / GSR) contains at least a pair of miniaturizable string / ground selection line areas (SSL / GSL) formed between a pair of first connection source / drain areas (ISD1) and a micronizable common drain / source area (CDR / CSR) is formed between the pair of miniaturizable string / ground selection line areas (SSL / GSL); each of the pair of miniaturizable string / ground selection line areas (SSL / GSL) is composed of Page 44 1234244 6. The scope of the patent application includes at least one second side wall dielectric pad to define each of the pair of miniaturizable string / ground selection line areas (SSL / GSL), one 亊 / The ground selection line conductive layer, an inter-gate dielectric layer, and a plurality of integrated floating gate structures, wherein each of the plurality of integrated floating gate structures includes at least one main floating gate layer formed on a penetrating dielectric layer And two extended floating gate layers are formed on the side wall of the main floating gate layer and are placed adjacent to the first etched back first oxide field oxide layer; the miniaturizable common drain / source region (CDR / CSR) A plurality of common sink / source diffusion regions including at least the first conductivity type are formed in the semiconductor substrate within the plurality of active regions (AA) between the pair of micronizable string / ground selection line regions (SSL / GSL). The surface portion and a pair of third side wall dielectric pads are formed on the side walls of the pair of miniaturizable string / ground selection line areas (SSL / GSL) and placed between the penetrating dielectric layer and A reciprocal second protruding field oxide layer composed alternately on a flat surface and The plurality of highly doped drain / source diffusion regions of the second conductivity type are formed within the plurality of common drain / source diffusion regions; a common source conductive pipeline is formed between the pair of third side wall dielectric pads and disposed. On a flat bed consisting of an etched back third protruding field oxide layer and each of the plurality of highly doped source diffusion regions within the scalable common source region (CSR) alternately A third planarized oxide layer is formed between the pair of third side wall dielectric pads and placed on the common source conductive pipeline; a plurality of common drain conductive islands are formed on the pair of third side wall dielectrics. Between the underlayers and over the plurality of highly doped drain diffusion regions within the scalable common drain region (CDR); and Page 45 1234244 VI. Scope of patent application The plurality of metal bit lines together with the plurality of conductive islands located within the scalable common drain region (CDR) are aligned on the plurality of active regions (AA) to form at the same time. 1 5. The non-contact non-type flash memory array according to item 14 of the scope of the patent application, wherein a shallow buried ion implantation layer of the second conductivity type is formed on a surface of the semiconductor substrate. Part. 16. The non-contact non-flash memory array as described in item 14 of the scope of patent application, wherein the above-mentioned common source conductive pipeline includes at least one tungsten (W) or tungsten silicide (WS i 2) layer placed on On top of a highly doped polycrystalline silicon, a highly doped polycrystalline silicon layer, or a tungsten (W) or tungsten silicide (WS i 2) layer is lined with a barrier metal layer and each of the plurality of total conductive islands is at least Contains a tungsten (W) or tungsten silicide (WSi 2) island placed on top of a highly doped polycrystalline silicon island, a highly-therapeutic polysparite island, or a crane (W) or Shixi chemical plutonium (WS i 2) The island has a barrier metal layer. Quick and easy to side configuration, one and one knots and non-one-wall non-enveloped points, each borrowed from the edge point less connected to the side to the non-layer layer angle without layer gate electric slant Drifting into the gate_Extending the engraving_System 14 Extending the Eclipse 14 Controlling the first place and enclosing the two or the perimeter of the treasury, etc. Fan Lishu, non-profit, post-secondary wall, and post-secondary Please ask Shen Zhongru and Shen Ruru, Dian Lairu, • Guide layer · Column 7 8 Page 46 1234244 6. The scope of patent application (WS i 2) or tungsten (W) layer is placed on a highly doped polycrystalline silicon layer and the inter-gate dielectric layer contains at least one silicon dioxide / silicon nitride / Silicon dioxide (NO) structure or a silicon nitride / silicon dioxide (NO) structure. 19. The non-contact non-flash memory array as described in item 14 of the scope of patent application, wherein each of the plurality of metal bit lines described above includes at least one tungsten (W), aluminum (A1), or A copper (Cu) layer is placed on top of a barrier metal layer. 20. The non-contact non-flash memory array as described in item 14 of the scope of the patent application, wherein each of the above-mentioned plural integrated floating gate structures is formed into a steep integrated floating gate structure A double beveled integrated floating gate structure having the beveled side wall structure located in the first connection source / drain region (ISD1) and the scaleable second connection source / drain region (ISD2) or one The single beveled floating gate structure has the beveled side wall structure located within the first connection source / drain region (ISD1). Page 47