TWI220558B - Dual-bit floating-gate flash cell structure and its contactless flash memory arrays - Google Patents

Abstract

A dual-bit floating-gate flash cell structure comprises a gate region being formed between a common-source region and a common-drain region. The gate region comprises a pair of floating-gates being defined by a pair of second sidewall dielectric spacers and a select-gate dielectric layer being formed between the pair of floating-gates. The common-source/drain region comprises a common-source/drain diffusion region or a pair of isolated source/drain diffusion regions divided by a shallow trench isolation region being formed between a pair of first sidewall dielectric spacers. A word line being formed over an intergate dielectric layer is at least formed over the pair of floating-gates and the select-gate dielectric layer. Based on the common-source/drain diffusion regions and the isolated source/drain diffusion regions of the described dual-bit floating-gate cell structure, two different contactless flash memory arrays are formed.

Description

1220558 V. Description of the invention (1) (1) The technical field to which the invention belongs The present invention relates to a non-volatile semiconductor memory cell and its memory array, and in particular to a two-bit floating gate flash cell structure and its Contact flash memory array. (2) The prior technology is considered to be a technology. Therefore, the flash memory can be grouped (N0R stack gate is often one, but because a bit sum type is the element array 1J, the flash memory of the array is added and a stack gate (st ack-gat e) The flash memory cell is a public transistor cell, and the gate length of one cell is defined by a minimum-feature size F, which is a high density. ), Non- or flash memory array, plus additional connection. The smaller the size of the cell is, the slower the speed. The speed of the pair is faster, but the element size is a non-through flash memory layer source. / Non-diffusion line A non-harmonic flash unit is commonly used to group cells, such as a unit system of non-and a non-harmonic source / diffusion, which reads out, and reads out unit cells. For a cell line, the ratio of the size of the buried cell is slower than a non-sum flash memory array but slightly slower than a non-or flash memory array. The stack gate is fast, and the stack gate flash memory cell system. Stacking gate flash memory into a variety of different The array architecture), and the type and (AND). For the flash memory cell element system, the contact relationship of the element line by a series of non-harmonic flash memory arrays in the structure of the off-resistance or type flash memory array, and the contact relationship of the element line, the size of the flash memory array is large, but it is not miniaturized. A major concern is that the flash memory of the stacked gates is connected in a small way.

Page 6 1220558 V. Description of the invention (2) The cell can use a pair of stacked flash memory cells to be isolated by a selective gate transistor to form a two-bit flash memory cell to avoid stacking. Over-erasing of the gate structure. A typical example of a two-bit flash memory cell is shown in Figures A and B. Now referring to FIG. 1A, two stacked gate cells 2 2 G and 20 G are separated by a selective gate 24G, and two total N + / N diffusion lines 20A and 22A are used as bit line systems. They are formed in the outer parts of each of the two stacked gate cells 2 2 G and 20 G, respectively. A top-view layout system of FIG. 1A is shown in FIG. 1b, where a polycrystalline silicon layer 28 is formed as a selective gate line system on two common N + / N diffusion lines 2 0 A, 2 2 A And above the two control gate lines 2 2 C, 2 0 C of the two stacked gate cell elements. It can be clearly seen from Figures 1A and 1B that a two-bit flash memory cell requires at least four mask photoresist steps to make the 'minimum cell size of each bit is limited to 4F 2. In addition, compared with the existing non-harmonic, non-or, and harmonic arrays of stacked gate cells, the dual-bit flash memory cell still exhibits some disadvantages: the selection gate line 28 and the bit The stray capacitance between the element lines 20A and 22A is large; the selection gate line 28 and the control gate line 20 of the stacked gate cells (the stray capacitance between 22 (:) are large; the The alignment (a: ignment) between the selection gate line 28 and the floating gate 22β, 20β is a dangerous one (cr 丨 t 丨 ca 1); Poor isolation between the elements, and the Ft χ auto, > Μ & / t separation between adjacent control gates of the selected gate line is also poor. It is worth mentioning that adjacent selection The silent connection between the gate lines and the erroneous reading of ak and ak are the wrong data read of a selected cell. Therefore, a main object of the present invention is to provide a two-bit floating

1220558 V. Description of the invention (3) The gate cell structure has a cell size of less than 4 F 2 per bit. Another object of the present invention is to provide a good isolation of the adjacent two-bit floating gate cell structure of the adjacent two-bit floating gate cell structure below the adjacent word line. It is a further object of the present invention to provide two array structures composed of the two-bit floating gate cell of the present invention with fewer mask photoresist steps. Summary of the invention:

The invention discloses a double-bit floating gate flash cell structure and a contactless flash memory array formed on a semiconductor substrate. The two-bit floating gate flash cell structure includes at least one gate region formed between a common source region and a common drain region, wherein the above gate region and the common source / drain region are borrowed by a first mask light. Resistance step to shape. The gate region includes at least a pair of floating gates formed on a pair of penetrating dielectric layers and is defined by a pair of second side wall dielectric pads and a selective gate dielectric layer is formed between the pair of floating gates. Wherein one of the ion implantation regions includes at least one shallow ion implantation region as a threshold voltage adjustment and a deep ion implantation region to form a semiconductor substrate formed under the selective gate dielectric layer with a resisting prohibited region Surface part. The common source / drain region includes at least one common source / drain diffusion region or a pair of separated source / drain diffusion regions; a pair of first side wall dielectric pads are formed on the sides of each of the common source / drain regions. Over the wall and on a portion of the surface of the penetrating dielectric layer to form a shallow highly doped common source / drain diffusion region within each of the common source / drain diffusion regions or a shallow recess Slot in the pair of first side walls

Page 8 1220558 V. Description of the invention (4)

A pair of separated source / diffusion regions is obtained between the dielectric pads; and a first planarized thick dioxide layer of the worm and a pair of dysprosium layers of the first side wall of the worm Within each of the common source / drain zones. A word line is placed on an inter-gate dielectric layer formed on the pair of floating gates and the selective gate dielectric layer in the gate region and on the first etch-back side of the common source / drain region The side wall dielectric cushion layer and the etched back first planarized thick silicon dioxide layer, wherein the zigzag line, the inter-gate dielectric layer and the pair of floating gates are subjected to a second mask photoresist step. The semiconductor substrate is formed and etched at the same time and located inside the gate region outside the word line to implant dopants to form an isolation implant region or anisotropic etching to form a shallow groove isolation region. The above-mentioned two-bit floating gate cell structure is used to form two different contactless flash memory arrays: a contactless parallel common source / drain diffusion bit line array and a contactless parallel separated source / drain Diffusion bit line array.

The contactless parallel common source / diffusion bit line array includes at least a plurality of gate regions. A first mask photoresist step is used to form and alternately form a semiconductor substrate in parallel. The above-mentioned plurality of gate regions Each is located between the common source / drain regions; a common source / drain diffusion region is formed as a common source / drain diffusion bit line on a surface portion of the semiconductor substrate of each of the common source / drain regions ; A pair of etched first side wall dielectric pads are formed on a pair of penetrating dielectric layers located within each of the common source / drain regions: a shallow highly doped common source / drain diffusion region A dopant is implanted on the surface portion of the semiconductor substrate between a pair of first side wall dielectric pads and formed in the common source / drain diffusion region by an automatic alignment method; an etched back first plane A thick silicon dioxide layer is formed in each of the common source / drain regions

Page 9 1220558 V. Description of the invention (5)

Between the pair of back-etched first side wall dielectric pads; the plurality of even-pair floating gates are defined within each of the plurality of gate regions by a pair of second side wall dielectric pads and have A selective gate dielectric layer is placed on an ion implanted region to form between the pair of floating gates; a complex digital line is placed on the inter-gate dielectric layer and is perpendicular to the common source / drain region and forms Over the plurality of even-pair floating gates and the selective gate dielectric layer located in the plurality of gate areas and the plurality of etched back first side wall dielectric cushion layers and the etched first place in the common source / drain area Planarizing a thick silicon dioxide layer; and a plurality of isolation implanted regions or a plurality of shallow groove isolation regions formed on the surface portion of the semiconductor substrate outside the plurality of digital lines and located between the common source / drain regions. The ion implantation region is located under the selective gate dielectric layer and includes at least one shallow ion implantation region as a threshold voltage adjustment and a deep ion implantation region to form a resistance forbidden region.

The contactless parallel separated source / diffusion bit line array includes at least a plurality of gate regions. A first mask photoresist step is used to form and alternately form a semiconductor substrate in parallel. The above-mentioned plurality of gate regions Each is located between the common source / drain regions; a pair of separated source / drain diffusion regions are defined by a pair of first side wall dielectric pads and separated by a shallow groove isolation region; a back An etched first planarized thick silicon dioxide layer is formed between each of a pair of etched back side wall dielectric pads in each of the common source / drain regions; a plurality of even pairs of floating gates are formed by a pair of first Two side wall dielectric mats are formed within each of the plurality of gate regions and a selective gate dielectric layer is placed over an ion implantation region to form between the pair of floating gates; The plurality of pairs of floating gates and the selection are positioned above each of the plurality of inter-gate dielectric layers perpendicular to the separation source / diffusion diffusion region and placed in each of the plurality of gate regions

Page 10 1220558 V. Description of the invention (6) Etching the first side wall dielectric cushion layer above the gate dielectric layer and each of the common source / drain regions and the first planarization thickness Above the oxide layer, and a plurality of isolation implanted regions or a plurality of shallow groove isolation regions are formed on the surface portion of the semiconductor substrate outside the plurality of digital lines and located between the common source and the region. The ion implantation region is placed under the selective gate dielectric layer and includes at least one shallow ion implantation region as a threshold voltage adjustment and a deep ion implantation region to form a resistance forbidden region. Embodiments of the invention: Please refer to FIG. 2A to FIG. 2I, which disclose the manufacturing steps of manufacturing a two-bit floating gate cell structure of the present invention and a contact-free parallel co-source / diffusion bit line array and the steps Sectional view. FIG. 2A shows that a penetrating dielectric layer 3 0 1 is formed on a semiconductor substrate 3 0 of a first conductivity type; a first conducting layer 3 0 2 is formed on the penetrating dielectric layer 30 1 And a first mask dielectric layer 303 is formed on the first conductive layer 302. The penetrating dielectric layer 301 is a thermally oxidized layer or a nitrided thermal oxide layer, and its thickness is between 70 angstroms and 120 angstroms. The first conductive layer 3 0 2 is a doped polycrystalline silicon layer or a doped amorphous silicon layer and is deposited by a low pressure chemical vapor deposition (LPCVD) method. The thickness is between 100 angstroms and 3 angstroms. 0 0 0 Angstroms. The first mask dielectric layer 303 is a silicon nitride layer and is deposited by LPCVD, and has a thickness between 2000 angstroms and 5000 angstroms. FIG. 2B shows that the first mask dielectric layer 303 a described above uses a first mask photoresist (PR1) step (not shown) to define a plurality of gate regions (GR) and

1220558 V. Description of the invention (7) ^ ^ ........ ^ Plural common source / drain region (CS / DR); Then, it is located in each of the plural common source / narrow region (CS / DR) The first mask dielectric layer 303 and the first conductive layer 302 are sequentially removed using an anisotropic dry etching method; then, 'an ion implantation process is performed and an automatic alignment is performed. A complex common source / drain diffusion region 304a of the i-th conductivity type is formed. It is worth mentioning here that ^ the width of the gate area (GR) and the width of the common source / drain area (CS // DR) can be defined by using a minimum line width of the technology (minimum feature siz 1). The common source / drain diffusion region 3 〇 4 a may be lightly doped, moderately strained, or highly doped. Τ and doped

^ Figure 2C shows a pair of first side wall dielectric pads 305 are respectively formed on the side walls adjacent to the gate region (GR) and placed at the common source / drain ^ (CS / DR ) Above each of the penetrating dielectric layers 301; then, ion implantation is performed in the following manner to form a second conductivity type: hetero-common source / drain diffusion region 304b Within the common source / drain diffusion region 3.04a, the pair of first side wall dielectric pads 305a is composed of silicon dioxide, and a silicon dioxide layer is deposited by LPCVD method 305. A thickness of one of the deposited silicon oxide layers 3 05 is then etched back.

Figure 2D shows that a first planarized thick silicon dioxide layer 306a is formed; = each of the common source / drain regions (CS / DR) is between the pair of first sides, and a wall dielectric layer A gap between 3 0 5a; then 'located in the gate area :: the shaped first mask dielectric layer 3 0 3 a is made using hot phosphoric acid or non-equal: J: type etching to add selectivity Ground m '~; the second side wall layer 307a is formed on the side adjacent to the first side wall dielectric pad layer 305a and is placed on a portion of the first conductive layer 3 0 2a. Above the surface

1212558 on page 12 V. Description of the invention (8) The meaning of a pair of floating gates 3 0 2 b and a selection gate between 4 pairs of floating gates 3 0 2 b in each of the gate regions (GR). Area (s GR). The first planarized thick monoxide layer 306a is composed of dioxide, glass (p-giass: or BP-glass), and uses the lpcvd method and high-density plasma (HDP). CVD method, or plasma enhanced (PE) CVD method, is used to deposit a thick silicon dioxide layer 3 06 on top of it, and then chemical-mechanical smoothing (CMp) method is used to planarize and form the first mask. The dielectric layer 303a serves as a polishing stop. The pair of second side dielectric pads 307a is composed of silicon nitride and is deposited using the LPCVD method. It can be clearly seen here that The selected gate region (SGR) located in each of the gate regions (GR) can be controlled by the pad width of the second side wall dielectric cushion layer 307 & The thickness of the stacked dielectric layer 307 is controlled. It is noted that the pair of the second side wall dielectric cushion layer 30h can also be composed of 1 疋 dioxide crushed and used LPCVD method to It is shown that the two-layer conductive layer 3202, which is located between the pair of second side wall dielectric pads 307a, uses an anisotropic dry etching method. The preselected impurities "J i are ion implanted in an auto-aligned manner to implant the dopant-penetrating dielectric layer 301 into the surface of the semiconducting semiconductor 30 and cut to form the selective gate region (s Γ An ion implantation area of the first conductivity type within the mother of Fuji Lei Xing & Yi Ye, Banxun ^ UGR). The ion implantation area is like a dotted line "4 = plant area contains at least one Shallow deep ion implantation is like playing xxx 1 :; 2: Adjusting the boundary voltage and-zone (nnnrh A u pay 5 tigers & shown to form a punch-through stop). Figure 2F The display is located at the I 筮 一 扣 I, true

The dielectric cushion layer on the side wall of the opposite side is between 3 〇 7 a

1220558 V. Description of the invention (9) The penetrating dielectric layer 3 0 1 is added and removed by using the method of Su boring> Jin # engraving; however, "Bu Di :: dipping, non-isotropic dry 3 0 9a system is formed on The pair of first-side-thickened silicon dioxide layer and second-planarized-thickness silicon dioxide layer: = electrical layer 3 ° 7a. The above-mentioned LPCVD method or high-temperature oxide: composed of Shi Xi and using = advanced two-planarization = oxygen = layer μ without advancing into an emulsification step > j to obtain the semiconductor-based: (Pictured) a good layer between the hard layer and the hard layer; the surface 30: and the flattened thick dioxide Figure 2G shows the pair of first side wall dielectric cushion layers 305a, and the first: the thick second layer After the oxide stone layer 306a and the second planarized thick stone dioxide layer a are anisotropically etched back to a top level of the floating gate layer "", the pair of second sides The wall dielectric pad layer 307a is removed by dry etching using a high-temperature phosphoric acid or a non-aqueous method to form a flat surface. FIG. 2A shows that an inter-gate dielectric layer 301 is formed on the planar surface of FIG. 2G; then, a second conductive layer 311 is formed on the inter-gate two layers 3 1 0. Then, a metal layer 3 丨 2 is formed on the second conductive layer 311. The inter-gate dielectric layer 310 is a silicon dioxide_silicon nitride_T vaporized silicon (0N0) layer, and its equivalent silicon dioxide thickness is between 100 angstroms and angstroms. The second conductive layer 311 is a doped polycrystalline silicon or doped non-silicon layer and is deposited by the LPCVD method. The metal layer 312 is a copper (Cu) j aluminum (A1) layer formed on a barrier metal or a tungsten (W) layer formed on a barrier metal layer. The barrier metal layer is a titanium nitride (TiN) or nitride button (TaN) layer.

Page 14 1220558 V. Explanation of the invention (ίο) Figure II shows the metal layer 3 1 2, the second conductive layer 3 1 1, the inter-gate dielectric layer 3 1 0, and the floating gate layer 3 0 2b. A second mask photoresist step (PR2) (not shown) is simultaneously formed and etched to form a complex digital line 312a / 3 1 1 a and the complex common source / drain diffusion bit line 3 0 4b / 3 0 4a are perpendicular to each other, and the floating gate layer 3 2 b is etched to form a pair of separated floating gates 3 2 c within each of the two-bit floating gate cells. It is worth mentioning here that an ion implantation process implants a moderate dose of dopants across the penetrating dielectric layer in an auto-aligned manner to form an adjacent word line (3 1 2 a /

3 1 1 a) between the first conductive type isolation implantation region 3 1 3 a as a diffusion isolation region, as shown in FIGS. 3A to 3D. It must be emphasized here that the above-mentioned isolation planting area 3 1 3 a may be replaced with a shallow groove (not shown) to form a shallow groove isolation (ST I) area like the isolation planting area 3 1 3 a Marked. It can be clearly seen here that only two mask photoresist steps (PR1 and PR2) are required to produce a two-bit floating gate cell of the present invention and a non-contact point indicated by a dashed square in FIG. Parallel co-source / non-diffused bit line flash memory array, and the cell size of each bit can be made equal to 2F2 °

FIG. 3A shows a top-view layout diagram of a contactless parallel common source / non-diffused bit line flash memory array according to the present invention. A cross-sectional view along an AA ′ line is shown in FIG. 2. In I; a cross-sectional view along a line BB 'shown in FIG. 3A is shown in FIG. 3B; a cross-sectional view along a line CG' shown in FIG. 3A is shown in FIG. C; and a cross-sectional view along a line D-D 'shown in FIG. 3A is shown in FIG. 3D. Figure 3A shows a complex common source / drain diffusion bit line 3 0 4b / 3 0 4a (BL ’s

Page 15 l22〇558 V. Description of the invention (11)) are alternately formed on a semiconductor substrate 300; and each gate region (GR) is located in the common source / drain region (cs / DR) Between the plurality of metal word lines 3 1 2 a together with the control gate layer 3 1 1 a, the inter-gate dielectric layer 3 1 〇a, and the separation floating chamber 3 0 2 c are simultaneously formed and anisotropically I Insect engraved with the common source /; and the diffusion bit line 3 0 4 b / 3 0 4 a (BL 's) are perpendicular to each other; a complex pair of floating gates are formed on the complex metal word line 3 1 2 a Below each of them, there is a selective gate dielectric layer 3 0 9b formed between the pair of floating gates 3 0 2 c; and a plurality of isolation implanted regions 3 1 3 a are formed on the phase in an automatic alignment manner. The adjacent metal word line 3128 and the adjacent common source / drain region (between 〇8 / 01〇. Figure 38 shows a double-bit floating gate cell as indicated by a dashed square, and its unit cell size is equal to 4F 2 , Where the common source / drain diffusion region (CS / DR), the gate region (GR), the width of the metal word line, and the width of the isolation region are based on a minimum line width (F) of the technology used Therefore, the cell size of each bit is equal to 2 F 2. Fig. 3B shows a cross-sectional view along a line BB 'shown in Fig. 3A. The source / non-diffusion region 304 b / 304a is formed as a common source / drain diffusion bit line (BL) on a surface portion of the semiconductor substrate 3 0 0; the penetrating dielectric layer 3 0 1 a is formed on The common source / drain diffusion region 30 4b / 3 0 4a; the etched back first planarized thick silicon dioxide layer 3 0 6 b is formed on the penetrating dielectric layer 3 0 1 a; and The plurality of metal word lines 3 1 2a together with the control gate layer 3 1 1 a and the inter-gate dielectric layer 3 1 0a are simultaneously formed by a second mask photoresist step (PR2) (not shown) and Anisotropy is left for a moment. Figure 3C shows a cross section along a CC line marked in Figure 3A

1220558 V. Description of the invention (12) Figure, wherein the plurality of metal word lines 3 1 2 a together with the control gate layer 3 1 1 a, the inter-gate dielectric layer 3 1 0 a, and the pair of floating gates 3 0 2 c is simultaneously formed and anisotropically etched by the second mask photoresist step (PR 2); and the plurality of isolation implanted regions 3 1 3 a are formed on adjacent metal word lines 3 1 The surface portion of the semiconductor substrate 300 between 2a. FIG. 3D shows a cross-sectional view along a line D-D, marked in FIG. 3A, in which the plurality of metal word lines 3 1 2 a together with the control gate layer 3 1 1 a and the inter-gate dielectric layer 31 Oa is simultaneously formed and anisotropically etched through the second mask photoresist step (PR2) and is formed on the selective gate dielectric layer 3 0 9 b; the ion implantation region 3 0 8 a is formed between the pair of floating gates 3 0 2 c and is placed under each of the complex digital lines 3 1 2 a / 3 1 1 a; and the isolation planting area 3 1 3 a Formed between adjacent metal word lines 3 1 2 a and adjacent common source / drain regions (CS / DR). The ion implantation area includes at least one shallow ion implantation area as indicated by a dashed line as an adjustment of the threshold voltage and a deep ion implantation area as indicated by the number X X X to form a penetration prohibited area. It is worth emphasizing here that the formation of the isolation implantation region 3 1 3a under the selective gate dielectric layer 3 0 9 b is due to the invasion of dopants implanted by the metal word line 3 1 2 a. )caused. FIG. 3E shows a schematic circuit representation of the parallel common source / diffusion bit line array of the present invention, where the complex common source / drain diffusion bit line 3 0 4 b / 3 0 4 a is formed alternately. On the surface of the semiconductor substrate 300; a plurality of double-bit floating gate cells (201 ~ 2 15) are alternately formed on the complex common source / drain diffusion line 3 0 4b / 3 0 4a Between; and the plurality of metal word lines (WL's) and the plurality of common source / diffusion bit lines 304b / 3 04a

Page 17 1220558

5. Description of the invention (13) (BL 's) are vertical to each other. Each of the plurality of double-bit floating gate cells (201 ~ 205) includes at least a pair of floating gate transistors and a selective gate transistor located between the pair of floating gate transistors, and a small circle is formed in the double Each of the floating gate cells is below the selection gate region to represent the ion implantation region 308a. It can be clearly seen here that the selective gate transistor located in each of the two-bit floating gate cells can be used to avoid the super scrub problem of the parallel common source / drain-spread bit line array of the present invention. Please refer to FIG. 4A to FIG. 4C, which show the simplified manufacturing steps of manufacturing a two-bit floating gate cell and a contactless parallel separation source / diffusion bit line array of the present invention after FIG. 2C. Sectional view. Figure 4A shows the penetrating dielectric layer 3 0 1 system between the pair of first side wall dielectric pads 3 0 5 a in each of the common source / drain (CS / DR). It is removed by an anisotropic dry etching method; then, the semiconductor substrate 3 0 0 is etched anisotropically to form a shallow surface between the pair of first side wall dielectric pads 3 5 5 a. A groove; then, a first planarized thick silicon dioxide layer 3 0 6 c is formed in a gap between the pair of first side wall dielectric pads 3 5 a. Figure 4A again shows that the formed first-mask dielectric layer 3 0 3 a is selectively removed by using 1¾ thermal linoleic acid or anisotropic dry etching method; then, a pair of second side wall dielectrics The underlayer 3 0 a is formed on the side wall of each of the formed first mask dielectric layers 303 a separately. The first planarized thick silicon dioxide layer 3 06 c is composed of silicon dioxide, phosphor glass, borophospho glass, and is deposited using LPCVD, HDPCVD, or PECVD methods. The second side wall dielectric pad layer 307a is composed of silicon nitride and is deposited by the LPCVD method. It is worth mentioning here that when the first planarized thick silicon dioxide layer 3 0 6 c is not formed,

Page 18 1220558 V. Description of the invention (14) Before the thin groove (not shown) can be formed on the surface of the shallow groove. In addition, it can be clearly seen that each of the common source / drain diffusion regions (CS / DR) shown in FIG. 4A is formed by the first planarized thick silicon dioxide over each of the shallow grooves. The layer 3 0 6 c is separated to form two separate source / drain diffusion regions 3 0 4 c. According to the process steps shown in FIG. 2E to FIG. 2G, FIG. 4A can be further fabricated into the structure shown in FIG. 4B, in which the first planarized thick silicon dioxide layer 3 in each of the shallow grooves 3 0 6 c is etched back to form an etched back first planarized thick silicon dioxide layer 306 d.

FIG. 4C shows that an inter-gate dielectric layer 3 1 0, a second conductive layer 3 1 1, and a metal layer 3 1 2 are sequentially formed on a flat surface shown in FIG. 4B. The steps of the second mask photoresist (PR 2) described in Section I are simultaneously formed and etched to form a complex digital line 3 1 2 a / 3 1 1 a and the separated source / drain diffusion bit line 3 0 4 c is perpendicular to each other. Similarly, the semiconductor substrate 3 0 0 located between the complex digital line 3 1 2 a / 3 1 1 a and the complex common source / drain region (CS / DR) is implanted with a dopant to form the isolation cloth. Planting area 3 1 3 a, as shown in Figure II. A dotted square shown in FIG. 4C represents a two-bit floating gate cell of the present invention. It can be clearly seen here that the limiting cell size of the above two-bit floating gate cells is equal to 4 F 2, and the limiting cell size of each bit is equal to 2 F 2. FIG. 5A shows a schematic top-view layout diagram of the contactless parallel separated source / drain-diffusion bit line array of the present invention. A cross-sectional view along the line AA ′ shown in FIG. 5A shows In Figure 4C. It can be clearly seen from FIG. 5A that the complex separated source / sink diffusion bit lines (BL Γ s and BL2 ′ s)

Page 19 1220558 V. Description of the invention (15) 3 0 4c is formed in parallel and perpendicular to the complex number line (WL 's) 31 2a / 31 la. Each of the common source / drain regions (CS / DR) includes at least one etched back first planarized thick silicon dioxide layer 3 06 d formed on a shallow groove and a pair of separated source / drain diffusion regions ( 611 and ^ 2). The isolation planting area 3138 is located between the adjacent word line 3 1 2 a / 3 1 1 a (WL) and the adjacent etched back first side wall dielectric pad layer 3 0 5 b. The unit cell size of a two-bit floating gate cell is equal to 4 F 2 as indicated by a dashed square, and the unit cell size of each bit is equal to 2 F 2. FIG. 5B shows a cross-sectional view along a line BB ′ indicated in FIG. 5A, in which an etched back first planarized thick silicon dioxide layer 3 0 6 d is formed in each shallow groove and the The complex digital lines 3 1 2a / 3 11 a together with the inter-gate dielectric layer 3 1 0 a are formed on the etched back first planarized thick silicon dioxide layer 3 0 6 d. FIG. 5C is a cross-sectional view taken along a line CC ′ shown in FIG. 5A, in which a separation source / drain diffusion region 3 0 4 c is formed on a surface portion of the semiconductor substrate 300 An etch-back first side wall dielectric pad layer 3 0 5b is formed on the penetrating dielectric layer 3 0 1 a and is formed on the separation source / drain diffusion region 3 04c; and the complex digital line 312a / 31la together with the inter-gate dielectric layer 3 1 0 a are formed on the etched back side wall dielectric pad layer 3 5 b. FIG. 5D shows a cross-sectional view taken along a line D-D ′ shown in FIG. 5A, wherein the complex digital line 312 a / 311 a, the inter-gate dielectric layer 310 a, and the pair of floating gates 3 0 2 c They are simultaneously formed to form a plurality of stack gates on the penetrating dielectric layer 3 0 1 a, and the isolation planting region 3 1 a is formed between adjacent stack gates. Figure 5E shows a section along line E-E, marked in Figure 5A

Page 20 1220558 V. Description of the invention (16) Figure, where the above-mentioned complex digital line 3 1 2 a / 3 1 1 a together with the inter-gate dielectric layer 3 1 0 a is formed on the selective gate dielectric layer 3 0 9 b; the ion implantation area 3 0 8 a is formed below the complex digital line 3 1 2 a / 3 1 1 a; and the isolation implantation area 3 1 3 a The invasion of impurities is located between the adjacent word lines 3 1 2 a / 3 1 1 a. The ion implantation region 3 0 8a includes at least one shallow ion implantation region as indicated by a dashed line as an adjustment of the threshold voltage and a deep ion implantation region as indicated by X X X to form a resistance forbidden region. FIG. 5F shows a schematic circuit representative diagram of the contactless parallel separation source / diffusion bit line array of the present invention, in which a plurality of double-bit floating gate cell units in each row are formed on a pair of separation source / diffusion Between the bit lines (BL1 and BL2) 3 04c, the complex digital line 312a / 31la and the complex separated source / diffusion bit line 304c (BL1's and BL2's) are perpendicular to each other. It can be clearly seen here that each bit of a two-bit floating gate cell can be written and scrubbed independently, and each bit can transfer electrons by the Fowler-Nordheim penetration method The separation source / drain diffusion region 304c penetrates into the floating gate 302c through the penetrating dielectric layer 30a. Based on this, the double-bit floating gate cell structure of the present invention and its non-contact flash memory array can provide the following features and advantages: (a) The double-bit floating gate cell structure of the present invention can provide a unit cell The cell size of each cell is equal to 4F and the size of each cell is equal to 2F. (B) The double-bit floating gate cell structure of the present invention provides an automatic alignment to select the gate region with a high threshold voltage to avoid over scrub problems. And one

Page 21 1220558 V. Description of the invention (17) Efficiently penetrate the prohibited area to further reduce the cell size. (c) The double-bit floating gate cell structure and the contactless flash memory array of the present invention are manufactured by an automatic alignment method, and only two mask photoresist steps are required. Tiller's Memories. The wiring of the fast-resistance fast-electric point has no wording. It is issued every time. It is low to reduce the d C width layer. Ηη · ι. The lineup recalls the electric flashes of the Invisible Lightning Line of the Electricity Flashes, which are connected in a short time. (E.g., the expansion of the Flash Lines of the Expansion of the Flashes. The flash line of the Expansion of the Flash Lines, and the write-in point for the source and operation The asexual bullets are clearly issued for this issue.} F CArray—ΐ} ΊΠΊ As shown in the limit map, the internal map or book is not covered, as an example. Attached.虽 Although Chen Chen indicated that the generation of hair is the only form, but the shape and shape are the same, it is reconciled, and the real, realistic, and real human hair is reconciled. Starting from the action, it ’s more, but it ’s more detailed, but the

1220558 on page 22 Brief description of the drawings Figures 1A and 1B show the schematic structure of the prior art, of which Figure 1A shows a cross-sectional view of a two-bit floating gate flash memory cell and Figure 1B shows the A top view of a two-bit floating brake flash memory cell. Figures 2A to 2I show the manufacturing steps and cross-sectional views of manufacturing a two-bit floating gate cell structure and a contactless parallel common source / diffusion bit line array of the present invention. FIG. 3A shows a schematic top-view layout diagram of the contactless parallel common source / drain diffusion bit line array of the present invention.

FIG. 3B to FIG. 3D show various cross-sectional views indicated in FIG. 3A, of which FIG. 3B shows a cross-sectional view along a line B-B 'indicated in FIG. 3A; FIG. 3C shows FIG. A cross-sectional view taken along line A-C 'indicated by A; and FIG. 3D shows a cross-sectional view taken along line D-D' indicated by FIG. 3A. Figure 3E reveals a circuit representation of a two-bit floating gate cell structure and a contactless parallel source / diffusion bit line array of the present invention.

FIG. 4A to FIG. 4C show the simplified process steps and cross-sectional views of FIG. 2C, which are subsequent to FIG. 2C, for manufacturing the contactless parallel source / drain diffusion bit line array of the present invention. # FIG. 5A shows a schematic top-view layout diagram of the contactless parallel source / drain diffusion bit line of the present invention. Figures 5B to 5E show various cross-sectional views marked in Figure 5A, where Figure 5B shows a cross-section along a B-B 'line marked in Figure 5A

1220558 on page 23 is a simple illustration of a diagram; Figure 5C shows a cross-section view along a CC line shown in Figure 5A; Figure 5D shows a D-D mark along Figure 5A A cross-sectional view of the 'line'; and FIG. 5E shows a cross-sectional view along the line E-E 'indicated in FIG. 5A. Fig. 5F shows a circuit representative diagram of a contactless parallel separation source / drain diffusion bit line according to the present invention. Representative drawing number description: 3 0 0 semiconductor substrate 301a penetrates dielectric layer 30 1b penetrates dielectric layer 3 0 2b floating gate layer 3 0 2 c floating gate 3 0 3 first mask dielectric layer 3 0 3a One mask dielectric layer 3 0 4a common source / drain diffusion region 3 0 4b shallow highly doped common source / drain diffusion region 3 0 4 c separated source / non-diffused region 3 0 5 a first side wall dielectric pad Layer 3 0 5 b cash back first side wall dielectric plutonium layer 306 a first planarized thick silicon dioxide layer 306 b etch back first planarized thick silicon dioxide layer 307 a second side wall dielectric cushion layer 308 a ion Distribution area 309a Second planarized thick silicon dioxide layer 3 0 9 b Select gate dielectric layer 3 1 0 a Inter-gate dielectric layer 3 1 1 a Control gate layer 3 1 2 a Metal word line 3 1 3 a Isolation Planting area

Page 24

Claims (1)

1220558 VI. Scope of patent application 1. A double-bit floating gate flash cell structure including at least: a semiconductor substrate of a first conductivity type; a cell region is formed on the semiconductor substrate, and the above-mentioned cell The area contains at least one gate area formed between a common source area and a common drain area. The gate region includes at least a pair of floating gates defined by a pair of second side wall dielectric pads and a selective gate dielectric layer is formed between the pair of floating gates, one of which penetrates the first of the dielectric layers. A portion is formed under the pair of floating gates and an ion implantation region of the first conductivity type is formed on a surface portion of the semiconductor substrate under the selective gate dielectric layer; the common source / drain region A common source / drain diffusion region including at least the second conductivity type is formed on a surface portion of the semiconductor substrate, and a pair of etch-back first sidewall spacers is formed on a second portion of the penetrating dielectric layer. Over a portion of the surface, and an etched back first planarized thick silicon dioxide layer is formed between the pair of etched back side wall dielectric pads; A word line is placed on an inter-gate dielectric layer and is formed over the pair of floating gates and the selective gate dielectric layer in the gate region and the etch-back first of each of the common source / drain regions. A planarized thick silicon dioxide layer and the pair of etched back side wall dielectric pads; and two cell isolation regions are formed outside the word line and between the common source and the region . 2. The two-bit floating gate cell structure described in item 1 of the scope of the patent application, wherein the zigzag line includes at least one metal layer placed on a doped complex Page 25 1220558 VI. Scope of patent application On the stone or doped amorphous stone layer, the inter-gate dielectric layer includes at least one silicon dioxide-silicon nitride-silicon dioxide (0N0) layer. 3. The double-bit floating gate cell structure described in item 1 of the patent application scope, wherein the cell isolation region includes at least an isolation implanted region of the first conductivity type formed on a surface portion of the semiconductor substrate Serving. 4. The double-bit floating gate cell structure described in item 1 of the patent application range, wherein the cell isolation region includes at least one shallow groove isolation (ST I) region formed on a surface portion of the semiconductor substrate . 5. The double-bit floating gate cell structure described in item 1 of the scope of patent application, wherein a shallow highly doped common source / drain diffusion region of the second conductivity type described above forms within the common source / drain diffusion region It is formed by implanting doping across the penetrating dielectric layer between the pair of first side wall dielectric pads. 6. The double-bit floating gate cell structure described in item 1 of the scope of the patent application, wherein a shallow groove is formed in the pair of Huiyu first side wall dielectric cushion layers A surface portion of the semiconductor substrate therebetween to separate each of the common source / drain diffusion regions to form two separate source / drain diffusion regions and the etched back first planarized thick silicon dioxide layer is formed on the Over shallow grooves. 7. The double-bit floating gate cell structure described in item 1 of the scope of the patent application, wherein the ion implantation area is located at least under the selective gate dielectric layer. Page 26 1220558 VI. Scope of patent application Contains a shallow ion implantation area as a threshold voltage adjustment and a deep ion implantation area to form a punch-through-stop. 8 CP one type quickly connect without the first type guide. It contains as little as the meaning of the words. The base of the board is changed one by one and the shape of the area is closed. The number of steps is blocked. Covering the first one of the board, half of the gates in the base body area should be restored to the shape of the second type, the second one should contain as little as; The formation system is divided into two parts: a plate, a substrate, and an electrical surface on one side of the surface of the wall. The base body of the body is guided by a half of the body. The source is a wall, the source side, the side on the common side, a pair of surfaces on the first surface, a part of the area, and the second part spreading over the second channel, a co-doped layer, a source, and a hybrid. Bu Jie Gao passes through the shallow and meridian and passes through the inner area of the pattern area to form an electric divergence guide to expand and separate. ^ 一 | ^ ¢ 0 A wall of the etched side of the wall and a back of the wall The two layers of the silicon layer are electrically separated from each other through the inter-layer oxygen of the silicon; The surface of the gate is borrowed from the gate to the floating layer of the floating drift. The gate selection number is one that includes a bag and the number from the bottom to the fixed layer. The number of sides of the gate of each area of the gate is doubled. The board of choice of the CLP's gate is based on the body's formation of the semi-system, the plant's cloth, and the floating pair of floating pairs. The number of pairs of parts that floated and floated through each of the gates that pass through the gates is repeatedly shown from the base of the shape of the plate to the base of the body. 27 pages 1220558 Page 28, 1220558 VI. Application scope of patent 1 2. The contactless flash memory array as described in item 8 of the scope of patent application, wherein the above-mentioned cell isolation region includes at least one shallow groove isolation (ST I) region. On a surface portion of the semiconductor substrate. 1 3. A contactless flash memory array comprising at least: a semiconductor substrate of a first conductivity type; a plurality of gate regions are formed and alternately formed on the semiconductor substrate by a first mask photoresist step. Above, each of the plurality of gate regions is formed between the common source / drain regions; each of the common source / drain regions includes at least the pair of separated source / drain diffusion regions of the second conductivity type by A pair of first side wall dielectric pads is defined, a shallow groove is formed in a surface portion of the semiconductor substrate between the pair of first side wall dielectric pads, and a pair of first sides A bet dielectric layer is formed on a second partial surface of a penetrating dielectric layer, and a back #first planarized thick dioxide layer is formed on the pair of back #first side wall Each of the plurality of gate regions includes at least a plurality of even pairs of floating gates defined by a pair of first side wall dielectric mats and a selective gate dielectric. A layer is formed at least on the semiconductor substrate between the plurality of even-pair floating gates, and An ion implantation region of the above-mentioned first conductivity type is formed on a surface portion of the semiconductor substrate under the selective gate dielectric layer and a first portion of the penetrating dielectric layer is formed at least on Under the plural pairs of floating gates; Page 29 1220558 VI. Patent application scope The complex digital line is placed on the dielectric layer between the plurality of gates and is formed perpendicular to the separation source / diffusion diffusion region and is placed in the plurality of even gates in each of the plurality of gate regions. A pair of etched first side wall dielectric pads and the etched first planarized thick dioxide layer above the floating gate and the selective gate dielectric layer and placed on each of the common source / drain regions On a portion of the surface of the silicon layer, wherein the above-mentioned complex digital lines, the plurality of inter-gate dielectric layers, and the plurality of even-pair floating gates are simultaneously formed and etched by a second mask photoresist step; and The plurality of cell isolation regions are respectively formed on the surface portions of the semiconductor substrate located outside the complex digital line and between the common source / drain regions. 14. The non-contact flash memory array as described in item 13 of the scope of patent application, wherein the above-mentioned ion implantation region is placed under the selective gate dielectric layer and includes at least one shallow ion implantation region as a threshold. The voltage is adjusted and a deep ion implantation area is formed to form a forbidden region. 1 5. The contactless flash memory array as described in item 13 of the scope of patent application, wherein each of the above-mentioned pair of separated source / non-diffused regions includes at least one shallow highly doped diffusion region formed in a lightly doped region Within the diffusion zone. 16. The non-contact flash memory array as described in item 13 of the scope of patent application, wherein each of the above-mentioned multiple digital lines includes at least one metal layer placed on a barrier metal layer and then formed in a doping Over polycrystalline silicon or doped amorphous silicon. Page 30 1220558 VI. Application for patent scope 1 7. The contactless flash memory array as described in item 13 of the scope of patent application, wherein the above-mentioned cell isolation region includes at least one isolation implant of the first conductivity type A region is formed on a surface portion of the semiconductor substrate. 1 8. The contactless flash memory array as described in item 13 of the scope of patent application, wherein the cell isolation region includes at least one shallow groove isolation (ST I) region formed on a surface portion of the semiconductor substrate Serving. 19. The contactless flash memory array as described in item 13 of the scope of patent application, wherein the inter-gate dielectric layer includes at least one silicon dioxide-silicon nitride-silicon dioxide (0N0) layer and the The penetrating dielectric layer includes at least one thermal silicon dioxide layer or one nitrided stone dioxide layer. 20. The contactless flash memory array as described in item 13 of the scope of the patent application, wherein the selective gate dielectric layer described above includes at least one stone dioxide layer or one silicon nitride layer. Page 31