TW591763B - Scalable dual-bit floating-gate flash cell structure and its contactless flash memory arrays - Google Patents

Abstract

A scalable dual-bit floating-gate flash cell structure comprises a gate region being formed between common-source/drain regions, wherein the gate region comprises a pair of scalable floating-gate conductive islands with a pair of intergate dielectric layers being formed on their top surfaces and a pair of poly-oxide layers being formed over their inner sidewalls, a gate dielectric layer being formed between the pair of scalable floating-gate islands and on a middle portion of a semiconductor substrate, an implant region being formed under the gate dielectric layer, and a planarized control-gate conductive island being formed on the pair of intergate dielectric layers and the gate dielectric layer. The common-source/drain region comprises a common-source/drain diffusion region or a pair of buried source/drain diffusion regions. Based on common/buried source/drain diffusion region, two contactless flash memory arrays are disclosed.

Description

591763 V. Description of the invention (1) (1) Technical field to which the invention belongs The present invention relates to a dual-bit (dua 1-bit) floating gate flash memory cell and its flash array. The structure of miniaturized two-bit floating gate flash memory cells is related to the contact less flash memory array. (2) The conventional flash memory elements of the prior art can basically be divided into two categories: a stack-gate flash cell structure and a split-gate (sp 1 11 -ga te) flash Cellular structure. The above-mentioned stacked gate flash cell structure is recognized as a cell of an electric crystal, and the gate length of one cell can be defined using a minimum line width (F) of the technology used. The above-mentioned gated flash cell structure includes a floating gate and a selection gate system which is recognized as a 1.5 cell cell. Therefore, the above-mentioned stacked flash cell structure is often used to form a high-density flash memory system. The above-mentioned stacked gate flash cell structure can be added in series to form a type with co-source / non-diffusion regions. High-density non-type (NAND_type) fast flash: Ji Yi array 'However, because the structure's series resistance is larger, its reading speed is faster.' The above-mentioned stack gate flash cell structure can be added in parallel to form a non-or-type (_-type) flash memory array from = hot electron injection_) as a write = m fine t element When the gate length is increased by 1 and the size is reduced, the punch-through effect (punch-through effec 10 1 L is a major concern 591763 V. Invention description (2). In addition, a non-or type flash memory array The over-erase problem of the flash cell structure of the stack gate requires a more complex logic circuit to verify and scrub. The above-mentioned split flash cell structure has a selective gate to avoid the over scrub The problem is usually used to form a non-or flash memory array and the middle channel hot electron channel (MCHE I) is used as a writing method to increase the writing efficiency. However, its cell size is smaller than that of a non-flash. The cell size of a memory array is much larger. Therefore, a flash memory cell structure has taken advantage of the stack gate cell structure and the advantages of the gated cell structure to become a mainstream development. A typical example of the previous technology See Figure 1A and Figure 1B, where two stacked gate cell structures and a selective gate system are used to form a two-bit floating gate flash memory cell structure. Now see Figure 1A, two stacked The stack gate structures 20 G and 2 2 G are separated by a selection gate 24G and two common N + / N- diffusion lines 20A and 22A are formed as bit line systems on each side of the stack gate structure. FIG. 1B shows a top-view layout shown in FIG. 1A, in which a third polycrystalline silicon layer 28 is formed as a selective gate system on the total N + / N _ diffusion lines 2 0 A, 2 2 A And control gates 20 C, 2 2 C. As can be clearly seen from Figure 19 and Figure 1B, this structure requires four mask photoresist steps to form the cell and each bit The cell size is limited to 4 F 2 and its cell size is equal to the size of a non-flash memory array that uses the stack gate to memorize the cell structure. However, it is the same as the existing non-or flash type or non-or type. Compared with flash memory arrays, this structure has some drawbacks: it is located between the selection gate (word) line and the control gate line It has a large stray capacitance, located election

591763 V. Description of the invention (3) Large stray capacitance between the selective gate (word) line and the bit line, poor isolation between the cell adjacent to the word line, and adjacent word lines and adjacent bits Weak isolation between lines. Therefore, a main object of the present invention is to provide a miniaturizable two-bit floating gate flash memory cell structure having a micronizable cell size and a size of each bit less than 4F2. Another object of the present invention is to manufacture the miniaturizable double-bit floating gate flash memory cell structure and its contactless buried diffusion bit line array with fewer mask photoresist steps. A further object of the present invention is to provide a small stray capacitance between a word line and a buried diffusion bit line. Other objects and features of the present invention will become more apparent in the subsequent detailed description. (3) SUMMARY OF THE INVENTION A flash memory cell structure capable of miniaturizing a two-bit floating gate is formed on a semiconductor substrate of a first conductivity type. At least one gate region is formed in a common source region and a common sink region. between. The above gate region includes at least a pair of miniaturizable floating gate islands formed on a part of a surface of a penetrating dielectric layer, a pair of inter-gate dielectric layers formed on a top surface thereof, and a pair of polycrystalline silicon oxides. An object layer is formed on its inner side wall, an inter-gate dielectric layer is formed between the pair of micronizable floating gate islands and is placed on the middle portion of the semiconductor substrate, and one of the first conductivity type The ion implantation area includes at least a shallow ion implantation area for the adjustment of the threshold voltage and a deep ion 591763. V. Description of the invention (4) The implantation area is formed to form a planar electric control layer. The aforesaid dimples have a common source and a common source scatter area that breaks through the gate with a metal word line to separate them. The connection system and the common source / drain region include an isolation region of the first conductivity type. The semiconductor is formed on the surface portion of the metal word substrate. A semi-conductor of a first first conductivity type of the present invention is alternately formed. And a part of the common source / drain pipeline formed with the complex conductive common source / drain pipeline is formed on the second side wall / drain pipeline; a plurality of elements may be formed at Adjacent common source / number metal word lines and the plurality of planarization control gate conductive island regions are formed on the surface of the plurality of digital lines and the above, wherein the above includes a STI region of the first conductivity type. Prohibited area Electric island-shaped / no area has or does not belong outside of this isolated line. Type contactless substrate is formed under the gate dielectric layer, and is formed between the gate dielectric layer and the gate medium including at least one second conductivity type planarization control gate conductive island with a planarization field oxide layer The integration is straight and a cell isolation area is at least an ion implantation area or a shallow groove partition and is located above the dot flash between the common source / drain area to a number of metal word lines on a pair of second sides. The internal surface of the dielectric pad is micro-scaled and the micro-diffusion can be micro-integrated to isolate the second source from the second source; the two-bit bit lines are linearized and the two-position links between the layers; The small package is a conductive side wall of the vertical side wall and floats between the floating element and the outer isolation planting area. The array contains a coplanar, dielectric surface, and the floating gate is formed from a source. Each of the high-layered and one-field oxygen-guided flashes in the semi-conducting region of the flash cell semi-conducting region or each of the shallow and highly doped material layers is electrically co-sourced to the multiple cell element spacer substrate Groove

591763 V. Description of the invention (5) A second type of contactless flash memory array of the present invention is formed on a semiconductor substrate of a first conductivity type and includes at least a plurality of pairs of source / drain diffusion bit lines alternately. Formed and perpendicular to the plurality of metal word lines, wherein each of the plurality of even-pair common source / drain diffusion bit lines is formed by a pair of second side walls formed above the side walls adjacent to the gate region A planarized field oxide layer between the dielectric pads is used for separation; a plurality of microbitable two-bit floating gate flash memory cells are formed between a pair of source / drain diffusion bit lines; The plural metal word line is related to the plural: the planarization control of the miniaturizable double-bit floating gate flash memory cell, the gate conductive island integrated connection, and the plural cell isolation zone formed on the plural metal word line and the common source A surface portion of the semiconductor substrate outside the / drain region, wherein each of the plurality of cell isolation regions includes at least an isolation ion implantation region or a shallow groove isolation (STI) region of the first conductivity type. (4) Embodiments of the invention Please refer to FIG. 2A to FIG. 2I, which show the manufacture of a micronizable two-bit floating gate flash memory cell structure and a first type of contactless flash memory array of the present invention. Process steps and cross-sectional views. FIG. 2A shows that a penetrating dielectric layer 201 is formed on a semiconductor substrate 200 of a first conductivity type; then, a first conducting layer 2202 is formed on the penetrating dielectric layer. On 2001, an inter-gate dielectric layer 203 is formed on the first conductive layer 202; and a mask dielectric layer 204 is formed on the inter-gate dielectric layer 203. The above-mentioned penetrating dielectric layer 201 is a thermal dioxide layer or a nitrided thermal dioxide

Page 10 591763 V. Description of the invention (6) The siliconized layer has a thickness between 7 Å by chemical vapor deposition (LPCVD) and a low pressure of 300 angstroms. For the above inter-gate dielectric screen, 〇, ff is between 100 angstroms and silicon-silicon dioxide (0N0) or a dioxygen ^ and—a pen emulsified stone—nitrification is between 70 angstroms and 300 angstroms. Mo, special-purpose thickened gasification of dilute silicon ... Using the LPCVD method "=: = layer, system-between 8 0 0 0 angstroms. Mining product, its thickness is between 3000 angstroms and Ϊ = concealed that The mask dielectric layer 204 uses a first mask photoresistor (PR1) to mean a plurality of parallel gate regions (GR) and a plurality of common source / drain regions (GR) located outside the gate regions (GR). cs / DR); then, the mask dielectric layer 204, the inter-gate dielectric layer 203, and the first conductive layer within the complex common source / drain region (CS / DR) are sequentially Using an anisotropic dry etching method to perform removal; then, an ion implantation process is performed in an automatic alignment manner, and a dopant is implanted across the penetrating dielectric layer 2 on the semiconductor substrate. A surface portion of 2 0 0 to form a common source / non-diffusion region 2 0 5 a of a second conductivity type within each of the plurality of common source / drain regions (CS / DR). The common source / drain diffusion region 2 0 5 a includes at least one heavily-doped common source / drain diffusion region or a highly doped common source / drain diffusion region formed in a lightly-doped common region. source, Figure 2C shows a pair of second side wall dielectric spacers 2 0 6a formed on the side wall adjacent to the gate region (GR) and placed on the common source. A portion of the penetrating dielectric layer 201 within each of the CS / DR regions

V. Description of the Invention (γ) The composition on the surface is composed of the Chu and the use of ~ the second side wall dielectric cushion layer 2 0 6a is formed by the silicon dioxide layer 2 0 6 by the PCVD method to deposit, The silicon dioxide layer is deposited on a thick structure surface of the silicon dioxide layer 206 and then etched back. The silicon dioxide layer shown in FIG. 2D shows that the pair is located within the sub-scores; $ 复数 共 源 / Each 201 of the drain region (CS / DR) is removed by dry etching using the penetrating dielectric layer between the non-i side wall dielectric pads 206a and the second conductive layer. Then, The half & ^ 7b between one back is formed on the pair of second side wall dielectric pads 20 6a to perform a distance of 200; then, an automatically aligned Two-lead lightning: the implantation process, a high-dose doped material is implanted within each 107b of CS / DR to form the shallow common doped I / of the complex common source /; The common source / diffusion region is 2 ° 5a, and the original / and diffusion region is 205b. The above-mentioned etched back second conductive layer 20 7b is composed of doped polycrystalline stone and is stacked using the LpcvD method. A second conductive layer 207 is first stacked to fill the pair of second side wall dielectrics. Each gap between the cushion layers 20 6a is then planarized by chemical-mechanical smoothing (CMP) and the shaped mask dielectric layer 2 4a is used as a pol ishing stop. Then, the planarized second conductive layer 20 7a is etched back to form the etched second conductive layer 20 7b within each of the plurality of common source / drain regions (cs〆DR). FIG. 2E shows that a back-contact covering conductive layer 208b is formed on each of the etched-back second conductive layer 207b and a planarized oxide layer 209a is formed on the plurality of common source / negative regions (CS // DR) each gap between the pair of second side wall dielectric pads 206a within each of them. Etch back

591763 V. Description of the invention (8) The second conductive layer 208 b is covered with at least one fsi 2 or tungsten (W) layer and the same process steps for forming the etched back second conductive layer 207b are used to form. The above-mentioned planar oxide layer 209a is made of silicon dioxide, phosphorous glass (P-glass) or greenhouse phosphorous glass (BP-glass) and is enhanced by LPCVD, high-density plasma (HDP) CVD or plasma. (PE) CVD for stacking, first depositing a thick silicon dioxide layer 209 to fill each gap between the second side wall dielectric cushion layer 2 6 a and then using the CMP method to The stacked thick silicon dioxide layer 209 is flattened and the shaped mask dielectric layer 204a is used as a smoothing stop layer. It can be clearly seen here that the etch-back covering conductive layer 208b is placed on top of the etch-back second conductive layer 207b as a highly conductive common source / submerged line (BL) 2 0 8b / 2 0 7b. When the junction depth of the buried layer co-source / drain-diffusion area of a micronized cell is 2 0 5 b / 2 0 5 a is added to the micro-scale, the far south conductive co-source / drain line (BL) 2 0 8 b / 2 0 7 a can greatly reduce the stray series resistance of the buried common source / drain diffusion bit line 205b // 205a. FIG. 2F shows that the shaped mask dielectric layer 204a within each of the plurality of gate regions (GR) is selectively removed by using an anisotropic dry etching method or a wet #etching method of hot phosphoric acid. ; Then, a pair of first side wall dielectric pads 2 1 0a is formed on a side wall adjacent to the second side wall dielectric pads 2 0a and is placed in the plurality of gate regions (GR). On each part of the surface of the formed inter-gate dielectric layer 2 0 3 a; then, the formed inter-gate dielectric layer between the pair of first side wall dielectric pads 2 1 0 a The electrical layer 2 3 a and the formed first conductive layer 2 1 a are sequentially removed using an anisotropic dry etching method, and then an ion implantation process is performed in an automatic alignment manner, and Dopants are implanted across the penetrating dielectric layer 201a to the pair of first side wall dielectrics.

IHHI page 13 591763 V. Description of the invention (9) A surface portion of the semiconductor substrate 2000 between the electron-emitting layers 210a to form an ion implantation region 211a of the first conductivity type. The above-mentioned first side wall dielectric plutonium layer 21a is composed of silicon nitride and is stacked using the lpcvd method. Its plutonium layer width is used to define a miniaturizable floating gate area (SFGR) and to define the location A selection zone (SGR) between a pair of miniaturizable floating gate zones (SFGR). The above-mentioned ion implantation area 2Ua includes at least a shallow ion implantation area as indicated by a dashed line as a threshold voltage (thresh volt-volt age) adjustment and a deep sub-value distribution area as indicated by XXX to form a PUnch-through stop. FIG. 2G shows that the penetrating dielectric layer 201 located between the pair of first side wall dielectric pads 2a and 0a is added using an anisotropic dry etching method or a diluted hydrofluoric acid bubble immersion method. Pre-removed; then, a thermal oxidation process is performed to form a gate dielectric layer 2 1 3 and said semiconductor substrate 2 0 0 between the pair of first side wall dielectric pads 2 1 〇a is simultaneously formed A polycrystalline silicon oxide layer 212 is said on each inner side wall of the shaped first conductive layer 2 0 2 b within each of the plurality of gate regions (GR). Figure 2 (a) shows the pair of first side wall dielectric pads 2 1 0a located within each of the plurality of gate regions (GR), which are added and removed using hot phosphoric acid; then, a planarized third conductive layer 2 14a is used to fill a gap within each of the plurality of gate areas (GR). The above-mentioned planarized third conductive layer 2Ha is composed of doped polycrystalline silicon and is stacked by LPCVD. First, a thick second conductive layer 2 1 4 is stacked to fill each of the plurality of gate regions (g R). A two-gap within one is then planarized by using the CMP method or back-up technology to thicken the stacked third conductive layer 2 1 4. It is worth noting here that the planarization

Page 14 591763 V. Description of the Invention (two) The second conductive layer 214a can be implanted with a high-dose dopant of the second conductivity type to add high doping. '' Figure I shows that a metal layer 215 is formed on a flat surface as shown in Figure 2n and is formed by a second mask photoresist (pR2) step (not shown) to define A common metal word line (BL) 215a 'that is perpendicular to each other with the multiple buried layer common source / diffusion bit lines 2 08b / 2 0 7b; and then, located within each of the multiple gate regions (G r) The planarized third conductive layer 2 1 5 a between adjacent metal word lines 2 1 5 a, the inter-gate dielectric layer 2 0 3 b, and the polycrystalline spar oxide layer 2 1 2 b and the formed first conductive layer 202 b are sequentially removed by using a non-specific dry etching method, and then an ion implantation process is performed in an auto-aligned manner to implant the dopant A surface portion of the semiconductor substrate 200 between an adjacent common source / drain region (CS / DR) and an adjacent metal word line to form the first-conduction-type ion-implanted region 2 1 6 a (not shown) ). The above metal layer 215 includes at least a copper (cu) or aluminum (A1) layer placed on a barrier metal layer, a tungsten (ψ) layer formed on a barrier metal layer, or a tungsten silicide (WS i 2) layer . It is worth noting here that the isolated ion implantation region 2 1 6 a can be replaced by a shallow groove isolation ($ I) region and the penetrating dielectric layer 20 is firstly used in an automatic alignment manner. 1 b and the inter-gate dielectric layer 2 1 3 a are removed, and then the semiconductor substrate 2 0 0 is etched to form a shallow groove. Referring now to FIGS. 3A to 3F, a brief illustration of the miniaturizable double-bit floating gate flash memory cell and its non-contact flash memory array is disclosed. FIG. 3A shows a schematic top-view layout of the miniaturizable double-bit floating gate flash memory cell structure and its first type of contactless flash memory array.

Page 15 591763 V. Description of the invention (11) A cross-sectional view along line A_A, shown in FIG. 3A is shown in FIG. 2I; a line along a B_β, line shown in FIG. 3A A cross-sectional view is shown in FIG. 3B; a cross-section shown in FIG. 3A along a line c-c, and a cross-section is shown in FIG. 3C. A cross-sectional view is shown in FIG. 3D; a cross-sectional view along the line EE shown in FIG. 3 is shown in FIG. 3E; and FIG. 3F shows the miniaturizable double-bit floating gate flash memory. A brief circuit representation of the cell structure and its first type of contactless flash memory array. As shown in FIG. 3A, the multiple buried layer common source / drain diffusion bit line (BL) 2 0 5b / 2 0 5a is covered with a plurality of highly conductive common source / drain lines 2 08b / 2 0 7b and are formed in parallel and It is perpendicular to the plurality of metal word lines (WL) 215 a, wherein each of the above-mentioned plurality of highly conductive common source / drain lines 2 0 8 b / 2 0 7 b is formed on a pair of second side wall dielectric pads A buried common source / drain-diffusion bit line (BL) 2 0 5 b / 2 0 5 a between layers 2 06a and a planarized oxide layer 2 0 9 a are formed on the second side of the pair The side wall dielectric cushion layer is between 2 0 6 a and is placed on the highly conductive common source / drain line 2 08b / 2 07b; the plurality of microbitable double-bit floating gate cells are marked by the dotted X Alternately formed between adjacent common source / drain regions (CS / DR) and integrated with the plurality of metal word lines (WL) 215a through a planarization control gate conductive island 214b; and a plurality of cell isolation regions 21 6a is formed on the surface portion of the semiconductor substrate 2 0 outside the plurality of metal word lines (WL) 2 15a and the common source / drain region (CS / DR), wherein the plurality of cell isolation regions described above 2 0 6 a At least one compartment comprising a (STI) region from the ion implantation isolation region or a shallow recess. Figure 3B shows a high-conductivity common source / drain line 2 0 8b / 20 7b system.

Page 16 591763 V. Description of the invention (12) Co-origination and compound layer in one (WL) 〇Gate 2 0 2c 2 0 2c An adjacent gold part is formed in a common-source / non-diffusive region 2 0 5 a over a highly doped / drain diffusion region 20 5b; a planarized oxide layer 2 0 9a forms over each of the highly conductive common source / drain lines 2 8b / 2 0 7b; A number of metal word lines (WL) 2 1 5a are alternately formed on the planarized oxide 2 9 a. FIG. 3C shows a second side wall dielectric pad layer 2 0 6 a which forms a part of the surface penetrating the dielectric layer 2 0 1 b and a plurality of metal word lines 2 1 5 a which are alternately grounded. Formed on the second side wall dielectric pad layer 2 0 6 a FIG. 3D shows a plurality of metal word lines (WL) 2 15 a and the planarized conductive island 2 1 4 b integrated connection system formed on the The inter-gate dielectric layer 2 0 3 c above the miniaturizable floating gate island is formed on a part of the surface of the penetrating dielectric layer 2 0 1 b; And the isolated ion implantation area 2 1 6 a is formed on the surface of the semiconductor substrate 2 0 0 between the associated word lines (BL) 21 5 a as indicated by XXX. FIG. 3E shows a plurality of metal word lines (WL ) 2 15a is integrated with the conductive island 214b of the planarization control gate and is formed on a damaged surface of the gate dielectric layer 21 3a. An ion implantation area 2 1 1 3 contains at least one shallow ion implantation. The area is indicated by a dashed line as an adjustment of the threshold voltage and a deep ion implantation area is indicated by xxx to form a breakdown prohibited area. Under the planar control gate conductive island 2 1 4b within the gate region (SGR); and an isolation ion implantation region 2 丨 6a is not formed on the adjacent metal word line (WL) as marked with XX χ A surface portion of the semiconductor substrate 2000 between 2 15a.

Page 17 591763 V. Description of the invention (13) Figure 3F shows a schematic circuit representation of the miniaturizable double-bit floating gate flash memory cell structure and its first type of contactless flash memory array. A plurality of highly conductive common source / drain lines (BL) 2 0 8b / 2 0 7b are formed alternately and perpendicular to the plurality of metal word lines (WL) 2 15a; and a plurality of microbitable double-bit floating gate cells (300 ~ 33 5) is alternately formed between adjacent high-conductivity common source / drain lines (BL) 2 08b / 2 07b, in which the plurality of micronizable floating gate cells (30 00 ~ 3 3 5) The two hollow circles within each one are used to represent an ion implantation region 2 1 1 a formed on a surface portion of the semiconductor substrate 2 0 0 within the selection gate region (SGR) .

Please refer to FIG. 4A to FIG. 4D, which reveals the structure of the ## miniaturizable double-bit floating gate flash memory cell structure and the continuation of the second type contactless flash memory array of the present invention. C's process steps and sectional views. ,

FIG. 4A shows that the penetrating dielectric layer 2 01 is located between the pair of second side wall dielectric pads 206a within each of the plurality of common source / drain regions (CS / DR). The non-isotropic dry etching method is used to add and remove; then, the semiconductor substrate 200 is located between two pairs of second side wall dielectric pads 206a. The non-isotropic dry etching method is used to add and remove. Etched to form a shallow groove; then, a planarized field oxide layer (FOX) 2 0 9b is used to fill the pair of first and second common source / drain regions (CS / DR) The gap between the two side wall dielectric ^ layers 206a; then, the shaped mask dielectric layer 204a located within each of the plurality of gate regions (GR) uses a thermostructural acid or anisotropic Dry 'I worming method was used to remove it; then, a pair of first side wall dielectric pads 2 1 g were formed in the adjacent common source / none regions within each of the plurality of gate regions (GR) ( CS / DR) on the side wall and on a gate dielectric layer 2 0a

Page 18 591763 V. Description of the invention (14) Then, the inter-gate dielectric layer between the pair of first side wall dielectric pads 21a located within each of the plurality of gate regions (GR) 203a and the shaped first conductive layer 202a are sequentially removed by using an anisotropic dry etching method; finally, an ion implantation process is performed in an auto-alignment manner to cross the dopants The penetrating dielectric layer 20a located between the pair of first side wall dielectric pads 20a is implanted on a surface portion of the semiconductor substrate 2000 to form a plurality of gate regions ( GR) An ion implantation region 211a of the first conductive channel within each of the GRs. The depth of the shallow groove in the semiconductor substrate 200 is between 300 angstroms and 800 angstroms. The above-mentioned planarized field oxide layer 209 b is composed of silicon dioxide, phosphorous glass (p-glass) or borophosphoric glass (Bp-glass), and is made of LpcvD, high-density plasma enhanced type First, a thick oxide layer is filled in each of the plurality of common source / drain regions (cs / DR), and the gap between the two-wall dielectric spacers 2 0 6a of the flute is used to remove all The thick oxide layer 20 9 is flattened and the shaped mask dielectric screen is used as 5-flattening stop layers. The above-mentioned first side wall dielectric cushion layer; a is composed of silicon nitride and is used The LPCVD method is used for stacking. The thickness of the second to third electron-emitting layer 210 on the surface of the structure is reduced to the thickness of the second layer 210. The above-mentioned ion implantation area 2Ua includes at least one ^ implantation area as a dotted line. The labeled ion ion implantation zone is formed as indicated by the number X xx to form a ::: depth according to the process steps shown in Figure 2G to Figure 2 ", Figure: Zone. It can be easily obtained. It can be clearly seen here that the gate area (GR) in Xin 2 to Fig. 4 D is the same as the gate area shown in Fig. 2 I and: One place

Page 19 591763 V. Description of the invention (15) The common source / diffusion region 2 0 5 a at each of the plurality of common source / no regions (CS / DR) is planarized by one shown in FIG. 4D The field oxide layer 209 b is separated into two buried layer source / drain diffusion bit lines 205c. FIG. 5A to FIG. 5F show the schematic diagrams of the miniaturizable double-bit floating gate flash memory cell structure and the second type of contactless flash memory array, and FIG. 5A shows a brief top view cloth. Figure 5A is shown along Figure 5B, Figure 5C, Figure 5C, Figure 5D, Figure E, and Figure 5F. A cross-sectional view of the line AA 'is shown in the figure. A cross-section view along the line B-B, marked by 5A in 40. A cross-section view along the line B-B, marked by 5A. A along D-D, line indicated by the 5A. A cross-section view along the line e-E 'shown in Figure 58 shows the structure of the miniaturizable two-bit floating gate flash memory cell structure and its second type of contactless flash memory array. A brief circuit representation. FIG. 5A shows that a pair of buried source / drain diffusion bit lines (BL1 / BL2) 205c are formed in each of the plurality of common source / drain diffusion regions (Cs / dR) and are formed by A planarized field oxide layer 209b between a pair of second side wall dielectric pads 206a to add separation; multiple buried layer source / drain diffusion bit lines (BL1 / BL2) 2 0 5c is perpendicular to the complex metal word line (wL) 215a, where the above-mentioned complex micronizable double-bit floating gate flash memory cell cells are controlled by the planarization of the conductive island 2 1 4 b. Is integrated with the complex metal word line (BL) 2 1 5a; and a complex cell isolation region 2168 is formed in the complex metal word line (child) 215 & and the complex common source / drain area (CS / DR ) Other than the surface portion of the semiconductor substrate 2000. Figure 5B shows that a planarized field oxide (FOX) layer 2 0 9b is formed on the I-plane.

Page 591 763

5. Description of the invention (16) A plurality of metal word lines (BL) 2 1 5a are alternately formed on the semiconductor substrate 2 0 0 on the planarized field oxide layer 2 9 b. FIG. 5C shows a second side wall dielectric pad layer 2 0 6 a formed on a penetrating dielectric layer 2 0 1 b and then formed on a buried source / drain diffusion bit line 2 0 5 c A plurality of metal word lines (BL) 2 15a are alternately formed on the second side wall dielectric pad layer 20 6a. FIG. 5D shows that a complex metal word line (Wl) 21 5 a is formed with a planarized control gate conductive island 21 4b integrated connection system located within each of the miniaturizable double-bit floating gate area (SFGR). Above the inter-gate dielectric layer 203 of the demiseable floating gate island 002c; the diffusible floating gate island 002c alternately forms the penetrating dielectric layer 〇1 a part of the surface of b; and a cell isolation region 2 1 6a is formed as one of the semiconductor substrates 200 between adjacent metal word lines (WL) 2 15a as indicated by X χ χ Surface part. A cell isolation region 216a includes at least an isolation ion implantation region or a shallow groove isolation (STI) region of the first conductivity type.

FIG. 5E shows that a plurality of metal word lines (WL) 215a alternately form a part of a gate dielectric layer with the planar control gate conductive island 2ub integrated connection system located within each of the selection gates (SGR). Above the surface; a thin ^ isolation region 216a is formed on the adjacent metal word line 丨 the surface portion of the semiconductor; and an ion cloth = 2 11 a is formed in the selective gate region as described earlier (Below each of the conductive gates 214b inside the control gate. Figure 5F shows the miniaturizable structure and its second type of contactless flash dual-bit floating gate flash memory cell memory. A brief circuit of the array represents 591763. V. Description of the invention (17), in which the complex numbers alternately form a number of scalable micro-planar control gate links; and the (50, 5 2 5) system between 2 0 5 c This shrinks the two-bit drift to separately scrub and form the buried layer source / drain / symmetry and the area diffusion potentials BL1 and BL2 based on this, which can be based on this structure and its non-contact (a) invention. The structure has a pair of structures which can effectively apply the voltage and power (b) of the present invention. There is a first pair of buried layer source / drain-diffusion bit lines (BL1 / BL2) 205c, which are perpendicular to the plurality of metal word lines (WL) 2 15a, and the reset element floating gate flash memory cell (5 0 1 ~ 5 2 5) The conductive island 2 1 4b is integrated with the plurality of metal word lines 2 1 5a to form a multi-miniaturizable double-bit floating gate flash memory cell located at an adjacent buried layer source / sink diffusion site It can be clearly seen in the lines (BL1 // BL2) that each of the plurality of micro-floatable flash memory cells (5 0 ~ 5 2 5) in Figure 5F can be operated with the flexibility of the cell. It is emphasized that the complex common source / drain region (CS // DR) is symmetrical with the buried common source / drain diffusion bit line 204a / 204b and the diffusion bit line 204c. Therefore, the buried layer common source line (BL1, BL2) or the buried layer source / diffusion bit line is interchangeable. The characteristics and advantages of the miniaturizable double bit floating gate cell junction junction flash memory array of the present invention can be It can be summarized as follows: The: Miniaturized double-bit floating gate flash memory cell node micronized floating floating M island can be separated by a selection free area M ϋ ¥ # t + U ^ : Come to write people and have a lower foreign teacher planting area formed on this semiconductor

Sowing λ 丨, Question of Jiaj § Jiyi Cell / ϋ, Charm An ion of conductivity type

591763

V. Description of the invention (18) A middle part of the substrate can be further miniaturized with helmet penetration effect and super scrub problem. (c) The miniaturizable dual structure and the contactless flash memory array of the present invention can be manufactured with fewer mask photoresist steps. The floating junction flash memory cell cell junction provides a plurality of metal word lines by an automatic alignment technology and (d) the contactless flash memory array of the present invention to greatly reduce the word line resistance.

(e) The first type of contactless flash memory array of the present invention provides a high-conductivity common source / submerged pipeline of the mother of the plurality of buried layer common source / non-diffusion regions to substantially reduce the buried bit line. resistance. (f) The first type of contactless flash memory array of the present invention provides a pair of buried source / drain diffusion bit lines within each of the plurality of common source / drain regions to increase the flexibility of cell operation.

Although the present invention is specifically illustrated and described with reference to the attached examples or connotations, it is only a representative statement and not a limitation. Furthermore, the present invention is not limited to the details listed, and those skilled in the art can also understand that changes in various shapes or details are made without departing from the true spirit and scope of the present invention, but also belong to The scope of the invention.

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591763 Schematic illustrations Figures 1A to 1B show a brief illustration of the structure of a conventional two-bit flash memory cell, where Figure 1A shows a cross section along the length of a channel and Figure 1B shows a Top view layout. Figures 2A to 2I show the manufacturing steps and cross-sectional views of the manufacturing of a miniaturized two-bit floating gate flash memory cell structure and the first type of contactless flash memory array of the present invention. FIG. 3A to FIG. 3F show a schematic diagram of the miniaturizable double-bit floating gate flash memory cell structure and the first type of contactless flash memory array, and FIG. 3A shows a brief top view cloth. Create a map and a cross-sectional view along an AA 'line shown in FIG. 3A is shown in FIG. 2I; FIG. 3B shows a cross-sectional view along an BB ′ line shown in FIG. ; Figure 3C shows a cross-section view along a CC line shown in Figure 3; Figure 3D shows a cross-section view along a DD 'line shown in Figure III Am; Figure 3E shows Figure III A cross-section view along an E-E 'line; and FIG. 3F shows the structure of the miniaturizable double-bit floating gate flash memory cell structure and the first type of contactless flash memory array. Representative figure. FIG. 4A to FIG. 4D show the fabrication of a microminiaturized double-bit floating gate flash memory cell structure and its second type of contactless flash memory array in accordance with the present invention. FIG. Illustration. FIG. 5A to FIG. 5F show the schematic diagrams of the miniaturizable double-bit floating gate flash memory cell structure and the second type of contactless flash memory array, and FIG. 5A shows a brief top view cloth. Create a map and a cross-sectional view along an AA 'line shown in FIG. 5A is shown in FIG. 4D; FIG. 5B shows a cross-section along a BB' line shown in FIG. 5A Figure; Figure C shows

Page 591763 The diagram briefly illustrates a cross-sectional view along the line CC-C 'indicated by five A; FIG. 5D shows a cross-section view along the line D-D' indicated by FIG. 5A; 5E shows a cross-sectional view along an E-E 'line shown in FIG. 5A; and FIG. 5F shows the structure of the miniaturizable double-bit floating gate memory cell and its second type of contactless flash A brief circuit representation of a memory array. Representative drawing number description: 2 0 0 semiconductor substrate 201 penetrating dielectric layer 201a / 201b forming penetrating dielectric layer 202 first conductive layer 2 0 2a forming first conductive layer 20 2b floating gate layer 2 0 2 c floating gate island 20 3 Inter-gate dielectric layer 2 0 3a / 2 0 3b / 2 0 3c Formed inter-gate dielectric layer 204 Mask dielectric layer 204a Formed mask dielectric layer 2 0 5 a Common source / drain diffusion region 2 0 5 b Highly doped common source / drain diffusion region 2 0 5 c Buried source / drain diffusion bit line 2 0 6 a Second side wall dielectric pad 2 0 8b / 2 0 7b Highly conductive common source / drain line 2 0 9 a planarized oxide layer 2 0 9 b planarized field oxide layer 2 1 0a first side wall dielectric pad 2 1 1 a ion implanted area 2 1 2 a polycrystalline silicon oxide layer 2 1 3 a Gate dielectric layer 2 1 4a Planar third (control gate) conductive layer 2 1 4b Planar third (control gate) conductive island 215a Metal word line 216a Cell cell isolation zone

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Claims (1)

591763 VI. Scope of patent application 1. A miniaturized double-bit floating gate flash memory cell structure including at least: a semiconductor substrate of a first conductivity type; a gate region through a first mask photoresist step To define a gate region formed on the semiconductor substrate and located between a common source region and a common drain region; the gate region includes at least a pair of scaleable floating gate islands formed by a pair of first side wall dielectric pads Defined on a side wall of the common source / drain region formed on a portion of the surface of a penetrating dielectric layer and having a pair of inter-gate dielectric layers formed on a top surface thereof and a pair of complex crystals A silicon oxide layer is formed on the inner side wall, a gate dielectric layer is formed on the semiconductor substrate between the pair of miniaturizable floating gate islands, and a planarization control gate conductive island is formed in the gate region. Within the pair of inter-gate dielectric layers and above the gate dielectric layer; a common source / drain diffusion region of a second conductivity type is formed in the common source by ion implantation in an automatically aligned manner Semiconductor-based A surface portion; a metal word line is formed on at least the conductive island of the planarization control gate and is perpendicular to the common source / drain region, wherein the metal word line, the conductive island of the planarization control gate, the The inter-gate dielectric layer and the miniaturizable floating gate island system are simultaneously formed by a second mask photoresist step; and two cell isolation regions are formed outside the metal word line and the common The surface portion of the semiconductor substrate between the source / drain regions. 2. The miniaturizable double-bit floating gate as described in item 1 of the scope of patent application Page 26 591763 VI. Patent application scope Flash memory cell structure, wherein the above-mentioned common source / drain region further includes at least a pair of second side wall dielectric pads formed on the side wall adjacent to the gate region and disposed. Over a portion of the surface of the penetrating dielectric layer, a highly conductive common source / drain layer is formed within a portion of a highly doped diffusion region of the second conductivity type within the common source / drain diffusion region. A portion of the surface and a planarized oxide layer are formed between the pair of second sidewall spacers and placed on a portion of the surface of the highly conductive common source / drain layer. 3. The miniaturizable double-bit floating gate flash memory cell structure described in item 1 of the scope of the patent application, wherein the co-source / drain region further includes at least a pair of second side wall dielectric cushion layers. A shallow groove is formed between the side wall adjacent to the gate region and a part of the surface of the penetrating dielectric layer, and a shallow groove is formed between the pair of second side wall dielectric pads to separate the common layer. The source / drain diffusion region is formed as a pair of buried source / drain diffusion regions and a planarized field oxide layer formed between the pair of second side wall dielectric pads and formed on the shallow groove. 4. The miniaturizable two-bit floating gate flash memory cell structure described in item 1 of the scope of the patent application, wherein the conductive island of the planarization control gate includes at least one planarized doped polycrystalline silicon island and the The micronized floating gate island contains at least one doped polycrystalline silicon or doped amorphous silicon island. 5. The miniaturizable double-bit floating gate flash memory cell structure described in item 1 of the scope of the patent application, wherein the metal word line includes at least one copper Page 27 591763 VI. Patent application scope (Cu), aluminum (A1) or tungsten (W) layer is placed on a barrier metal layer and the highly conductive common source / drain layer contains at least one tungsten silicide (WS i 2) Or a tungsten (W) layer is formed on a highly doped polycrystalline silicon or amorphous silicon layer as a source of the highly doped source / drain diffusion region forming the second conductivity type within the common source / drain diffusion region. A dopant diffusion source. 6. The miniaturizable double-bit floating gate flash memory cell structure described in item 1 of the scope of the patent application, wherein the co-source / drain-diffusion region includes at least one highly doped co-source / drain-diffusion region or one The highly doped common source / drain diffusion region is formed within a lightly doped common source / drain diffusion region. 7. The miniaturizable double-bit floating gate flash memory cell structure described in item 1 of the scope of the patent application, wherein the cell isolation region includes at least one isolation ion implantation region or one of the first conductivity type. Shallow trench isolation (STI) region. 8. The miniaturizable two-bit floating gate flash memory cell structure as described in item 1 of the scope of patent application, wherein an ion implantation region of the first conductivity type described above includes at least one shallow ion implantation region as The threshold voltage is adjusted and a deep ion implantation region is formed to form a surface portion of the semiconductor substrate which is formed under the gate dielectric layer and penetrates the forbidden region. 9. A contactless flash memory array, comprising at least: a semiconductor substrate of a first conductivity type; Page 591 763 6. The plurality of gates described in the patent application scope of resistance steps include at least a complex dielectric pad layer formed in a dielectric layer shape and a layer of the alternating ground formed between a pair of complex crystal side walls. Each of the drain regions of the drain diffusion region, wherein the above-mentioned dielectric pad-shaped conductive common source / is placed on the pair of second side lines of the common source diffusion region; The gate is formed by a plurality of gates on the half of a side layer located in a co-condensing floating gate / zone. The gate can be micro-scaled and drifted over the pair of electrical layers and the dielectric layer between the gates. A first alignment method. The semiconductor substrate region is further to the first and one flat layers of the dielectric layer, and a plurality of gold junctions are placed between the first and second flat layers and the common, the flat, and the even regions. The source area of a conductive substrate and an island can be miniaturized by floating atop the gate island by a pair of side walls and floating on the surface of the gate island and the gate dielectric two-conductivity type One surface of the implanted dopant A pair of partial surface dielectric two-conductivity facet fields of a pair of surfaces are oxidized on the highly conductive word line and the source / inverted area. The control gate pair can be miniaturized on the first mask light. The first side wall between the common drain areas is defined and the portion of the inner side wall dielectric pad gate conductive island layer with a pair of floating gate islands above the surface of the gate section alternately represents a common source / at the common source / section To form a second side wall, between a high cushion layer and a high dopant layer formed on a common source / drain tube. The planarization is vertical, and its conductive island and the floating gate island are defined and alternating. The mother of a pair of pairs can be formed in the common source through the dielectric, formed in the silicon oxide layer of the pair, and a gated semiconductor substrate in the complex pair. The tears are formed on the surface, and the dielectric layer is formed on the surface. The island dielectric is an island, the number is a metal word, and the dielectric layer is a second cover. Page 29 591763 VI. Patent application scope Photoresist step to form; and a plurality of cell isolation regions are formed on the surface portion of the semiconductor substrate outside the plurality of metal word lines and the common source / drain region. 10. The non-contact flash memory array according to item 9 of the scope of the patent application, wherein the common source / drain diffusion region includes at least one highly doped common source / drain diffusion region or one highly doped common source / drain diffusion region. The drain diffusion region is formed in a lightly doped common source / non-diffusion region. 1 1. The non-contact flash memory array as described in item 9 of the scope of the patent application, wherein each of the above-mentioned plurality of planarization control gate conductive islands includes at least one doped polycrystalline silicon island and the complex even pair can be scaled down Each of the floating gate islands includes at least an even-pair doped complex silicon island or an even-pair doped amorphous silicon island. 1 2. The contactless flash memory array as described in item 9 of the scope of patent application, wherein each of the plurality of metal word lines described above comprises at least one copper (Cu), aluminum (A1), or tungsten (W) layer It is over a barrier metal layer and the high-conductivity common source / sub-pipeline contains at least one fragmented crane (WS i 2) or crane (W) layer formed on a doped polycrystalline silicon or doped amorphous silicon. 1 3. The contactless flash memory array as described in item 9 of the scope of the patent application, wherein each of the plurality of inter-gate dielectric layers includes at least one silicon dioxide-silicon nitride-silicon dioxide (ΟΝΟ) Layer, a thermal polycrystalline silicon oxide layer, or a nitrided thermal polycrystalline silicon oxide layer. Page 30 591763 VI. Application for patent scope 1 4. The contactless flash memory array as described in item 9 of the patent application scope, wherein each of the plurality of cell isolation regions described above includes at least one of the first conductivity type Isolate the ion implantation area or a shallow groove isolation (STI) area. 1 5. The non-contact flash memory array according to item 9 of the scope of the patent application, wherein an ion implantation region of the first conductivity type described above includes at least one shallow ion implantation region as a threshold voltage adjustment and a A deep ion implantation region is formed to form a surface portion of the semiconductor substrate that penetrates the forbidden region under the gate dielectric layer. 1 6. A contactless flash memory array including at least: a semiconductor substrate of a first conductivity type; a plurality of gate regions are formed and alternately formed on the semiconductor substrate by a first mask photoresist step. Above, each of the plurality of gates described above is located between a common source region and a common drain region and includes at least a plurality of even pairs of scaleable floating gate islands formed by side walls of the common source / drain region. A pair of first side wall dielectric chirp layers are defined and alternately placed on a portion of the surface of a penetrating dielectric layer and have a pair of inter-gate dielectric layers formed on the pair of scaleable The top surface of the floating floating islands and a pair of polycrystalline silicon oxide layers are formed on the inner side walls of the pair of miniaturizable floating floating islands, and a gate dielectric layer is formed on the pair of first sides The semiconductor substrate between the wall dielectric pads and the plurality of planarization control gate conductive islands are alternately formed on the plurality of pairs of gate dielectric layers and a portion of the surface of the gate dielectric layer; P.31 591763 VI. A dielectric pad 4 on the semiconductor layer aligned with the scope of the patent application is placed on the shallow complex junction and the complex resistive step complex > and the second conductive type of the zone A common source / diffusion region of the substrate is arranged in a manner that each of the regions is inside. The steps include the number of oxide grooves between the surface layers of the metal. The common source plane pair pairs can be used to form extracellular cells. The implanted dopant is formed on the half layer formed on a surface portion of the common source to form a pair of second side stepping interfaces; word line and / or drain region control micronization; and element isolation semiconductor formation, wherein The above-mentioned common source electric pad layer is formed on the penetrating shallow grooves formed on a surface portion of the pair of second side conductor substrates and the plurality of planes between the pair of second side wall dielectric pad layers. For the vertical, the gate conductive island and floating gate island series are formed on the surface of the substrate to control the gate conductive island complex, wherein the above-mentioned plurality of metals, the plurality of even pairs of inter-gate dielectrics are simultaneously passed through a second cover, the plurality of metal word lines and the There are parts. Automatic, flat / composite ligature layer and curtain light source for the dielectric side wall / 1 7. The contactless flash memory array as described in item 16 of the patent application scope, where the above-mentioned common source / The drain diffusion region includes at least one highly doped common source / drain diffusion region or a highly doped common source / drain diffusion region formed in a lightly doped common source / drain diffusion region. Page 32 591763 VI. Application scope 1 9. The contactless flash memory array as described in item 16 of the scope of patent application, wherein an ion implantation area includes at least one shallow ion implantation of the first conductivity type. The region serves as an adjustment of the threshold voltage and a deep ion implantation region of the first conductivity type to form a surface portion of the semiconductor substrate that penetrates the forbidden region and is formed under the gate dielectric layer. 20. The contactless flash memory array as described in item 16 of the scope of patent application, wherein each of the plurality of metal word lines includes at least one copper (Cu), aluminum (A 1), or tungsten (W) The layer is formed on a barrier metal layer and the planarized control gate conductive island includes at least one doped polycrystalline silicon island. Page 33