TW526593B - A self-aligned multi-bit flash memory cell and its contactless flash memory array - Google Patents

Abstract

A self-aligned multi-bit flash memory cell of the present invention comprises two floating-gate structures with a spacing dielectric layer being formed therebetween; a planarized control-gate layer over an integrate-dielectric layer being formed over the two floating-gate structures and the spacing dielectric layer; and a common-source/drain bit line together with a first sidewall dielectric spacer being formed over a flat bed formed by a common-source/drain diffusion region and nearby etched raised field-oxide layers. A contactless multi-bit flash memory array of the present invention comprises a plurality of common-source/drain bit lines being formed transversely to a plurality of parallel STI regions and a plurality of word lines integrated with a plurality of planarized control-gate layers of the described cells being patterned and formed transversely to the plurality of common-source/drain bit lines.

Description

526593 V. Description of the invention (1) Background of the invention: (1) Scope of the invention The present invention relates to general flash memory cells and their memory arrays, especially to an automatically aligned multi-bit (mu 1 ti-bit) memory Cells and their non-contact flash memory arrays. (2) Description of the know-how. The structure of a flash memory cell can be basically divided into two categories: a stack-gate structure and a split-gate structure. The stack gate structure has a cell cell gate length that is defined using a minimum line width of the technology used and is therefore often used in today's high-density flash memory systems. Stacked gate-type flash memory cells can be connected to a variety of different circuit structures, such as NOR-type, NAND-type, and ANN- t y p e, in accordance with basic logic functions. A stacked gate flash memory cell can be written using the channel hot electron injection method to form different threshold voltage levels as a multi-bit storage. However, the durability of the cell and the sensing of the threshold voltage level have become a difficult task, especially the stack gate flash memory cell gate length has been further reduced. Therefore, a two-bit flash memory cell with two floating gate structures has become a major trend in technological development. Figure 1A shows a cross-sectional view of a two-bit flash memory cell, two of which are stacked gate-type Crystal 2 2 G, 2 0 G with a selection gate transistor

526593 V. Description of the invention (2) 2 4 G is formed on a semiconductor substrate 26; two total N + / N- diffusion regions 22A and 20A are formed on each side of the gate region; a selective gate line (SG) system Formed on two N + / N-diffusion regions, two stacked gate transistors, and one gate dielectric layer 2 4 A formed on a semiconductor substrate 2 6 A due to stacked gate transistors The selection of the gate transistor and the common N + / N-diffusion region can be defined by a mask photoresistance step with a minimum line width F. Therefore, the cell size of each bit of a two-bit flash memory cell It can be designed to be equal to 4 F 2. If a selection gate line and its distance can be defined by a minimum line width F. Figure 1B shows a top view of a two-bit flash memory cell shown in Figure 1A. Obviously, the cell size of each bit shown in Figures A and B can be made comparable to the cell size of a non-harmonic flash memory array due to the contactless structure. However, some shortcomings can be seen from Figure 1A and Figure 1B: The stray capacitance between the selective gate line (SG) and the total N + / N —diffusion regions 2 0 A, 2 2 A is large; The stray capacitance between the selective gate line (SG) and the control gate line 2 2 C, 20 C is large; the area outside the selective gate area between the common N + / N diffusion areas has poor isolation; and Adjacent selection gates have poor isolation below the control gates. It is worth emphasizing here that the poor isolation between adjacent selection gate lines will cause erroneous data reading of adjacent cell elements under the same control line. Therefore, a main object of the present invention is to provide an automatic alignment multi-bit flash memory cell having a cell size of less than 2F2 per cell. Another object of the present invention is to provide an intermediate channel for automatically aligning multi-bit flash memory cells with better writing efficiency and lower writing power.

526593 5. Description of the invention (3) Mid-channel hot electron injection method for writing. A still further object of the present invention is to provide a high-conductivity common source / drain line of a contactless flash memory array as each bit line and has a smaller bit line resistance and is relatively smaller than a semiconductor substrate and a word line. The smaller bit line stray capacitance. Another special object of the present invention is to provide a highly conductive metal line of a contactless multi-bit flash memory array as each word line and has a smaller word line resistance and a smaller relative to the bit line. Word line stray capacitance. Other objects and features of the present invention will be more prominent in the subsequent description. SUMMARY OF THE INVENTION The present invention discloses an automatic alignment multi-bit flash memory cell and a contactless flash memory array. An auto-aligned multi-bit flash memory cell unit is formed on a semiconductor substrate of a first conductivity type having an active region and two parallel shallow groove isolation (ST I) regions and can be divided into three regions: one A common source area, a gate area, and a common leakage area, wherein the gate area is located between the common source area and the common leakage area. The common source / drain area includes at least one first / second side wall dielectric cushion layer formed on each side wall of the gate area, and is disposed between a common source / drain area and two adjacent etched levels. A part of the surface of a first / second flat bed composed of a first / second protruding field oxide layer; a common source / drain conductive line is formed on the first / second side wall dielectric cushion layer Outside the first / second flat bed; and a first /

Page 7 526593 5. Description of the invention (4) A second planarized thick silicon dioxide layer is formed on the common source / drain conductive pipeline and the first / second side wall dielectric pad layer. The gate region includes at least a first floating gate structure having a first floating gate layer (FG 1) disposed on the first gate dielectric layer and a second floating gate layer (FG2) disposed in the active region. Dipping a second floating gate structure on the second gate dielectric layer with a sandwich dielectric layer interposed therebetween; and a planarization control gate layer (CG) placed on top of the inter-gate dielectric layer and at least Formed on the first / second floating gate structure, the interlayer dielectric layer, the first / second side wall dielectric cushion layer and its side wall, and the protruding field oxide layer to form the first A connotation. A first connection metal layer is formed on the inter-gate dielectric layer on the common source / drain region and the planarization control gate layer (CG) as a word line, wherein the first connection metal layer is a A mask dielectric layer and two side wall dielectric cushion layers are used to form the planarization control gate layer at the same time. A first conductivity type ion implantation region is formed in a semiconductor substrate under the second floating gate structure, wherein the ion implantation region includes at least a shallow ion implantation region as a threshold voltage adjustment and a deep The ion implants the area to form a forbidden area. Similarly, if the inter-gate dielectric layer of the first meaning of the present invention is formed only on the first / second floating gate layer and the interlayer dielectric layer of the active area, the automatic alignment of multiple bits Flash memory cells become the second connotation of the present invention. A contactless multi-bit flash memory array of the present invention is formed on a semiconductor substrate of a first conductivity type having a plurality of parallel shallow groove isolation regions and a plurality of active regions alternately formed. The complex common source pipeline area and the complex virtual gate area are alternately formed and parallel to the complex parallel shallow groove isolation area.

526593 V. Description of the invention (5) The number of the common sides of the gate line to the tube and the source side are duplicated. In the location line, there is a small number of complex gates in the quasi-interval area of the gate, including a gate and a gate, and a gate in the quasi-intermediate area of the gate, and the shape-shaped electric current shared by the adjacent sources in the gate area of the straight area. The layer guide pad is electrically connected to the first layer, and the first layer is from the side to the side area to the side area. Every time the area area is flat, the first side is the first one. The electrical conductivity source oxygen field has a sudden burst; the upper surface of the surface is equal to the remaining one by one and the bed = the mouth and the wire tube conductivity source should be the layered layered pads The two sides of the wall are flattened on the side of the bed and flat on the side of the wall. The first one is two on the side from the opposite one and the side with the wall. The area gate is one by one. Lines adjacent to the tube are leaked together to form the layer of the upper layer of the dielectric layer pad on the electric side and the dielectric layer of the tube bed. The transformer bed is the second layer of the leaked oxygen.上 的 面面 突 表 垫 二份 电 部 部 平平 一 墙 # The side of the bed One, two, peace, two, two, two, three, one, two, one, two, one, two, one, two, one thick, thick, and two, one side, one side, one, two, one, one, and two, one, one, and two. And on-line layered silicon oxide gates = mouth tube with low electricity to the conduction area leakage, the total number of active areas in the area, one in the other area, and the other in the area. It is located in the districts that contain packages and gates. The gates are floating, floating, floating, floating, floating, floating, floating, floating, floating, floating, floating, floating, floating. The layer is directly above the vertical layer of gold. The wire is an interconnecting wire. The second pipe is the first one. The compound is leaked to the floating gate and the second layer is flat. Counting and engraving layers; # 电 间 和 介 之 形 The first field should be out, the protruding layer should be the second fragmented area \ Oxygen 112 The thickened area should be flattened at the surface gate, and the shape should be flat and small. To the layer, a layer of the first dielectric layer, the dielectric layer, the electrical side of the wall gate layer, a dielectric layer. The first line of the Yanzi line, the floating gate

I

Page 9 526593 V. Description of the invention (6) The source of Qiu <The copy of the Mingshu is in the complex gate between the line and the word of each oxygen in the form of the upper layer of the system. In other words, the internal shape of the tube inside the culvert line is divided into two parts: the main layer, the ground layer, the dielectric layer, and the layer layer gate. The first han, \ 内 and a kind of second. The first layer of the first bright layer of the invention is based on the checkmark diagram 300 semiconductor substrate 301c first gate dielectric layer 302 first conductive layer 3 0 2 c first floating gate layer 303 first mask dielectric layer 3 0 4b First protruding field oxide layer 3 0 4 c First etched flat field oxide layer 3 0 4d Second etched field oxide layer 3 0 4 e Second etched flat field oxide layer 3 0 5 Second mask Screen dielectric layer 3 0 6 a Common source diffusion region 3 0 6b Shallowly doped source diffusion region 3 0 7a First side wall dielectric pad 3 0 7b Etching the first side wall dielectric pad 30 8b common source conductive pipeline 309a first planarized thick silicon dioxide layer 309b etched flat first planarized thick silicon dioxide layer 310a third side wall dielectric cushion layer 3 1 1 a ion implanted area 312a sandwiched dielectric Layer 313b second gate dielectric layer 3 1 4 c second floating gate layer 3 1 5 a fourth side wall dielectric cushion layer

Page 10

526593 V. Description of the invention (7) 3 1 6a co-drained diffusion region 3 1 6b shallow highly doped leakage diffusion region 317a second side wall dielectric pad 3 1 7b etched flat second side wall dielectric pad 3 18b Common leakage conductive pipeline 319a Second planarized thick silicon dioxide layer 3 1 9 b Etched second planarized thick silicon dioxide layer 3 2 0 Intergate dielectric layer 3 2 0 a Intergate dielectric layer 3 2 1 b Planarization control gate layer 3 2 2 a First connection metal layer 323a Third mask dielectric layer 324a Side wall dielectric cushion layer invention detailed description: Now refer to FIG. 2A (a) and FIG. 2B ( b), which discloses cross-sectional views of two types of self-aligned multi-bit flash memory cells of the present invention. Fig. 2A (a) A cross-sectional view of an automatic alignment of multi-bit flash memory cells that reveals the first connotation of the present invention and Fig. 2 A (b) An automatic alignment of the second connotation of the present invention Sectional view of multi-bit flash memory cells. According to Figure A (a), an auto-aligned multi-bit flash memory cell marked by a dashed line can be divided into three regions: a common source region, a gate region, and a co-leak region, where the gate region It is between the common source area and the common leak area. The common source / drain region includes at least one first / second side wall dielectric cushion layer 3 7b / 317b formed on each side wall of the gate region and placed on a common source / Leakage diffusion region 3 0 6 a / 3 1 6 a and part of a first / second flat bed formed by two adjacent etched flat first / second protruding field oxide layers

526593 V. Description of Invention (8)

On the surface, a common / bleeding conductive line 308b / 318b (CSBL / CDBL) is formed on the first / first side wall dielectric cushion layer 〇7b / 3 丨 7b. On a flat bed, and a first / second planarized thick silicon dioxide layer 3 9b / 319b = produced, common source / drain conductive pipeline 308b / 丨 8b (cSBL / CDBL) and the first / second Side wall dielectric pads over 307b / 317b. The gate region includes at least a first floating gate structure having a first floating gate layer 302c (FG1) formed on a first gate dielectric cushion layer 30lc, and a second floating gate in the active region. Layer 3 丨 4c (FG2) is a second floating gate structure formed on a second gate dielectric pad layer 3 1 3b and a central dielectric layer 3 1 2 a interposed therebetween, and filled with Two shallow groove isolation regions protruding from the field oxide layer 3 0 4 b; and a planarization control gate layer 3 2 1 b (CG) is placed on top of an inter-gate dielectric layer 3 2 0 and formed at least on Of the first / second floating gate structure, the inter-gate dielectric layer 3 丨 2a, the first / second side wall dielectric pad layer 307b / 317b, and the protruding field oxide layer 304b To form the first connotation of the present invention. A first connection metal layer 3 2 2a is formed on the inter-gate dielectric layer 3 2 0 of the common source / area and the planarization control gate layer 321 b (CG) as a word line (milk), Wherein, the first connection metal layer 3 2 2 a-and the planarization control gate layer 3 2 丨 b (CG) simultaneously use a mask dielectric layer 323 a and its two side wall dielectric cushion layers 3 2 4 a to form. An ion implantation region 3 1 1 b of the first conductivity type includes at least one shallow ion implantation region as a threshold voltage adjustment and a deep ion implantation region to form a resistance-prohibited region. FIG. 2A (b) reveals a cell structure similar to FIG. 2a (a), in which an inter-gate dielectric layer 3 2 0 a replaces the inter-gate dielectric layer 3 2 0 only in the first / second Two floating gate layers and the interlayer dielectric layer 3 1 2 a.

Page 12 526593 V. Description of the invention (9) Figure 2B discloses a top view construction diagram of a contactless multi-bit flash memory array of the present invention, wherein a plurality of parallel shallow groove isolation regions are marked as STI 1 ines and The plurality of active regions are alternately formed on a semiconductor substrate 300 of a first conductivity type as indicated by AA's. The plurality of common source pipeline regions and the plurality of virtual gate regions are alternately formed and perpendicular to the plurality of parallel shallow groove isolation regions, wherein the plurality of virtual gate regions include at least one pair of gate regions on each side and a common vent. The pipeline area is located between the gate areas. Each of the plurality of common source pipeline areas includes at least-a first side wall dielectric pad 3 0 7 b formed on each side wall of an adjacent virtual gate area and placed by a second conductive A common source diffusion region of type 3 0 6 a, 3 0 6 b and an etched flat first protruding field oxide layer 3 0 4 c alternately on a part of a surface of a first flat bed; A source conductive pipeline 3 0 8b is formed on the first flat bed between the pair of first side wall dielectric pads 3 7 7b; and a first planarized thick silicon dioxide layer 3 9 b is formed on the common layer. The source conductive pipeline 3 0 8 b and the pair of first side wall dielectric pads 3 7 b. Each zone of the common leakage pipeline area includes at least a pair of second side wall dielectric pads 3 1 7b formed on each side wall of the adjacent gate area and placed on a common; poor diffusion area. 316a, 31 6b, and a portion of the surface of a second flat bed composed alternately of the second protruding field oxide layer 3 0 4 d; a common leakage conductive line 3 1 8 b is formed on the surface The second flat bed between the second side wall dielectric pads 3 1 7b; and a second planarized thick silicon dioxide layer 3 1 9b is formed on the common leakage conductive line 3 1 8b and the pair of first Two side wall dielectric pads 3 1 7b. Each region of the pair of gate regions includes at least a plurality of first floating gate layers 3 0 2 c (FG 1) located on a side portion of the plurality of active regions. On and above the plural master

526593 V. Description of the invention (10) The second floating gate layer 314c on the other side of the moving area is formed on the second gate dielectric layer 3 1 3 b; the planar gate control layer 32 lb (CG) —formed simultaneously with the plurality of first connecting metal layers 3 2 2a and formed to form the common source / drain conductive lines 3 0 8b, 31 6b with each other _ ^ complex bit line (WL). An inter-gate dielectric layer 3 2 0 is formed at least in the first and second floating layers. The layer 3 2 2c / 314c, the interlayer dielectric layer 312a, and the second planarized thick silicon dioxide layer 309 b / 319b. , The first / first side wall dielectric pad 3 0 7b / 3 1 7b, and the projected field oxide layer 3 0 4 b of each of the gate regions to form the first type of the present invention Connotation, wherein the complex digital line is formed on the inter-gate dielectric layer 3 2 0 above the complex common source / drain pipeline area. However, the inter-gate dielectric layer 3 02 is formed only on the first and second floating gate layers 3 0 2 c / 3 丨 4 c and the interlayer dielectric layer 3 1 2 a located above the active region. To form the second connotation of the present invention. ^ ^ Ξ: ^ A kind of non-contact multi-bit flash memory array not shown in Figure 2 is a number of moments common source conductive pipeline (BL0, BL2, BL4) is an electrical pipeline (BU, = adjacent common source Between the conductive pipelines and the common bubble conductors BL0, BL2, and BUb are connected to the adjacent common source conductive pipeline (source / drain conductive pipeline f% 'and the complex digital line (WL0 ~ WL3)). The complex number s in a column is perpendicular to each other and each of the complex number lines is connected to the control gate of the flash / memory flash memory cell according to Figure 2. The contact flash memory array θ a = no, can be clear It can be seen that a non-cell cell can be aligned with each bit of a multi-bit flash memory cell to easily hunt a semiconductor etch under the dielectric layer 3i2a.

526593 V. Description of the invention (11) The middle channel hot electron injection generated by a south horizontal electric field on the surface of the substrate to store the multi-valued critical voltage must be located in each floating gate of the double floating gates (F G and F G 2). According to the above description, an automatic alignment multi-bit flash memory cell of the present invention and its contactless flash memory array exhibit the following advantages and features: (a) An automatic alignment multi-bit flash of the present invention The flash memory cell line can be miniaturized and its cell size can be made less than 4 F 2. (b) An auto-aligned multi-bit flash memory cell of the present invention has two independent floating gates to store multiple quasi-bit data in each of the floating gates. The flash rate of the recording rate is faster than the multiple write-in and write-in bit rate &amp; T xlL. The pairing method and the dynamic rate are self-injected and the hot Ming Dao Gao Tong is more efficient. There is CC usage in CC. The advantage is that the source is more in line with the content, and the power level is raised. The hash is scattered. The memory layer is expanded. The flash memory is more flashy. The fast-passing inter-cell has more specific points than the board. Phase-to-phase work and open wire resistance tube, electric wire, 3 conduit C, leaks and notes, flash memory, multi-point connection, no seed 1

Page 15 526593 V. Description of the invention (12) Highly conductive metal lines are used as word lines and have a smaller word line resistance and a smaller word line stray capacitance relative to the bit lines. Now, see FIG. 2A to FIG. 3F ′, which discloses a shallow groove isolation (ST I) structure for manufacturing an auto-aligned multi-bit το flash memory cell and a contactless flash memory array of the present invention. Process steps and sectional views. As shown in FIG. 3A, a first gate dielectric layer 301 is formed on a first conductivity type = semiconductor substrate 300; a first conductive layer 301 is formed on a first gate electrical layer. Over 3 0 1; a first mask dielectric layer 3 03 is formed on the first conductive layer 3 02; and a plurality of mask photoresist PR1 is placed on the first mask dielectric layer 3 0 3 The complex active area (AA, S) (below PR1) and the complex parallel = f slot ^ separation area (STI 1 ines) (between PR1) are defined above. The first gate dielectric layer 301 敎 5…, thermal-oxide or nitrided layer is used as a thin penetrating dielectric layer and its thickness is between 805 : Between 120 Angstroms. The first gate dielectric layer 301 may be a silicon dioxide-silicon (0N0) structure or a silicon nitride-silicon dioxide structure (100 angstroms). Unit and its equivalent silicon dioxide thickness is between 50 angstroms and heterocrystalline stone. The f conductive layer 302 is made of doped polycrystalline silicon or doped, with a thickness of 2.8 and a low voltage. The chemical vapor deposition (LPCVD) method is used to make 3〇3 ^ * aVy '/, 5! ° ^ ^ 2 5 0 0 ^ ^ ^ t ^ and LPCVD is used to sacrifice, Figure 3-ΒΛ Shown ΛίΛ curtain light, the "first-mask dielectric layer of PR1, the missing semiconductor, and the first gate dielectric layer 3 0 1 are sequentially removed + V-body substrate 3 0 0 is anisotropically etched to form Shallow groove

Page 16 526593 V. Description of the invention (13) Remove the multiple mask PR1. The depth of the shallow grooves in the semiconductor substrate 300 is between 300 angstroms and 800 angstroms. Figure 3C shows that a planarized field oxide layer 3 0 4 a is formed in each shallow groove, and a thick silicon dioxide layer 3 0 4 is first deposited on the entire structure, and then a chemical-mechanical smoothing method is used. (CMP) to planarize and use the first mask dielectric layer 3 0 3 a as a flattening stop layer. A thick silicon dioxide layer 304 is manufactured using high-density plasma (HDP) CVD or CVD and is composed of silicon dioxide or glass-filled (PSG). FIG. 3D shows that the planarized field oxide layer 3 0 4 a is anisotropically etched back to a thickness approximately equal to that of the first mask dielectric layer 3 0 3 a to form a protruding field oxide layer 3 0 4 b. Figure 3E shows that the first mask dielectric layer 3 03a is removed using hot-phosphoric acid or anisotropic dry-type I engraving method. It can be clearly seen from FIG. 3E that a flat surface is alternately composed of the first conductive layer 3 2 a and the protruding field oxide layer 3 0 4 b. FIG. 3F shows that a second mask dielectric layer 3 0 5 is formed on the flat surface shown in FIG. 3 E and is composed of silicon nitride and manufactured by the LPCVD method. The thickness is 3 0 0 0 Angstroms and 15 0 0 0 Angstroms. The cross-sectional view of one active area in Fig. 3F is indicated in Fig. 4A as indicated by F-F '. Referring now to FIGS. 4A to 4N, the manufacturing steps and cross-sectional views of an automatic alignment multi-bit flash memory cell and a contactless flash memory array of the present invention are manufactured. Figure 4A shows only a small part of an array. A mask photoresist PR2 is used to define a virtual gate area (below PR2). A virtual gate zone contains a pair of gate zones and a common drain line

Page 17 526593 V. Description of the invention (14) Area, as indicated by xF; Areas other than PR2 are common source pipeline areas, as indicated by F. In fact, the multiple mask photoresist PR2 is perpendicular to the parallel parallel shallow groove isolation area and its spacing is defined by the common source official line area. FIG. 4B shows that the second mask dielectric layer 3 0 5 located outside the multiple mask photoresist PR2 is removed anisotropically, and then the protruding field oxide layer 3 0 4b is etched back to be equal to the first conductive layer 302. a depth of a, then remove the first conductive layer 302a, and then remove the mask photoresist PR2. Dopants are implanted across the first gate dielectric layer 3 0 1 a in a self-aligned manner within a semiconductor substrate 3 0 of a plurality of active regions along a common source pipeline region to form a plurality of second conductive types. The source diffusion region 3 0 6 a; then the first gate dielectric layer 3 0 1 a of the plurality of common source pipeline regions and the etched flat field oxide layer are etched to form a common source diffusion region 3 6 a and an etch A first flat bed alternately formed by planarizing the first protruding field oxide layer 3 0 4 c. A common source diffusion region 3 0 6 a is lightly doped, moderately-doped, or highly doped. Figure 4C shows a pair of first side wall dielectric pads 3 0 7 a formed on the outer side wall of the adjacent virtual gate area and placed on a portion of the surface of the first flat bed; a planarized second The conductive layer 3 0 8 a is formed on each first flat bed between a pair of first side wall dielectric pads 3 7 a. A planarized second conductive layer 3 0a is composed of doped polycrystalline silicon and is manufactured by LPCVD method. A thick second conductive layer 3 0 8 is first deposited to fill a pair of first side walls. The gap between the electrical pads 3 0 7a is planarized by the CMP method, and the second mask dielectric layer 305a is used as a smoothing stop layer. Figure 4D shows that the planarized second conductive layer 3 0 8 a is approximately equal to

526593 V. Description of the invention (15) ~-a curtain '丨 a depth of the thickness of the cladding layer 305 a, and then the etched back planar conductive layer 3 0 8b is implanted with a high-dose doped f as a A dopant diffusion source 3 0 6b of the second conductivity type is formed in each common source diffusion region. Ershi ~ &amp; β. ^. The second non-conducting soil μ repairs the heterodiffusion region 306b in each common source diffusion region Λ to form a planarized second conductive layer = ΐΐί = the conductivity of the conductive pipeline and can use Xi The aim is to aim at the silicidation technology or the stacking technology used in the electrified layer 3 08b to form a planarized second surface of the surname. The thickened second dioxide layer 3 0 9a is formed at 1; A first flat source conductive pipeline 3 0c and a pair of sides = two: a coplanar thick silicon dioxide layer 3 0 9a of a common source pipeline area is over 3 ° 7a. The first-Heisei, using HDPCVD or CVD to make and report 1 / silicon or phosphorous glass (PSG) film 3 0 9, and then the stacked system is first deposited a thick silicon dioxide second mask dielectric layer 305 A + mill ^ 309 plus planarization and the second layer of the second mask dielectric layer J is shown in Figure 4E. The dry etching method is used to selectively remove ", / a is using thermal phosphoric acid or non-isoelectric, layer 3 1 〇a is formed in the common source pipeline area, j, a pair of third side wall mother Above the side wall and placed on one side of the side wall dielectric cushion layer 3 007a 3 0 2 b and the tuxedo $ ^ virtual space of the flute -if two: large emulsion% emulsion layer 304b [Interchange] The younger brother—the conductive layer t ^ Next, each virtual gate area is a flat surface between a and two ... the first conductive layer 3a between the two three side wall dielectric pads 2 The sequence closing layer 302c, and a pair of the first-:::, the impurities in the-pair of the first and the second layer of the first dielectric layer: U: to form an ion implantation region 3 1 1 a, As shown in Figure 4E of the semiconductor substrate between Η and 。. An ion cloth 5265953 V. Description of the invention (16) (indicated by the dotted line) q Planting area 3 1 1 a may include a shallow ion implanting area (female is the critical voltage) Adjustment and a deep ion implantation area ^ xUS to form a punch-through forbidden area. (No) to show each virtual with a pair of third sides and then using the back worm method Figure 4F The first free dielectric layer 30 lb between a pair of third electrical layers 310a is added and removed by dilute = wall dielectric bubble dipping or non-isotropic dry type engraving; made by oxidation; acid A second dielectric layer 313a is formed on a pair of third dielectric pad layers 31〇a to form a conductor surface and a spacing dielectric layer 3i2a is formed on each of the two and a half drift gates 3 0 2c. An outer side wall; and then a # pair of first electrical layer 31 4b is formed between each of the second gate dielectric layers f of each virtual gate region between the sandwich dielectric layers 312a. The third conductive layer 31 : Doped: composed of two doped amorphous stones and using LPCVD to form first = two-crystal hetero ... amorphous stone film 314 to fill the gap between a pair of second two-two electric pad layers 301a and then Then use the CMP method to add the stacked thickness of 24 heteropoly / amorphous silicon film 3 丨 4 to planarization, =: electric cushion layer 3 丨 〇a as a flattening stop area; The next one: the surface of the I complex / amorphous layer 3 1 4 al is etched to a level close to the top surface of the pair of floating gate layers 3 0 2 c. Figure 4G shows a pair of fourth sides The wall dielectric layer 315a is formed on Yiningdi's three side wall dielectric pads 31 0a and each side wall and the third conductive layer 3 丨 4b and the protruding field oxide layer 304 d in the gate region are composed of a total of = On a flat surface; the non-rigid mask photoresist pR3 is formed on the common source second region and the third side wall dielectric pad 31 0a; and then the first and fourth side wall dielectric pads The protruding field oxide layer 3 between layers 3 and 5a looks like a mouth

Page 20 526593 V. Description of the invention (17) The pre-etchback is approximately equal to the thickness of a third conductive layer 3 1 4 b, and then between the pair of fourth side wall dielectric pad layers 3 1 5 a The three conductive layers are removed as shown in Figure 4 (a). FIG. 4A shows that the dopants are implanted across the second gate dielectric layer 3 1 3 a in an automatic alignment manner between each pair of fourth side wall dielectric pads 3 1 5 a in each virtual gate region. Between the active regions of the semiconductor substrate to form a second leakage type diffusion region 3 1 6 a. The co-drained diffusion region 3 1 6 a may be lightly doped, moderately doped, or highly doped. FIG. 4I shows that the second gate dielectric layer 3 1 3 a between a pair of fourth side wall dielectric plutonium layers 3 1 5 a is made by dilute hydrofluoric acid and immersed in immersion or by anisotropic dry type. I was removed by etching and the protruding field oxide layer 3 0 4 d was also etched to form a co-drained diffusion region 3 1 6 a and a second etched flat protruding field oxide layer 3 0 4 e. A second flat bed composed of alternating ground; and a pair of second side wall dielectric layers 3 1 7 a formed on a pair of fourth side wall dielectric cushion layers 3 1 5 a and a pair of first Two floating gates 3 1 4 c are placed on a part of the surface of the second flat bed of each virtual gate zone. The second side wall dielectric pad 3 1 7 a is composed of silicon dioxide and is manufactured by the LPCVD method. Figure 4J shows that a fourth conductive layer 3 1 8 b is formed on a second flat bed between one pair of second side wall dielectric pads 3 1 7 a in each virtual gate area and is automatically aligned. A high-dose dopant is implanted in the fourth conductive layer 3 1 8b to form a highly-doped drain diffusion region 3 1 6 b of a second conductivity type in a co-drain diffusion region 3 1 6 a. A dopant diffusion source inside. First, the conductive layer 318b is composed of doped polycrystalline silicon and is manufactured by LPCVD method, and is covered with a metal silicide layer to form a co-bleeding conductive pipeline.

526593 V. Description of the invention (18) 318b. Figure 4K shows a second planarized thick silicon dioxide layer 3 1 9 a is a common leakage conductive pipeline 3 1 8 b formed in each virtual gate area and a pair of second side wall dielectric pads 3 1 7 Above a, it is the same as the manufacturing method of the first planarized thick silicon dioxide layer 309 a. Figure L shows that the first / second planarized thick silicon dioxide layers 3 0 9 a, 3 1 9 a, and the first / second side wall dielectric pads 307 a, 317 a are removed by the first insect. Curved portions of the first / second side wall dielectric pads 307a, 317a; using thermal phosphoric acid or anisotropic dry etching to selectively remove the third / fourth side wall dielectric pads 310a , 315a. FIG. 4M (a) shows that an inter-gate dielectric layer 3 2 0 is formed on the structure shown in FIG. 4 L, and a planarization control gate layer 3 2 1 a is formed in the gap between the inter-gate dielectric layers. The gate dielectric layer 3 2 0 is a silicon dioxide-silicon nitride-silicon dioxide (ΟΝΟ) structure or a silicon nitride-silicon dioxide structure, and its equivalent silicon dioxide thickness is between 80 angstroms and 80 angstroms. Between 1 2 0 Angstroms. The inter-gate dielectric layer 3 2 0 can also be a silicon dioxide layer and is manufactured using a high-temperature silicon dioxide (HT0) stacking method, with a thickness between 100 angstroms and 500 angstroms. The planarization control gate 3 2 1 a is composed of doped polycrystalline silicon, or a planarized silicide layer formed in a planarized thin doped polycrystalline silicon layer. Fig. 4M (b) shows a thin layer of thermally complex polysilicon oxide (P 〇1 y-〇X ide) or a thin nitrided thermally complex silicon oxide layer 3 2 0 a is thermally grown. The method is formed on the first / second floating gate layer 3 0 2 c, 3 1 4 c, and its thickness is between 100 angstrom and 250 angstrom; and a planarization control gate 3 2 1 a formed on a thin thermal polycrystalline silicon oxide layer or a thin nitrided thermal polycrystalline silicon oxide layer and located on the first / second side

526593 V. Description of the invention (19) A protruding field oxide layer 3 04b and 3 0 4d between the wall dielectric pads 3 0 7b and 31 7b. It is worth noting here that the planarization control gate layer 3 2 1 a can be implanted with a high dose of dopants to increase the conductivity of the planarization control gate layer 3 2 1 a and can cover an automatic alignment metal stone A chemical compound layer, such as titanium sulfide (TiSi 2) or cobalt silicide (CoSi 2). Figure 4N (a) and Figure 4N (b) show a first connection metal layer 3 2 2 is placed on a metal barrier layer and then formed on the plane of Figure 4M (a) and Figure 4M (b) The structured structure and a set of hard cover curtain layers are formed on the first connection metal layer 3 2 2 to simultaneously shape and etch the first connection metal layer 3 2 2 and the planarization control gate layer 3 2 1 a to form The complex digital line 3 2 2 a integrated with the planarized control gate layer 3 2 1 b. Each hard cover curtain layer includes a third cover dielectric layer 3 2 3 a aligned on each of the plurality of active areas and two side wall dielectric pads 3 2 4 a formed on each cover Side wall of curtain dielectric layer 3 2 3 a. The first connection metal layer is composed of Sha or copper; the barrier metal (b a r r e r-m t a 1) layer is a titanium nitride (T i N) or nitride group (T a N) layer. A third mask dielectric layer 3 2 3 a and its two side wall dielectric pad layers 3 2 4 a are composed of silicon nitride or silicon dioxide and are manufactured by the LPCVD method. The cross-sections indicated in Figure 4N (a) are shown in Figures 5A to 5D and the cross-sections indicated in Figure 4N (b) are shown in Figures 6A to 6D, respectively. Please refer to FIG. 5A to FIG. 5D, which reveals the first connotation of the present invention shown in FIG. 4N (a). An automatic alignment multi-bit flash memory cell and its contactless flash Memory array. FIG. 5A shows a cross-sectional view along a common source conductive line 3 0 8 b, where a common source conductive line 3 0 8 b is formed on the first protruding field oxide layer 3 0 4 c and a Second conductive

526593 V. Description of the invention (20) A highly doped source diffusion region 3 0 6 b is formed on a first flat bed composed alternately within a common source diffusion region 3 6 a; a first planarization A thick silicon dioxide layer 309b is formed on the common source conductive pipeline 308b; an inter-gate dielectric layer 320 is formed on the first planarized thick silicon dioxide layer 309b; a plurality of first connection metals The layer 3 2 2 a is formed by a set of hard mask layers and is formed on the gate dielectric layer 320. Each hard mask layer includes a third mask dielectric layer 323 a aligned on the active area and two side wall dielectric pads 3 2 4 a formed on the sides of the mask dielectric layer 323 a On the wall. FIG. 5B shows a cross-sectional view along the first floating gate, in which the plurality of first connecting metal layers 3 2 2 a and the control gate are integrated and formed using a group of hard cover curtain layers to be simultaneously formed and etched and placed. The inter-gate dielectric layer 3 2 0; the inter-gate dielectric layer 3 2 0 is formed by an alternating ground consisting of a first protruding field oxide layer 3 0 4b and a first floating gate layer 3 0 2 c On a flat surface. Each hard mask layer includes a third mask dielectric layer 3 2 3a aligned with an active region having a first floating gate layer 3 2 c formed on a first gate dielectric layer 3 0 1 c. It can be clearly seen here that a third mask dielectric layer 3 2 3 a is aligned on the first floating gate layer of an active area and two side wall dielectric cushion layers 3 24 a are used to eliminate control Misalignment of the gate relative to the first floating gate layer 3 0 2 c. FIG. 5C shows a cross-sectional view along the second floating gate, in which an inter-gate dielectric layer 3 2 0 is formed by the second protruding field oxide layer 3 0 4d and the second floating gate layer 3 1 4 c. Alternately composed on a flat surface; the second floating gate layer 3 1 4c is formed on a second gate dielectric layer 3 1 3b; an ion implantation region 3 1 1 b includes a shallow ion implantation region to Adjustment as threshold voltage

Page 24 526593 V. Description of the invention (21) and a deep ion implantation area to form a penetration prohibited area, which is formed in the semiconductor substrate 3 0 0 of the active area; the plurality of first wiring metal layers 3 2 2 a It is integrated with the control gate layer 3 2 1 b and is formed and etched at the same time by using one of the aforementioned hard cover curtain layers. Similarly, the third mask dielectric layer 3 2 3 a and its two side wall dielectric cushion layers 3 2 4 a are used to eliminate the control gate layer 3 2 1 a relative to the second floating gate layer 31 4c. Misalignment. FIG. 5D shows a cross-sectional view along a co-bleeding conductive line 3 1 8b. A co-bleeding conductive line 3 1 8b is formed on the second protruding field oxide layer 3 0 4e and a second conductive layer. High-doped drain diffusion region 316b is formed on a second flat bed composed of a co-diffusion diffusion region 3 1 6 a; a second planarized thick silicon dioxide layer 3 1 9 b is formed on the common drain A conductive line 3 1 8 b; an inter-gate dielectric layer 3 2 0 is formed on the second planarized thick silicon dioxide layer 3 1 9 b; and a plurality of first connecting metal layers 3 2 2 a Use one of the above-mentioned hard cover curtain layers to shape and engraving. Referring now to FIGS. 6A to 6D, various cross-sectional views of the second connotation of the present invention shown in FIG. 4N (b) are disclosed. Comparing Fig. 6A and Fig. 5A and Fig. 6D and Fig. 5D, it can be clearly seen that the inter-gate dielectric layer 3 2 0 of Fig. 5A and Fig. 5D does not exist in Fig. 6A and Fig. 6D . Similarly, comparing Fig. 6B and Fig. 5B and Fig. 6C and Fig. 5C, it can be clearly seen that the inter-gate dielectric layer 3 2 0 of Fig. 5B and Fig. 5C consists of an inter-gate dielectric layer 3 2 a is formed only on the first / second floating gate layer 3 2 c / 3 14 c and the interlayer dielectric layer 312 a to form FIGS. 6B and 6C. Therefore, detailed descriptions of FIGS. 6A to 6D are omitted. According to Fig. 5A to Fig. 5D and Fig. 6A to Fig. 6D, it can be clearly observed that the common source / drain conductive pipeline as a bit line can provide a better than conventional buried layer diffusion layer.

526593 V. Description of the invention (22) There is a small pipeline resistance, a small pipeline stray capacitance relative to the substrate 300, and a small stray capacitance between the bit line and the word line; the first connection The metal layer as the word line can provide a smaller word line resistance than the silicided polycrystalline silicon gate line used in the prior art. Although the present invention is particularly illustrated and described with reference to the attached examples or connotations, it is only a statement rather than a limitation. Furthermore, the present invention is not limited to the listed details. For those who are jealous of this technology, it can be understood that changes of various shapes or details can be made without departing from the true spirit and paradigm of the present invention.

References US Patent 5, 364, 806 11/1994 Ma eta 1 5, 654,917 08/1997 Ogur aeta 1, 6, 051,860 04/2000 Odanaka.eta 6, 133, 098 10/2000 Ogur aeta 1 · 6, 248, 633 B1 06/2001 Ogur aeta 1. 6, 291, 855 B1 09/2001 Chang eta 1 · 6, 313, 501 B1 11/2001 K won Page 26 526593 Schematic illustration Figure 1 shows a brief construction diagram of the prior art Among them, FIG. 1A shows a cross-sectional view of a dual-bit flash memory cell and FIG. 1B shows a top-view construction diagram of FIG. 1A; FIG. 2 illustrates an indirect construction diagram of the present invention, of which FIG. 2A (a) A cross-sectional view of an auto-aligned multi-bit flash memory cell that does not disclose the first connotation of the present invention; FIG. 2A (b) An auto-aligned multi-bit reveal of the second connotation of the present invention A cross-sectional view of a flash memory cell; FIG. 2B discloses a top-view construction diagram of a contactless multi-bit flash memory array of the present invention; and FIG. 2C discloses a contactless multi-bit memory array shown in FIG. 2B A simplified circuit diagram of a bit flash memory array; Figures 3A to 3F reveal the system Process steps and sectional views of a shallow groove isolation structure for automatically aligning a multi-bit flash memory cell and a contactless multi-bit flash memory array according to the present invention; FIGS. 4A to 4N reveal Manufacturing steps and sectional views of manufacturing an automatic alignment multi-bit flash memory cell and a contactless multi-bit flash memory array of the present invention; FIGS. 5A to 5D disclose the first kind of the present invention A cross-sectional view of an auto-aligned multi-bit flash memory cell and its multi-bit flash memory array without contacts; and FIGS. 6A to 6D disclose an automatic Various cross-sectional views of the multi-bit flash memory cell and its multi-bit flash memory array without contacts.

Claims (1)

526593 6. Scope of patent application 1. An auto-aligned multi-bit flash memory cell including at least: a semiconductor substrate of a first conductivity type having an active area separated by two parallel shallow groove (ST I) areas Isolation, wherein each of the above-mentioned parallel shallow groove isolation regions is filled with a protruding field oxide layer; a cell region is formed on the semiconductor substrate and can be divided into two regions: a common source region and a gate region And a co-bubble area, wherein the gate area is located between the common source area and the co-bleed area; the common source area includes at least a first side wall dielectric cushion layer formed on one side of the gate area A side wall and a part of a first flat bed consisting of a common source diffusion region located in the active region and two etched first protruding field oxide layers located in the two parallel shallow groove isolation regions On the surface, a common source conductive line is formed on the first flat bed outside the first side wall dielectric cushion layer, and a first planarized thick silicon dioxide layer is formed on the common source conductive line and the The first side wall Over the cushion layer; the total: ¾ area includes at least one second side wall dielectric cushion layer formed on the other side wall of the gate area and placed on a common leakage diffusion area located in the active area and located in the On a part of the surface of a second flat bed composed of two etched flat second protruding field oxide layers of two parallel shallow groove isolation regions, a common leakage conductive line is formed on the second side wall dielectric The second flat bed outside the cushion layer, and a second planarized thick silicon dioxide layer are formed on the common leakage conductive pipeline and the second side wall dielectric cushion layer; the gate region includes at least An active region having a first floating gate layer formed on a first gate dielectric layer, a first floating gate structure, and a second floating gate layer formed on a second gate dielectric layer. 526593 6. The scope of the patent application is a second floating gate structure, a sandwich dielectric layer is formed between the first floating gate structure and the second floating gate structure, and a planarized control gate layer is composed of an inter-gate dielectric layer The partition is formed at least on the first floating gate structure, the interlayer dielectric layer, and the second floating gate structure; and a first connecting metal layer is simultaneously formed and etched together with the planarization control gate layer. To form a word line perpendicular to the common source / drain conductive pipeline. 2. The self-aligned multi-bit flash memory cell as described in item 1 of the patent application scope, wherein the first / second gate dielectric layer is a thermal silicon dioxide or nitrided thermal silicon dioxide layer As a penetrating dielectric layer, the thickness is between 80 angstroms and 120 angstroms. 3. The self-aligned multi-bit flash memory cell as described in item 1 of the scope of the patent application, wherein the first / second gate dielectric layer is a stone dioxide-silicon nitride-silicon dioxide (ΟΝΟ) or silicon nitride-silicon dioxide structure as a storage unit and its equivalent silicon dioxide thickness is between 50 angstroms and 100 angstroms. 4. Automatic as described in the first scope of the patent application Multi-bit flash memory cells are aligned, where the inter-gate dielectric layer is a silicon dioxide-silicon nitride-silicon dioxide (ON0) or silicon nitride-silicon dioxide structure and its equivalent dioxide The thickness of the silicon is between 80 angstroms and 120 angstroms and is formed at least in the first / second planarized thick silicon dioxide layer located in the common source / drain region and in the parallel shallow Page 29 526593 6. Scope of patent application The protruding field oxide layer in the groove isolation region, and the first / second floating gate and the sandwich dielectric layer in the active region. 5. The self-aligned multi-bit flash memory cell as described in item 1 of the scope of patent application, wherein the inter-gate dielectric layer is a thermally complex silicon oxide or nitrided thermally complex silicon oxide layer The thickness is between 100 angstroms and 300 angstroms and is formed only on the first / second floating gate layer and the interlayer dielectric layer of the active region. 6. The self-aligned multi-bit flash memory cell as described in item 1 of the scope of the patent application, wherein the above-mentioned co-source / drain conductive line is a highly doped polycrystalline silicon layer covering a metal silicide layer such as a Composition of tungsten silicide or other refracting metal silicide layer and the highly doped polycrystalline silicon layer as an impurity diffusion source forming a shallow highly doped diffusion region of the second conductivity type in the common source / drain diffusion region . 7. The self-aligned multi-bit flash memory cell as described in item 1 of the scope of patent application, wherein the above-mentioned first connection metal layer is a copper or copper layer placed on a barrier metal layer such as a nitride (T i N) or nitride group (T a N) layer and is formed on the third active layer and two side wall dielectric pads through a third mask dielectric layer. A hard mask layer is formed on each side wall of the mask dielectric layer. 8. Automatically align multi-bit flash memory as described in item 1 of patent application scope 526593 VI. Patent application scope cell, wherein the first conductivity type ion implantation region is formed in the semiconductor substrate under the second floating gate structure and includes at least one shallow ion implantation region as a threshold voltage. Adjust and apply a deep ion implantation area to form an anti-forbidden area. 9. The self-aligned multi-bit flash memory cell according to item 1 of the scope of patent application, wherein the planarization control gate layer is a planarized highly doped polycrystalline stone layer and the stone layer (si 1icided) has a metal oxide layer such as a titanium silicide (Ti Si 2) or cobalt silicide (CoSi 2) layer and can be a planarized silicide layer formed on a planarized highly doped polycrystalline silicon layer Within. 1 0. A contactless multi-bit flash memory array comprising at least: a semiconductor substrate of a first conductivity type having a plurality of parallel shallow groove isolation (ST I) regions and a plurality of active regions alternately forming the semiconductor substrate Each of the above-mentioned plural parallel shallow groove isolation regions is filled with a protruding field oxide layer; the plural common source pipeline regions and the plural virtual gate regions are alternately formed and parallel to the plural parallel shallow groove isolation regions. They are perpendicular to each other, wherein: each of the plurality of virtual gate areas includes at least one pair of gate areas formed on each side and a common leakage pipeline area is located between the pair of gate areas; each of the plurality of common source pipeline areas The area includes at least a pair of first side wall dielectric pads formed on each side wall of an adjacent virtual gate area and placed by a common source diffusion area located in the active area and in parallel shallow grooves. Every 526593 VI. A patented patent application covers an etched flat first protruding field oxide layer alternately formed on a first flat bed, and a common source conductive pipeline is formed on the pair of first side wall dielectric cushion layers. The first flat bed and a first planarized thick silicon dioxide layer are formed on the common source conductive pipeline and the pair of first side wall dielectric cushion layers; each of the common leak pipeline regions At least a pair of second side wall dielectric pads are formed on each side wall of the pair of gate regions and are disposed by a common leakage diffusion region located in the active region and a parallel shallow groove isolation region. A #flat second protruding field oxide layer alternately composed of a second flat bed, a common leakage conductive pipeline formed on the second flat bed between the pair of second side wall dielectric cushion layers, And a second planarized thick silicon dioxide layer is formed on the co-bleeding conductive pipeline and the pair of second side wall dielectric pads; a plurality of automatic alignment multi-bit flash memory cell units are formed on the plurality Each of the pair of gates in each of the virtual gates Wherein each of the above-mentioned plural auto-aligned multi-bit flash memory cells includes at least a first floating gate in the active region having a first floating gate layer formed on a first gate dielectric layer Structure and a second floating gate structure having a second floating gate layer formed on a second gate dielectric layer, and a sandwich dielectric layer formed on the first floating gate structure and the second floating gate structure And a planar control gate layer separated by an inter-gate dielectric layer formed at least on the first floating gate structure, the interlayer dielectric layer, and the second floating gate structure; and a complex digital line and The plurality of common source / drain conductive pipelines are formed perpendicular to each other, wherein each of the above-mentioned plurality of digital lines includes at least one first connection metal. Page 32 526593 6. The scope of the patent application belongs to the layer and the plurality of planarization control gate layers of each column are aligned on each of the plurality of active areas and two dielectric layers by having a third mask dielectric layer. The electric mask layer is formed on a hard mask layer of each side wall of the third mask dielectric layer for shaping and engraving. 1 1. The contactless multi-bit flash memory array according to item 10 of the scope of patent application, wherein the first / second gate dielectric layer is a thermal silicon dioxide or a thermal nitrided silicon dioxide The layer acts as a penetrating dielectric layer with a thickness between 80 angstroms and 120 angstroms. 1 2. The contactless multi-bit flash memory array according to item 10 of the patent application scope, wherein the first / second gate dielectric layer is a silicon dioxide-silicon nitride-silicon dioxide (〇N 0) or silicon nitride-silicon dioxide structure as a storage unit and its equivalent dioxide thickness is between 50 angstroms and 100 angstroms 1 3. As the scope of patent application No. 10 The contactless multi-bit flash memory array as described in the above item, wherein the inter-gate dielectric layer is a silicon dioxide-silicon nitride-silicon dioxide (NO) structure or a silicon nitride-silicon dioxide structure. The equivalent silicon dioxide thickness is between 80 angstroms and 120 angstroms and is formed at least on the first / second planarized thick silicon dioxide layer located in the common source / drain conductive pipeline area, located on the parallel shallow The protruding field oxide layer in the trench isolation region, and the first / second floating gate and the sandwich dielectric layer in the active region. Page 33 526593 6. Application for patent scope 1 4. The contactless multi-bit flash memory array as described in item 10 of the scope of patent application, wherein the inter-gate dielectric layer is a thermal compoundite Or nitride thermal polycrystalline silicon oxide layer with a thickness between 100 angstroms and 300 angstroms and formed only on the first / second floating gate layer and the sandwich dielectric in the active region Layer above. 1 5. The contactless multi-bit flash memory array as described in item 10 of the scope of patent application, wherein the common source / drain conductive line is a highly doped polycrystalline silicon layer covering a metal oxide layer For example, it is composed of a hafnium hafnium or other refracting metal silicide layer and the highly doped polycrystalline silicon layer serves as a shallow highly doped diffusion region of the second conductivity type in the common source / drain diffusion region. A dopant diffusion source. 16. The contactless multi-bit flash memory array as described in item 10 of the scope of patent applications, wherein the first connection metal layer is a copper or aluminum layer placed on a barrier metal layer such as titanium nitride (T i N) or nitride group (T a N) 1 7. The contactless multi-bit flash memory array as described in item 10 of the patent application scope, one of which is the first conductivity type The ion implantation region is formed in the semiconductor substrate under the second floating gate structure and includes at least one shallow ion implantation region as a threshold voltage adjustment and a deep ion implantation region to form a penetration prohibited region. . 526593 6. Scope of Patent Application 1 8. The contactless multi-bit flash memory array according to item 10 of the scope of patent application, wherein the planarization control gate layer is a planarized highly doped polycrystalline silicon layer and a metal silicide is silicided. The material layer is composed of a titanium silicide (T i S i) or Shi Xihuaming (C o S i 2) layer and can be a planar fossil oxide layer formed in a planarized highly doped polycrystalline silicon layer Composed of. 1 9. A contactless multi-bit flash memory array, comprising at least: a plurality of common source conductive bit lines formed in parallel in one direction; A plurality of pairs of multi-bit flash memory cells are formed between the plurality of common source conductive bit lines, wherein the above-mentioned plurality of multiple-source flash memory cells have a plurality of common source diffusion regions and the plurality of common source conductive positions The element lines are electrically connected; the plurality of co-leakage conductive bit lines are formed between the plurality of pairs of multi-bit flash memory cells, wherein the plurality of co-leakage diffusion regions of the plurality of pairs of multi-bit flash memory cells and The plurality of common leakage conductive bit lines are electrically connected; and The complex number line is connected to the complex control gate product of the complex pair of multi-bit flash memory cells and is simultaneously formed and perpendicular to the other direction, wherein the above complex number is related to the multi-bit flash memory cells. Each gate region includes at least a first floating gate structure having a first floating gate layer formed on a first gate dielectric layer and a second floating gate layer formed on a second gate dielectric layer A second floating gate structure; a sandwich dielectric layer is formed between the first floating gate structure and the second floating gate structure; an inter-gate dielectric layer is formed at least in the first floating gate structure and the second floating gate structure A floating gate structure and the interlayer dielectric layer; and a planarized conductive layer ϊ Page 35 526593 6. Scope of patent application The control gate is formed at least on the inter-gate dielectric layer. 20. The contactless multi-bit flash memory array as described in item 19 of the scope of patent applications, wherein each of the above-mentioned multiple digital lines is formed by a first connecting metal layer and the The plurality of control gate layers are simultaneously formed and etched by a hard cover curtain layer. Page 36