TW567611B - A scalable split-gate flash memory cell structure and its contactless flash memory arrays - Google Patents

Abstract

A scalable split-gate memory cell structure of the present invention comprises a common-source region, a scalable split-gate region being formed by a sidewall dielectric spacer, and a scalable common-drain region, wherein the scalable split-gate region comprising a floating-gate region being defined by another sidewall dielectric spacer has a tip-cathode line for erasing. The cell size of the present invention is scalable and can be made to be equal to 4F2 or smaller. The scalable split-gate flash memory cell structure is used to implement two contactless flash memory arrays: a contactless NOR-type flash memory array and a contactless parallel common-source/drain conductive bit-lines flash memory array for high-speed read/write/erase operations. Moreover, the contactless flash memory arrays can be fabricated with less critical masking steps as compared to the prior art.

Description

567611 V. Description of the invention (1) Background of the invention: (1) Scope of the invention The present invention relates to a sp 1 it-gate flash memory cell and its flash memory array, and in particular to a miniaturizable The (sea 1 ab 1 e) split-type flash memory cell has a controllable tipcat hode floating gate structure and its non-contact (c ntac 11 ess) flash memory array. (2) Description of the know-how. A split-type flash memory cell structure usually has a select-gate region and a gate-stack region, which can provide more than a st ack- ga te) flash memory cells have a relatively large cell size and often form a non-or (NOR) array. Figure 1A and Figure 1B show the two typical open flash memory cell structures. Figure 1A shows a floating gate formed by a split flash memory cell structure with local silicon oxide (LOCOS) technology. The length of the floating gate due to the formation of two bird's beaks at the two gate ends is usually longer than A minimum feature size (F) of the technology is large; a control gate layer 15 is formed on a portion of a local oxide layer 12 and a portion of a thicker selective gate oxide layer 14; a The polycrystalite oxidation (ρ ο 1 y-ο X ide) layer 1 3 is formed on a side wall of the floating gate layer 1 1; a source diffusion region 16 and a drain diffusion region 17 are automatically formed. The alignment is formed in a semiconductor substrate 100; and a thin gate dielectric layer 10 is formed in the floating gate.

567611 V. Description of the invention (2) Below layer 1 1. The split-type flash memory cell structure shown in FIG. 1A is written using a mid-channel hot-electron injection method. Therefore, the writing efficiency is higher and the writing power is higher than that of a conventional stack. The channel hot electron injection method used in the stack flash memory cell structure is small. In addition, the over-erasing problem of the open-cell memory cell structure can be avoided by a higher threshold-voltage of the selection transistor located in the selection gate area, thus scrubbing And verified control logic can be simplified. However, Figure 1A has some disadvantages: due to a non-automatic alignment control gate structure, the size of the cell is large; due to the misalignment between the control gate layer 15 and the floating gate layer 1 1, the gate length is not Easy to scale down; low coupling ratio (c 0up 1 ingrati 〇), larger control voltage applied during scrubbing; due to the weak shielding capability of the bird's beak of the local silicon oxide layer 12, the field emission of the floating gate layer 1 1 Tips are difficult to control; and forming a pronounced launch tip requires a high-temperature oxidation process. Figure 1B shows another open flash memory cell structure. A floating gate layer 2 1 is defined by a minimum line width (F) of the technology used; a thin penetrating silicon dioxide layer 2 0 Is formed under the floating gate layer 2 1; a selective gate oxide layer 2 2 is formed over a semiconductor substrate 100 and an exposed floating gate layer 2 1 in the selective gate region; a control gate layer 2 3 system Placed on the floating gate layer 21 and a part of the surface of the selective gate region; and a source diffusion region 24 and a double-diffused structure 2 5/2 6 are formed on the semiconductor substrate 10 respectively Within 0. According to Figure 1B, it can be clearly seen that, except that the scrubbing position is between the floating gate layer 21 and the double diffusion structure 2 5/2 6, the disadvantages similar to Figure A still remain.

567611 V. Description of the invention (3) Exist. Obviously, the double diffusion structure 2 5/2 6 is mainly used to eliminate the band-to-band penetration effect, but it becomes an obstacle to further miniaturization. Based on this, it is an object of the present invention to provide a micronizable and switchable flash memory cell structure having a micronizable cell size equal to 4F 2 or less. Another object of the present invention is to provide a controllable tip cathode structure of the miniaturizable open-type flash memory cell with a high scrubbing efficiency. It is a further object of the present invention to provide a manufacturing method with fewer rigorous masking steps. An additional object of the present invention is to provide two contactless array architectures for high-speed operation with low power consumption. Summary of the Invention: A miniaturized and openable flash memory cell structure of the present invention is formed on a semiconductor substrate of a first conductivity type having an active region and two shallow groove isolation (STI) regions, and At least one common source area, one miniaturizable trip area, and one miniaturizable co-leak area are included. The aforementioned miniaturizable trip area is located between the common source area and the micronizable co-leak area. The common source region includes at least a second conductivity type. A common source diffusion region is formed in the active region, and a first side wall dielectric cushion layer is formed on an outer side wall of the micronizable gate opening region. Above and placed by

567611 V. Description of the invention (4) A penetrating dielectric layer in the moving region and a part of a flat surface composed of two fourth protruding field oxide layers located in the two shallow groove isolation regions, A common source conductive line is formed on a first flat bed outside the first side wall dielectric cushion layer, and a first planarized thick silicon dioxide layer is formed on the common source conductive line. The common source diffusion region includes at least a shallow highly doped common source diffusion region formed in a lightly doped common source diffusion region and the first flat bed includes at least the shallow highly doped common source diffusion in the active region. A region and two fifth protruding field oxide layers located in the two shallow groove isolation regions. The miniaturizable opening area is defined by a third side wall dielectric cushion layer formed on an outer side wall of the common source area, and includes at least one outer side wall formed in the common source area. A floating gate area defined by a second side wall dielectric cushion layer above and a selective gate area located outside the floating gate area. One of the floating gate layers is placed above a thin penetrating dielectric layer. A portion of a conductive gate control layer formed on the semiconductor substrate in the active region of the floating gate region and a gate dielectric layer is formed on the first of the active regions of the selected gate region. Above an ion implantation area of conductivity type. The ion implantation area includes at least one shallow ion implantation area as a threshold voltage adjustment for selecting a gate transistor and a deep ion implantation area to form a breakdown prohibited area. The floating gate layer includes at least a first thermal polycrystalline silicon dioxide layer formed on an outer side wall of the floating gate layer adjacent to the selective gate region and a floating gate adjacent to the common source region. Between a backfilled silicon dioxide layer in an upper corner portion of the layer and a second thermally complex silicon dioxide layer is formed over the tip cathode line as a penetrating dielectric layer. A control gate conductive layer is covered with a coverage control

567611 V. Description of the invention (5) The gate-conducting conductive layer is formed on the floating gate area and the selective gate area of the miniaturizable sub-gate area as a conductive word line to form a first type of the present invention. A microscopic split-gate flash memory cell, in which a planarized silica layer is formed on the conductive layer of the overlay control gate. A metal word line and a planar control gate conductive island are placed on top of a control gate conductive island, are aligned on the active area and formed to form a second type of micronizable split-gate flash memory cell of the present invention. The conductive gate island of the control gate is formed on the floating gate layer in the floating gate region and the gate dielectric layer in the selected gate region. The above-mentioned miniaturizable co-leakage region includes at least a co-leakage diffusion region of the second conductivity type and a fourth side wall dielectric cushion layer formed on the other side wall of the micronizable gate opening region and Placed on a part of the surface of a second flat bed, wherein the co-drained diffusion region includes at least a shallow highly doped co-drained diffusion region formed in a lightly doped co-drained diffusion region and the second flat The bed includes at least the shallow highly doped co-drained diffusion region in the active region and two sixth protruding field oxide layers in the two shallow groove isolation regions. A metal bit line and a planarized co-bleeding conductive island integrated connection system are aligned on the active area to form the first type of micronizable and switchable flash memory cell of the present invention. A leakage conductive island is formed on the shallow highly doped co-bleeding diffusion region outside the fourth side wall dielectric pad. A co-bleeding conductive layer is covered with a co-bleeding conductive layer formed on the second flat bed outside the fourth side wall dielectric cushion layer to form a second type of micronizable split-gate of the present invention. In a flash memory cell, a second planarized thick silicon dioxide layer is formed on the covered and co-bleeded conductive layer.

567611 V. Description of the invention (6) The miniaturizable split-type flash memory cell structure of the present invention is used to form two types of non-contact flash memory arrays: a non-contact non-or type flash memory array and a Contactless parallel common source / drain conductive bit line flash memory array. The above non-contact non-OR flash memory array includes at least a plurality of active regions and a plurality of shallow groove isolation regions which are alternately formed on a semiconductor substrate of a first conductivity type, and the plurality of first type micronizable micro-switches. Flash memory cells are formed on the semiconductor substrate, a plurality of common source conductive pipelines are perpendicular to the plurality of active regions, and a plurality of metal bit lines and the plurality of first-type miniaturizable open-type flash memories The planarized and collectively drained conductive island integrated connection system of the cell is perpendicular to the plurality of conductive word lines. The non-contact parallel common source / drain conductive bit line flash memory array of the present invention includes at least a plurality of active regions and a plurality of shallow groove isolation regions alternately formed on a semiconductor substrate of a first conductivity type. Type II micronizable split-type flash memory cells are formed on the semiconductor substrate, and a plurality of common source conductive bit lines and a plurality of co-leakable conductive bit lines are alternately formed and perpendicular to the plurality of active regions. The plurality of metals The word line is integrated with the planar control gate conductive island on the control gate conductive island and is perpendicular to the plurality of common source / drain conductive bit lines. The size of each unit cell of the above-mentioned contactless flash memory array can be miniaturized and can be made equal to 4F 2 or less, using less rigorous masking steps than the prior art. Detailed description of the invention: Please refer to FIG. 2A to FIG. 2C, which discloses a method for manufacturing the present invention.

567611 V. Description of the invention (7) Process steps and cross-sectional views of a shallow recessed isolation structure of a flash memory cell structure capable of miniaturizing a split-type flash memory and its helmet contact flash memory array.

“FIG. 2 shows that a thin penetrating dielectric layer 3 0 1 is formed on a semiconductor substrate 300 having a first conductivity t; a conductive acoustic go 2 is formed on the thin penetrating dielectric layer 3 01 Then, a first electrical layer 30 is formed on the conductive layer 3 02; then, a plurality of mask photoresistors pR1 are formed on the first mask dielectric layer 3 0 3 to define a plurality of active layers. Area (aa) (below pR1) and multiple shallow groove isolations (^^ area (between PR1). The thin penetrating dielectric layer 301 is a thermal silicon oxide layer or a nitrided thermal layer The dioxide layer has a thickness between 70 angstroms and 120 angstroms. The conductive layer 302 is a heart-shaped polycrystalite or doped amorphous stone layer and is deposited using low-pressure chemical vapor deposition. j LPCVD) method to deposit 'its thickness is between 5 Angstroms and 4,000 Angstroms. «The first mask dielectric layer 3 0 3 is composed of silicon nitride and is deposited using the lpcVD method' Its thickness is between 1000 Angstroms and 3,000 Angstroms. It is worth mentioning here that the width and pitch of the multiple mask photoresist PR1 can be made using the technology used A minimum line width (F) is defined as shown in FIG two A.

FIG. 2B shows the first mask dielectric layer 3 0 3, the conductive layer 3 2 2, and the thin penetrating dielectric layer 301 between the plurality of mask photoresist PRs. The dry etching method is removed, and then the semiconductor substrate 300, which is located between the plurality of mask photoresists PR1, is anisotropically etched to form a plurality of shallow grooves, and then the plurality of mask photoresists is removed. PR1. FIG. 2B also shows that a planarized field oxide layer 3 0 4 a fills every gap between the first mask dielectric layer 3 03 a. The planarized field oxide 3 04a is composed of silicon dioxide, phosphorous glass (p-glass), or borophosphoric glass (BP-glass).

567611 V. Description of the invention (8) And using LPCVD, high-density plasma (HDP) CVD, or plasma enhanced (pE) CVD to deposit, first deposit a thick oxide layer 304 to fill the first Each gap between the mask dielectric layers 3 0 3a is then planarized by chemical mechanical polishing (CMP) and the thick oxide layer 30 is deposited and the first mask dielectric layer is formed. 3 0 3a acts as a polishing stop. FIG. 2C shows that the planarized field oxide layer 3 〇 4a is selectively etched back by a non-isotropic dry etching method to a depth equal to the first mask dielectric layer 3 〇 3a = ^ degrees; then using high temperature Phosphoric acid or non-isotropic dry etching method, except that the first mask dielectric layer 303a is violated to form a flat surface composed of a first protruding field oxide layer 304b and the conductive layer 302a; Then, a second mask dielectric layer 305 is formed on the flat surface. The second mask dielectric layer 305 is composed of silicon nitride and is deposited using the LPCVD method. Its thickness is between 500 angstroms and 15 angstroms. In Figure 2c, along the direction of an active area, such as a c_c, the lines are shown in Figure 38. It is worth mentioning here that there are some methods that can be used to form the flat surface shown in Figure 2c. For example, the first mask dielectric layer 3 03 can be composed of SiO2 and stacked using LPCVD method, and the first mask dielectric layer 3 0 3a and the thick silicon dioxide layer can be stacked. At the same time, the CMP method is used to add planarization; a plurality of mask photoresist PR1 can be directly formed on the conductive layer 302 ', and then a first mask dielectric layer is not required to form a plurality of shallow grooves, and then a first mask is formed by the CMP method. The field oxide layer 304b is protruding. However, the process steps of FIGS. 2A to 2C are more suitable for forming a lined with dioxide layer on the surface of the groove to eliminate defects caused by the groove.

567611 V. Description of the invention (9) ⑶ Referring now to FIG. 3A to FIG. 3J, which shows the manufacturing of a micro-dimensional switchable flash memory cell structure and a contactless flash memory array of the present invention— The manufacturing steps of a common platform structure and its sectional view. FIG. 3A shows that a plurality of mask photoresistors PR2 are formed on the second mask dielectric, 30 5 to define a complex scalable region (below pR2) and a complex common source region R 2). Each of the plurality of micronizable regions such as X1 F ^ shows that at least one pair of micronizable switching regions and a common micronizable wave f are formed between the pair of micronizable switching regions and the common source region such as F is marked = defined by a minimum line width (F) using the technology used. This value = It is mentioned that X 1 is a scaleable parameter. If X 1 is equal to 3, in this study: a unit cell 70 that can be miniaturized and opened flash memory cell structure is equal to 4F2. Generally, the unit cell size is equal to (1 + Xi) f2 and can be miniaturized through X i. 1 FIG. 2B shows the second mask I electrical layer located between the plurality of mask photoresist pr2. The 305 series uses a non-isotropic dry etching method to selectively & remove the multiple mask light. Resistance PR2. ', FIG. 3c shows that the conductive layer 3202a located in each of the plurality of common source regions is formed by an undercut shape using a clear etching method or an isotropic dry etching method. It is worth mentioning here that each of the plurality of scalable regions can be formed by the conventional oxidation process, and the grown oxide layer is reused by wet etching, but this method requires a high temperature oxidation step. Figure 3D shows that the etched hollow system is filled with the refilled oxidized stone layer 3 0 6b, and then the first protruding field oxygen in each of the plurality of common source regions

Page 13 567611 V. Description of the Invention (3) The compound layer 3 04b and an ex-situ stacking layer consisting of the thin penetrating dielectric alternating layer 3 0 5 a are thickened and the oxygen leveling is stopped to planarize the thickness. Level, then layer 3 0 1 a, 3 0 4 e, followed by the retention process, to be self-produced in the semi-doped co-source, and 4 ohms of the screen dielectric deposits as a cash back the top water-permeable dielectric Each layer is implanted with a lightly doped conductive layer 302b, which is sequentially added to the engraved surface to form: 30a and a fourth protruding field oxide layer 3004e. The backfilling process of the lower cavity can be filled with a thick layer of silica dioxide 3 06 to fill the gaps of the second cover and sand, and then planarize the layer using the CMP method. 〇5 & for layer bombardment; 耆 Use non-isotropic dry-etching method to selectively-liceize the silicon layer 3 0 6a to the surviving grave belt and return to the worm. 作 Make one of the electrical layers 3 0 2 b τΐ The oxide layer 3 0 4b is cut into the thin layer 2 h, and the thin layer is flattened to form the fourth protruding field oxygen to selectively remove the bit * the complex conductive layer 3 0 2b. Figure 3D again: the number; the dynamic alignment of the source region across the thin; the ion diffusion region W the complex number; the inside of each of the conductive type Ihe Figure E shows a pair of first The side wall dielectric pad is on the outer side wall of the micronizable region and is placed adjacent to the fourth protruding field oxide layer 3 0 4e and formed by 誃 9, a. The upper group is = the dielectric layer. 301 b on a part of the surface; then, the thin penetrating dielectric layer between the flat surfaces 3 0 8a of the pair ff; the 301a uses non-edged, dielectric padding or dilute hydrogen fluoride The acid is immersed in the bubble immersion method, and the dry etching layer 3 04_ is simultaneously etched to form a fifth doped oxide 3 0 4 f and the lightly doped common source diffusion region. 3 〇7a Alternate =% of the oxide layer artificially composed of a first

567611 V. Description of the invention (11) A flat bed is within each of the plurality of common source regions; then, a composite conductive layer 3 1 0 b / 3 0 9 b is formed in each of the plurality of common source regions. Above the first flat bed is used as a common source conductive line 3b / b; 3b; then, a first planarized thick silicon dioxide layer 31a is formed on the pair of first side walls. Each gap between the pads 3 0 8 a. The above-mentioned first side step dielectric layer 3 0a is composed of silicon dioxide and is deposited using the LpcVD method. First, a silicon dioxide layer 3 08 is deposited, and then the deposit is anisotropically etched back. The thickness of the silicon dioxide layer 308. It is worth noting here that before the silicon dioxide deposited is not etched back, an ion implantation process can be performed to automatically align the stacked silicon dioxide layer 308 and the thin penetration, An electrical layer 3 0 1 a is implanted with dopants within the semiconductor substrate 3000 to form a shallow highly doped common source diffusion region 3 of the first conductivity type 307 b on the lightly doped common source diffusion region 3 Within 0 7a. The above-mentioned composite conductive layer 31 0b / 309b includes at least one doped polycrystalline silicon layer 3 0 913 and is deposited by lCVD and covers a common source conductive layer 3101) such as a tungsten silicide (^ 丨 2) or tungsten (^ ) The layers are stacked by 1 ^ (^ 1) method or sputtering method. The above-mentioned doped polycrystalline silicon layer 309b can be further added with 12 Ϊ. The dopant in the interfacial agent is used as a dopant diffusion source to form a shallow highly doped common source diffusion of type ^ f 3 0 7b Within the lightly doped bazheng area 3 0 7a, a thickly doped polycrystalline silicon layer 3009 is deposited first, and the thickly doped polycrystalline stone layer 3/9 is deposited in force / surface. : Flat: Chemically doped polycrystalline stone takes a preset thickness. The source conductive layer 310b can be shaped using the same process steps of the doped polyspar evening layer 3009b. First planarized thick dioxygen

Page 15 567611 V. Description of the invention (12) '~ 一'-

The siliconized layer 3 1 1 a is composed of silicon dioxide, phosphorous glass, or borophosphoric glass M 碉 and is manufactured by LPCVD, HDPCVD, or PECVD. It is first connected to a pound of 70 and only one thick—silicon oxide Layer 311 to fill each gap of the pair of first side wall dielectric pads 308a, and then use the CMP method to planarize the stacked thick dioxin and fossils ^ and The second mask dielectric layer 3 0 5a acts as a grinding θ 31 1 Μ Τ 1 but Figure 2F shows that the second mask dielectric layer 3 0 5 a is selectively Liguron acid or anisotropic dry type. A pair of second side wall f electric cushion layers 312a are formed on a pair of floating closed areas 3 ° 2d wide adjacent to the dielectric wall of the first side wall. Then: The conductive layer 3 0 2c between the side wall dielectric pad layers 312a is selectively removed by non-etching method; the first step is to implant the dopant across the penetrating dielectric layer 301b in an automatic alignment. Impurities are in the layer of ==, between each of the plurality of active regions ㈡Γ :: an ion implanted region of the first conductivity type "3a. The second side wall dielectric pad Layer 31 2a is composed of The stacking of silicon nitride = it is first stacked-one nitrided ... 22 = = the thickness of the nitrided stone layer 312 that is stacked back. The dried = planted area 313 & contains at least one shallow ion cloth The planting area is two dotted lines as a dotted line; the threshold voltage switching transistor of the selection transistor in the selection area: 抿;: = as marked by the X: XX to form the selection = puncture more than (punch- thr〇Ugh area. Soak dipping “The 2 through Γ layer and 3 chuan system are removed by the special dry etching method of dilute chlorine gas acid, and are located in a plurality of shallow grooves 567611. 5. Description of the invention (13) The first of the isolation area The protruding field oxide layer 3 0 4b is also slightly etched to form a second protruding field oxide layer 3 0 4c, and then a thermal oxidation process is performed to form a dielectric spacer layer 3 1 2 a on the pair of second side walls. A gate dielectric layer 3 1 4a and a first thermal polycrystalline silicon dioxide layer 3 1 5 a within each of the plurality of active regions are formed on each side wall of the floating gate layer 3 0 2 d It is worth mentioning here that the thin penetrating dielectric layer 301b mentioned above may not be removed, and then a thermal oxidation process is performed. Here It can be clearly seen that a tip cathode line is formed in each of the plurality of floating gate layers, and the width of the tip cathode line is formed by the first thermally complex silicon dioxide layer 3 1 5 a and the backfilled silicon dioxide The distance between the layers 3 0 6 b is controlled and is between 100 angstroms and 300 angstroms. Fig. 3a shows that the pair of second side wall dielectric pads 3 1 2a selectively uses high-temperature phosphoric acid. Additive removal; then a thermal oxidation process is performed to form a second thermal polycrystalline silicon dioxide layer 3 1 6 a on each of the tip cathode lines, followed by a thermal annealing in a laughing gas (N 20) environment Process to form a nitrided first / second thermally complex silicon dioxide layer 3 1 5a / 3 1 6a and a nitrided gate dielectric layer 3 1 4a; then, a control gate conductive layer 3 1 7b is formed on the plurality of Micronization area; next, a pair of third side wall dielectric pads 3 1 8a are formed on the outer side wall adjacent to the first side wall dielectric pads 3 0 8 a and placed on the control gate A part of the surface of the conductive layer 3 1 7b is used to define a pair of micronizable switch-off regions and at the same time a micronizable co-leakage region is defined in the Between each of the plurality of scalable regions, between the pair of scalable gates. The thickness of the second thermally nitrided silicon dioxide layer 3 1 6 a is between 70 angstroms and 200 angstroms, and the first thermally nitrided silicon dioxide layer 3 1 5 a is nitrided. The thickness is between 200 angstroms and 300 angstroms. The above-mentioned control gate conductive layer 3 1 7b is doped with multiple crystals.

567611 V. Description of the invention (14) Silicon is formed by LPCVD method. A thick doped polycrystalline silicon layer 3 1 7 is deposited first, and then the deposited thick doped polycrystalline is deposited by CMP method or etch-back method. The silicon layer 3 1 7 is planarized, and then etched back to a predetermined thickness. The third side wall dielectric pad layer 3 1 8a is composed of silicon nitride and is deposited by LPCVD method. First, a silicon nitride layer 318 is deposited, and then the deposited silicon nitride layer 318 is etched back. A thickness. It is worth mentioning here that the thickness of the pad of the third side wall dielectric pad 3 1 8 a is controlled by the thickness of the stacked silicon nitride layer 3 1 8, so a micronizable component The control gate width of the gate area can be miniaturized. It must be emphasized here that the above-mentioned control gate conductive layer 3 1 7b may be a composite conductive layer and a doped polycrystalline silicon layer covered with a tungsten silicide (WSi 2) or tungsten (W) layer. FIG. 3I shows that a plurality of mask photoresistors PR3 are formed on the surface of the plurality of common source regions and a part of the surface of the adjacent micronizable switchable region; then, each of the plurality of micronizable regions is located The control gate layer 3 1 7b between the pair of third side wall dielectric pads 3 1 8a is etched back to a top surface level of the second protruding field oxide layer 3 04c, and then the second The field oxide layer 3 0 4 c is protruded to a top surface level of the gate dielectric layer 3 1 4 a, and then the remaining control gate conductive layer is anisotropically removed to form the gate dielectric layer 3. 1 4a and the third protruding field oxide layer 3 0 4d alternately constitute a flat surface; then, a dopant is implanted across the gate dielectric layer 31 4a in an automatic alignment manner to the semiconductor Within the substrate 300, a lightly doped co-drained diffusion region of the second conductivity type is formed in each of the plurality of active regions between the pair of third side wall dielectric pads 3 1 8a. Figure J shows the dielectric layer between the pair of third side wall dielectric pads 3 1 8 a.

567611 V. Description of the invention (15) The gate dielectric layer 3 1 4a is removed by dilute hydrofluoric acid and soaked or isotropically etched, and the third protruding field oxide layer 304d is also etched. To form a second flat bed; then, remove the multiple mask PR 3. Figure 2J again shows a pair of fourth side wall dielectric pads 3 2 0 & on the outer side wall adjacent to the miniaturizable trip zone and placed on a portion of the second surface. It is worth mentioning here that the etched back dielectric layer 3 2 0 is used to form the fourth side wall dielectric pad layer 32 0a, and the stacked dielectric layer cloth is automatically aligned. A dopant is implanted to form a shallow highly doped common region 3 1 9b of the second conductivity type within the lightly doped common leakage diffusion region 3 丨 9a. Therefore, 2 grounds are filled by the shallow highly doped collinear diffusion region 3i9b and the surface ... the conductive layer 3⑽ fills in the plural-micro = 个 pairs of each of the fourth side wall dielectric layers * °° four sides The side wall dielectric cushion layer 32 〇3 is made by Erong. The above method is used to accumulate, which is to accumulate a dioxin: Ersuo "and make use of it on the surface, and then return to the second accumulation of #: 化 :::: degree. The above-mentioned planarized co-bubble conductive layer 32 is stacked using LPCVD. First, a complex polycrystalline stone is deposited on the pair of fourth side wall dielectric pads 32 and 321 to use the CMP method. A gap between the mothers of the stacked thick conductors is stacked on the side of the electric conductor, and the two Lu Zhous are stacked. Figure 2J constitutes a prostitute. This kind of miniaturized split flash & ^ ° = mouth structure to make the hairy cryptic cell structure and its non-contact dry etching is formed by the eclipse photoresist before the accumulation of the flat bed, which can be discharged at high doses. Diffusion of the first one of the first flat structure of each of the LPCVD structures is made up of a thick filling bit 'then the pair of flashes worthy of the first

567611 V. Description of the invention (16) Memory array. Reference is now made to FIGS. 4A to 4C, which disclose the manufacturing steps of a miniaturized split-type flash memory cell structure and its non-contact non-or type flash memory array and its manufacturing steps following FIG. Sectional view. There are two methods that can be used to make a contactless NAND flash memory array. The first method: firstly implant the planarized co-draining conductive layer 3 2 1 a with a high dose of dopant of the second conductivity type, and then use a conventional automatic alignment process technology to silicide the Planarize the common leakage conductive layer 3 2 1 a to form a refractory metal petrified layer such as a petrified titanium (T i S i 2) or petrified diamond (CoS i D layer; then A metal layer 32 4 is formed on the surface of the formed structure; then the metal layer 3 2 4 together with the shattered planarized hump conductive layer 3 2 1 a—and formed by a mask photoresist step In order to form a plurality of metal bit lines 324a and silicidation planarization and co-leakage conductive islands, they are integrated. The above-mentioned metal layer 324 contains at least one copper (Cu) or aluminum (A1) layer in the form of a barrier metal ( barrier metal) layer such as a titanium nitride Θ (Τ ^ N) or nitride button (TaN) layer. The above mask photoresist step includes at least one mask photoresist aligned on the plurality of active regions. Or a plurality of hard masks ^ aligned on the plurality of active areas and a side wall dielectric pad shape & Count the hard cover screen dielectric layer on each side wall to eliminate misalignment ^. This process step is simpler, but each of the plurality of metal bit lines and the control gate conductive layer 3 丨 7c are conductive The stray capacitance between the word lines is very large, because the third side wall dielectric pad is composed of a high dielectric constant silicon nitride. Another method is shown in Figure 4A to Figure 4c, which can Provides smaller stray capacitance between the metal line and the conductive word line.

567611 V. Description of the invention (17) Figure, A shows that the above-mentioned planarized co-bleeding conductive layer 3 2 丨 & is selectively etched back by a non-isotropic dry etching method to remove the curved portion; then '4 pairs The first side wall dielectric cushion layer 3 0 8 a, the first planarized thick stone dioxide layer 3 1 1 a: and the fourth side wall dielectric cushion layer 3 2 0 a are also etched the same The degree of "continuation" of the third side wall dielectric pad 3a-8a described above is removed by using a high-temperature basic acid or an anisotropic dry etching method. Fig. 4B shows that a cover control gate conductive layer 322b is placed on each of the control gate conductive layers 317c, and then a planarized cover oxide layer 323a is formed on the cover control wide conductive layer 322b. The above-mentioned conductive control layer 32 2b includes at least one crane (w) or Shixihuahe crane (2) layer and is stacked by LPCVD method or sputtering method. A conductive layer 322 is first deposited to fill the back layer. Etch the fourth side wall dielectric pad layer 3 2 0b and etch back each gap between the first side edge = electric pad layer 308b, and then use the CMP method or the conductive layer 3 stacked 2 2 is planarized, and then the plane electrical layer is etched back to a preset thickness. The above planarized covering oxide 2 2 3 a is composed of silicon monoxide, phosphor glass, or borophospho glass and is deposited by f PCVD, HDPCVD, or PECVD, and a thick silicon dioxide layer is deposited first. 3 23 to fill each gap between the etched back side wall dielectric pad 30b and the etched back side wall dielectric pad 32b, and then use the CMP method or back The etching method planarizes the thick silicon dioxide layer 3 2 3. Similarly, the above-mentioned etch-back planarization and common-leakage conductive layer 321b can be implanted with a high-dose dopant of the second conductivity type, and then silicided by the conventional auto-aligned silicidation technology to form the refractive metal. Silicide layer 567611 V. Description of the invention (18) FIG. 4C shows that a metal layer 3 2 4 is formed on a formed structure surface; and the metal layer 324 together with the remnant planarization vapor-conductive layer 3 2 1 b is formed and etched at the same time by a mask photoresist step to form a plurality of metal bit lines 3 2 4 a and a planarized co-bleeding conductive layer 3 2 1 c. As mentioned above, the metal layer includes at least one copper (Cu) or aluminum (A1) layer to form a barrier metal layer; and the mask photoresist step includes at least a plurality of mask photoresist aligned to the plurality of active regions. The upper or plural hard mask dielectric layers are aligned on the plurality of active regions and a side wall dielectric pad is formed on each of the plural side walls of the plural hard mask dielectric layers. It can be clearly seen here that the 'complex high-conductivity word line 322 b / 3 1 7 c system is perpendicular to the complex metal only element line 3 2 4 a, and each of the complex metal bit line 3 2 4 a It is separated from the plurality of highly conductive word lines 3 2 2b / 3 17c by a planarization covering the silicon dioxide layer 3 2 3a. It can also be clearly seen here that the thickness of the second mask dielectric layer 305 described in FIG. 2c is between 10,000 angstroms and 1,500 angstroms. * The thickness of the oxidation second layer 323a is between 5000 angstroms and 1000 angstroms. Therefore, each of the plurality of metal bit word lines 3 2 4 a and the plurality of high conductive word lines 3 2 2 The stray capacitance between b / 3 1 7 c is small. Please refer to FIG. 5A to FIG. 5C, which reveals that following FIG. 3j, a miniaturized split-type flash memory cell structure of the present invention and its contactless parallel co-source / bleed line flash memory are disclosed. Array. FIG. 5A shows that the planarized co-bleeding conductive layer 3 2 1 a is selectively faced back to a thickness approximately equal to the common source conductive layer 3 9 9b; and then a high-dose dopant of the second conductivity type is implanted. Impurities are in the common vapor conductive layer 3 2 5 b; ~ covering the conductive layer 3 2 6 b is formed on the co-foam conductive layer 3 2 5 b,

Μ

Page 22 567611 V. Description of the invention (19) As a common vapor conductive bit line 3 2 6b / 32 5b within the mother of the multiple common leakage area; then, a second planarized thick silicon dioxide layer 3 2 7a is formed on the common leakage potential between the pair of fourth side wall dielectric pads 3 2 0a = line 3 2 6b / 3 2 5b. The above-mentioned co-bleeding conductive layer 325b is composed of a doped polycrystalline spar layer and is deposited by the LPCVD method, and is formed by the same process steps of the co-source conductive layer 309b described above. The above-mentioned covered common-leakage conductive layer 3 2 6b includes at least one tungsten silicide or tungsten layer and is stacked by using the lpcVd method or Tibetan plating. The covered common-source conductive layer 3 1 0 b uses each of the plurality of common source regions. The same process steps are used to form.

FIG. 5B shows the pair of first side wall dielectric pads 308a, the first planarized thick oxide; ε layer 3 1 1a, the pair of fourth side stepped dielectric layers 3 2 0 a, and the first planarized thick silicon dioxide layer 3 2 7a is a non-isotropic dry etching or wet etching plus selective etchback to remove the curved portion; then, the pair of third side walls The dielectric cushion layer 318 is removed by high temperature phosphoric acid or non-isotropic dry-etching method. Then, a planarization control gate conductive layer 3 28a is formed on the edge side of the first side wall dielectric layer 3 〇8 And the etch back on the control gate conductive layer 3 1 7 c between the fourth side wall dielectric pad layer 320 b. The above-mentioned planarization control gate conductive layer 3 28a is made of tungsten, tungsten silicide, or other metal, and is lined with (1 1 nedwith) a barrier metal layer (not shown) such as a titanium nitride (T i N) or It consists of tantalum nitride (T a N) layer. The above-mentioned control gate structure is firstly deposited a barrier metal layer on the formed structure surface, and then a highly conductive layer 3 28 fills the dielectric pad layer 3 8b located on the first side wall of the etch back and the etch back Each gap between the fourth side wall dielectric pad layer 32b, and then the CMP method or etch-back method is used to flatten the stacked highly conductive layer 328.

Page 23 567611 V. Description of the invention (20) ^ ~~ FIG. 5C shows that a metal layer 3 2 9 is formed on a formed structural surface, and the metal layer 329 together with the planarization control gate conductive layer 328 & is placed on the control gate conductive layer 317c while borrowing a cover The curtain photoresist step is opened to form a plurality of metal word lines 3 2 9 a and a planar control gate conductive island 3 2 8 b is integrated on the control gate conductive island 3 1 7 d. . Similarly, the above-mentioned metal layer 329 includes at least a copper layer or a layer formed on a barrier metal layer such as a titanium nitride (TiN) or nitride button (TaN) layer. The above mask photoresist step includes at least a plurality of mask photoresistors aligned on the plurality of active regions or a plurality of hard mask dielectric layers aligned on the plurality of active regions and a side wall dielectric cushion layer is formed. Over each side wall of the plurality of hard mask dielectric layers to eliminate misalignment. It can be clearly seen here that the above-mentioned plurality of metal word lines 3 2 9a are perpendicular to the complex common source conductive bit line 310b / 3 0 9b and the complex common drain conductive bit line 3 2 6b / 3 2 5b . FIG. 6A shows a top-view layout diagram of a non-contact non-or-type flash memory array according to the present invention, wherein the plurality of active regions (AA) and the plurality of shallow groove isolation regions (ST I) are alternately grounded. Formed on the semiconductor substrate 300; the plurality of conductive word lines (WL) are formed between the plurality of common source regions and the plurality of scaleable common leakage regions; each of the plurality of common source regions includes at least one A pair of first side wall dielectric pads 3 0 8b and a common source conductive pipeline (CSBL) are formed between the pair of first side wall dielectric pads 3 0 8b; Each of which includes at least a plurality of planarized common-leakage conductive islands 3 2 丨 c and the plurality of metal bit lines 324a are integrated and connected; a plurality of tip cathode lines 316a are formed at

567611 V. Description of the invention (21) Between the first thermally multicrystalline silicon dioxide layer 3 1 5a and the backfilled silicon dioxide layer 3 0 6 b in the floating gate area. As shown in FIG. 6A, if X corpse 3, the size of a unit cell is equal to 4 F 2; and the floating gate area, the micronizable sub-gate area, and the micronizable co-leakage area are formed by pads. Layer formation techniques are defined and can be miniaturized. FIG. 6B shows a top-view layout diagram of a contactless parallel common source / drain conductive bit line flash memory array according to the present invention, wherein the complex active area (AA) and the complex shallow groove isolation area (STI) ) Are alternately formed on the semiconductor substrate 300; the complex common source conductive bit line (cSBL) and the complex common drain conductive bit line (CDBL) are alternately formed and are in contact with the complex active region Each other is vertical; each of the plurality of common source conductive bit lines (CSBL) is formed between the pair of first side wall dielectric pads 3 0 8b; the plurality of common leaked conductive bit lines (CDBL) Each is formed between the pair of fourth side wall dielectric pads 32b; the plurality of metal word lines (WL) and the planarized control gate conductive island 3 28b are placed on the control gate conductive island 3 1 7 The integrated connection above d is perpendicular to the complex common source conductive bit line (CSBL) and the complex common drain conductive bit line (CDBL); each of the floating gate areas includes at least a complex tip cathode line 3 丨6 a, and each of the plurality of tip cathode wires 3 1 6 a is interposed between the first thermal polycrystalline silicon dioxide layer 3 1 5 of the floating layer a and the back-filled silicon dioxide layer 3 06 b. As shown in FIG. 6B, if X is 3, the size of a unit cell is equal to 4 F 2, and the floating gate area, the micronizable sub-gate area, and the micronizable co-leakage area are formed by pads. Layer formation techniques are defined and can be miniaturized. According to the above explanations, the features and advantages of a miniaturizable open-type flash memory cell structure and a contactless flash memory array of the present invention

567611 V. Description of the invention (22) The conclusion is as follows: (a) The miniaturizable and open-type fast-layer technology of the present invention provides an i, ° membrane cell structure that can be borrowed to make the cell area smaller than the 4F domain. (b) In the present invention, the micronizable gate can be controlled by a controllable tip cathode wire. The internal cell structure provides a scrub to the control gate. (C) The electricity stored in the floating gate layer (C) The miniaturizable tap point flash memory array of the present invention can ... Masking steps to manufacture. (d) The contactless element line and the planarized co-lead-conducting type flash memory array of the present invention provides a complex S-conductor β island integration connection with a plurality of metal plane capacitances, and has low spurious connection for high-speed reading. / Write / hold, 4 源 source conductive pipelines, and multiple conductive word lines for / label operation. (e) The non-contact row of the present invention provides a plurality of metal a green sheets, and the source / drain potential is integrated on the flash memory array island. The conductive island is placed on the control gate and the planar control gate. The high-speed read / write / swipe operation is based on the common source of the / bleed conductive bit line with two and f having lower interface stray capacitance. The present invention is #Special, manifested and explained, but the examples and connotations shown in * are used as an example to "state rather than limit. Furthermore, the present invention is not limited to all

n

567611

Page 567611 Brief Description of Drawings Figures 1A and 1B show a brief cross-sectional view of the prior art, of which Figure 1A shows a gated flash memory cell with a local silicon oxide (LOCOS) technology A cross-sectional view of a tip cathode floating gate structure; Figure 1B shows a cross-sectional view of a split flash memory cell with a source-side scrub. FIG. 2A to FIG. 2C show the manufacturing steps of a shallow groove isolation (ST I) structure for manufacturing a miniaturized split-type flash memory cell structure and a contactless flash memory array of the present invention, and FIG. Sectional view. FIG. 3A to FIG. 3J show the manufacturing steps and cross-sectional views of a common platform structure for fabricating a scalable flash memory cell structure and a contactless flash memory array of the present invention. Figures 4A to 4C disclose the manufacturing steps and cross-sectional views of the miniaturized split-type flash memory cell structure of the present invention and its non-contact non-or type flash memory cell array following Figure 3J. FIG. 5A to FIG. 5C disclose the manufacturing steps of the miniaturized split-type flash memory cell structure and the contactless parallel source / drain conductive bit line flash memory array following FIG. 3J. And its section. FIG. 6A and FIG. 6B disclose top-view layout diagrams of the present invention, wherein FIG. 6A discloses a top-view layout diagram of a non-contact non-or-type flash memory array; FIG. 6B illustrates a contactless parallel A top-view layout of a common source / drain conductive bit line memory array. Drawing number comparison description

567611 301 thin 303 first material layer 3 04b first material layer 3 04d first material layer 3 04 f first material layer 305 first layer 3 0 7a light diffusion region 3 08a first wall dielectric layer 3 0 9b co-layer silicon dioxide layering Thick silicon dioxide layer, electric pad layer 314a, gate oxide layer, oxide layer 317d, electric control layer 319a, light diffusion 1 ^ 32 0a, wall dielectric layer 321a, flat island 3 22b, silicon oxide layer 324a, gold 326b, Silicon oxide layer penetrates the dielectric layer, masks the dielectric layer & field oxide layer, two protruded field oxide layers, five protruded field oxide layers, two masked dielectric layers, doped common source diffusion region, one side wall dielectric Underlayer source conductive layer dielectric layer diagram brief description 300 semiconductor substrate 3 0 2 conductive layer 3 0 4 a planarization field oxidation 3 0 4c second protruding field oxygen 304e fourth protruding field oxygen 304 g sixth protruding field oxygen 3 0 6 b backfill silicon dioxide 3 0 7 b shallow highly doped common source 3 0 8b etch back the first side 31 b to cover common source conductivity 311 a first planarization thickness 311 bBack to the first plane 3 1 2 a Second side wall 313a Ion implantation area 3 1 5 a First thermal compound 2 3 1 6 a Second thermal compound 2 3 1 7 c Control gate conductive layer 3 1 8 a third side wall 3 1 9 b shallow highly doped co-macro 3 2 0 b back to the fourth side 3 2 1 b planarization co-vapor conductance 3 2 3a planarization covering two 325 b Conductive layer 327a The first planarized thick gate conductive island is intermixed with the four side wall dielectric cushion layers of the co-leakage diffusion area.

567611 Brief description of the diagram 3 2 7b Etching back the second planarized thick silicon dioxide layer 3 2 8a Planarization control gate conductive layer 3 28b Planarization control gate conductive island 3 2 9 a Metal word line Page 30

Claims (1)

567611 VI. Scope of patent application 1. A miniaturizable open-type flash memory cell structure including at least: a semiconductor substrate of a first conductivity type having an active region formed between two shallow groove isolation regions; A cell region includes at least one co-originated region, a micronizable switchable region, and a micronizable co-leakage region. The aforementioned micronizable switch-off region is located in the co-sourced region and the micronizable co-leakage region. The interval is defined by a third side wall dielectric cushion layer formed on an outer side wall of the common source area; the common source area is located on a side edge portion of the miniaturizable switching area A common source diffusion region containing at least a second conductivity type is formed in the semiconductor substrate of the active region, and a first side wall dielectric cushion layer is formed on a side wall of the miniaturizable trip region. And a first flat bed is formed outside the first side wall dielectric pad, wherein the first flat bed is formed by the common source diffusion region located in the active region and the two shallow grooves Two fifth processes A field oxide layer; the miniaturizable co-leakage region is located on the other side of the miniaturizable trip zone and includes at least a co-leakage diffusion region of the second conductivity type formed in the semiconductor of the active region In the substrate, a fourth side wall dielectric cushion layer is formed on the other side wall of the miniaturizable switching area, and a second flat bed is formed on the fourth side wall dielectric cushion layer. In addition, the above-mentioned second flat bed is composed of the co-leakage diffusion region located in the active region and two sixth protruding field oxide layers located in the two shallow groove isolation regions; the micronizable opening gate Area includes at least one floating gate area formed by a second side wall dielectric cushion layer formed on an outer side wall of the common source area Page 31 This layer is layered. The near broken oxygen layer is connected to silicon dioxide, which is crystallized by oxygen and oxygen to form a bis-reoxygenated crystal. A drop line with an upper corner pole containing a square yin on the wall and the end of the wall to the side of its apex structure is described in the outer area of the sluice gate, the source of which floats in the drift zone, and the The gate is close to the shape of the silicon layer 567611. 6. Definition of patent application scope and a selection gate area is located between the floating gate area and the miniaturizable co-leakage area. The above floating gate area contains at least A floating gate structure is formed on a penetrating dielectric layer of the active area and a control gate conductive layer or a part of a control gate conductive island is formed at least on the floating gate structure and the selected gate area contains at least The control gate conductive layer or another part of the control gate conductive island is formed on at least one gate dielectric layer of the active area; and 2. A micronizable split-gate type as described in item 1 of the scope of patent application Flash memory cell structure, one of the common source conductive pipelines One doped polycrystalline silicon layer is implanted with a high-dose dopant of the second conductivity type and covered with a tungsten silicide (WSi 2) or tungsten (W) system formed on the first flat bed And a first planarized thick silicon dioxide layer is formed on the common source conductive pipeline. 3. The miniaturizable split-gate flash memory cell structure described in item 1 of the scope of the patent application, wherein the control gate conductive layer includes at least one doped polycrystalline silicon layer implanted with the second conductive type A high-dose dopant is covered with a tungsten silicide (WS i 2) or tungsten (W) as a conductive word line and a P. 32 Yi Zai overlaid on the wall. Note that on the side of the system, the element flashes on the side of the island, the cells on the side of the island are fast, and the electric wall is thin. One of the control standards for fast shrinking islands is high control. Each type of micro-electricity in the pair is controlled by a blocking gate that can guide a flat island curtain with a light-level main gate on the side. A pair of hoods that control the electricity and guide a micro-projection can be described in 20% by a layered type. The second group controls the electricity and harden the surrounding area. The screen is in a kind of advantage, the plant or flat system is covered with a special cloth tungsten. The structure is formed. Please form an island and connect the hard layer group. Shenyuan Silicon Silicon wire pads. Attachment or mediation 567611 6. Patent application scope A flat cover silicon dioxide layer is formed on the conductive word line to form a first type of micronizable and switchable flash memory cell. 5. The miniaturizable open-type flash memory cell structure described in item 1 of the scope of the patent application, wherein the planarization and co-leakage conductive island includes at least one doped polycrystalline silicon island implanted with the second conductive type A high-dose dopant is formed at least on the co-bleeding diffusion region of the second flat bed and a metal bit line is integrated with the planarized co-bleeding conductive island integrated system through a mask light A resist is aligned on the active area or a hard cover screen dielectric layer is aligned on the active area and a side wall dielectric pad is formed on each side wall of the hard cover screen dielectric layer. Shaped to form a first type of micronizable, open-type flash memory cell. 6. Miniaturizable open-type flash memory as described in item 1 of the scope of patent application Page 33 567611 VI. Patent application cell structure, where a co-bleeding conductive pipeline contains at least one doped polycrystalline silicon layer implanted with a high-dose dopant of the second conductivity type and covered with a tungsten silicide A (WS i 2) or tungsten (W) layer is formed on the second flat bed and a second planarized thick silicon dioxide layer is formed on the co-bleeding conductive pipeline to form a second type of scalable Split-type flash memory cell 7. The structure of the splittable split-type flash memory cell described in item 1 of the patent application scope, wherein the above-mentioned co-source diffusion region includes at least one shallowly doped co-source The diffusion region is formed in a lightly doped co-source diffusion region and the co-drained diffusion region includes at least a shallow highly doped co-drained diffusion region formed in a lightly-doped co-drained diffusion region. 8. The miniaturizable split-type flash memory cell structure as described in item 1 of the scope of the patent application, wherein an ion implanted region of the first conductivity type is formed in the gate dielectric layer of the selected gate region The lower part includes at least one shallow ion implantation area as a threshold voltage adjustment and a deep ion implantation area to form a breakdown-resistant region. 9. A contactless and scalable flash memory array comprising at least: a semiconductor substrate of a first conductivity type having a shallow groove isolation (ST I) structure, wherein the above-mentioned shallow groove isolation structure is at least Alternately formed on the semiconductor substrate including a plurality of active regions and a plurality of shallow groove isolation regions; Page 34 567611 6. The scope of the patent application. The plural common source areas and plural miniaturizable areas are alternately formed on the shallow groove isolation structure and are perpendicular to the plural active areas. Among them, the aforementioned plural micronizable areas Each contains at least a pair of miniaturizable trip zones defined by a pair of third side wall dielectric pads formed on the outer side walls adjacent to the common source area and a miniaturizable co-bleed zone Each of the plurality of common source regions includes at least one second conductivity type common source diffusion region formed in the semiconductor substrate of the plurality of active regions, a pair of first sides A side wall dielectric cushion layer is formed on the outer side wall adjacent to the miniaturizable trip zone, and a first flat bed is located between the pair of first side stepped dielectric layers by the common source diffusion area and A fifth protruding field oxide layer is alternately composed of a common source conductive line system formed on the first flat bed and a first planarized thick silicon dioxide layer system formed on the pair of first sides This common source conduction between the sidewall dielectric pads Above the electrical pipeline; the miniaturizable co-leakage area includes at least the second conductivity type co-leakage diffusion area formed in the semiconductor substrate of the plurality of active areas, and a pair of fourth side wall dielectric cushion layers are formed A co-drained diffusion region and a sixth protruding field oxide are formed on the outer side wall adjacent to the miniaturizable trip zone and a second flat bed is located between the pair of fourth side wall dielectric cushions. The layers are alternately composed, wherein a plurality of planarized common-leakage conductive islands are formed at least on the plurality of common-leakage diffusion regions of the second flat bed; each of the pair of micronizable trip gates includes at least one floating gate region Defined by each of a pair of second side wall dielectric pads formed on the outer side wall adjacent to the common source region and a selection gate region is located in the floating gate region 567611 6. Between the scope of the patent application and the miniaturizable co-leakage area, the above floating gate area includes at least a plurality of floating gate structures formed on the dielectric layer of the plurality of active areas and a conductive gate control layer. A part is formed at least on the plurality of floating gate structures and the selected gate region includes at least the control gate conductive layer, and another part is formed at least on the gate dielectric layer of the plurality of active regions; the plurality of floating gate structures; Each includes at least one tip cathode line formed between a first thermal polycrystalline silicon dioxide layer formed on an outer side wall thereof and a backfilled silicon dioxide layer close to a corner portion of the common source area, The above-mentioned tip cathode wire has a second thermal polycrystalline silicon dioxide layer formed on top of the tip as a penetrating silicon dioxide layer; a control gate conductive layer is formed on the control gate conductive layer as a A conductive word line, wherein a planarized silicon dioxide layer is formed on the conductive layer of the cover control gate; and a plurality of metal bit lines co-leak with the planarization The electric island integrated connection is formed at the same time by a mask photoresist step, wherein the above mask photoresist step includes at least a plurality of mask photoresist aligned on the plurality of active areas or a plurality of hard mask dielectric layers. Aligned on the plurality of active areas and a side step dielectric layer is formed on each side wall of the plurality of hard mask dielectric layers to be formed. 10. The contactless and scalable micro-gate flash memory array as described in item 9 of the scope of the patent application, wherein the control gate conductive layer includes at least one doped polycrystalline silicon layer implanted with the second conductive layer. A high-dose dopant and the covering control gate conductive layer includes at least one tungsten silicide (WS i 2) or tungsten (W) layer 567611 VI. Scope of patent application 1 1 · The contactless, scalable, and split-type flash memory array as described in item 9 of the scope of patent application, in which the above-mentioned year * facetted conductive islands contain at least one doped complex The crystalline silicon island is implanted with a high-dose dopant of the second conductivity type and silicided with a refractive metal silicide layer such as a titanium silicide (TiSi 2) or cobalt silicide (CoSi 2) layer and the metal bit line. At least one copper (Cu) or aluminum (A 1) layer is formed on a barrier metal layer such as a titanium nitride (τn) or a nitride button (TaN) layer. 1 2. The contactless, scalable, split-gate flash memory array as described in item 9 of the scope of patent application, wherein the common source conductive pipeline includes at least one doped polycrystalline silicon layer implanted with the second conductive layer Type is a high-dose dopant and is covered with a tungsten silicide (WS i D or tungsten (w) layer. 1 3 · The contactless, scalable, and switch-off type described in item 9 of the scope of patent application A flash memory array, wherein an ion implanted region of the first conductivity type is formed below the gate dielectric layer and includes at least one shallow ion implanted region as a threshold voltage adjustment and a deep ion implanted region to form One forbidden zone 14. A contactless, scalable mini-memory flash memory array comprising at least a semiconductor substrate of a first conductivity type having a shallow groove Page 37 567611 VI. Patent application range separation (ST I) structure, wherein the above-mentioned shallow groove isolation structure includes at least a plurality of active regions and a plurality of shallow groove isolation regions alternately formed on the semiconductor substrate; a plurality of common sources The area and the plurality of micronizable regions are alternately formed on the shallow groove isolation structure and are perpendicular to the plurality of active regions, wherein each of the plurality of micronizable regions includes at least one pair of micronizable openings. And a deflatable co-leakage zone are located between the pair of deflatable open gates; each of the plurality of common source regions includes at least one second type of common source diffusion region formed in the plurality of active regions. Inside the semiconductor substrate, a pair of first side wall dielectric pads are formed on the outer side wall adjacent to the miniaturizable trip zone, and a first flat bed is located on the pair of first side wall dielectric pads. The layers are alternately composed of the common source diffusion region and a fifth protruding field oxide layer. A common source conductive line is formed on the first flat bed and a first planarized thick silicon dioxide. Layer system On the common source conductive pipeline located between the pair of first side wall dielectric pads; the micronizable co-leakage area including at least the second conductivity type co-leakage diffusion area is formed in the plurality of active areas Within the semiconductor substrate, a pair of fourth side wall dielectric pads are formed on the outer side walls adjacent to the miniaturizable trip zone, and a second flat bed is located on the pair of fourth side wall dielectrics. The electric pads are alternately composed of the co-bleeding diffusion region and a sixth protruding field oxide layer. A co-leaking conductive line is formed on the second flat bed and a second planarized layer is formed. A silicon oxide layer is formed on the co-bleeding conductive line between the pair of fourth side wall dielectric pads; each of the pair of miniaturizable trip zones includes at least one floating gate zone 567611 VI. The scope of patent application is defined by each of a pair of second side wall dielectric cushions formed on the outer side walls adjacent to the common source area and a selection gate area is located in the floating gate area and the Between the scaleable common leakage areas, the above floating gate area includes at least a plurality of floating gate structures formed on the penetrating dielectric layer of the plurality of active areas and a part of a conductive gate of a control gate is formed at least in the plurality Above each of the floating gate structures and the selected gate region includes at least another portion of the control gate conductive island formed at least on a gate dielectric layer of each of the plurality of active regions; Each includes at least one tip cathode line formed on a side wall of a first thermal polycrystalline silicon dioxide layer and a backfilled silicon dioxide layer close to a corner portion of the common source region, wherein The above-mentioned tip cathode line has a second thermal polycrystalline silicon dioxide layer formed on top of its tip as a penetrating silicon dioxide layer; a planarized control gate conductive island is formed on the control channel. Above the electric island; and a plurality of metal word lines and the planarized control gate conductive island are placed on the control gate conductive island in an integrated connection while being formed by a mask photoresist step, wherein the aforementioned mask photoresist The steps include at least a plurality of mask photoresistors aligned on the plurality of active regions or a plurality of hard mask dielectric layers aligned on the plurality of active regions and a side wall dielectric cushion layer forming the plurality of hard mask screens. Electrical layers are formed on each side wall. 1 5. The contactless, scalable, flash-type flash memory array as described in item 14 of the scope of patent application, wherein the above-mentioned common source conductive bit line includes at least one Page 39 567611 6. Application scope: Miscellaneous, crystalline silicon layer is implanted with a high-dose dopant of the second conductive crack, covered with a tungsten silicide (WSi 2) or tungsten (W) layer. 6 · The contactless shrinkable open-type flash memory array as described in item 14 of the scope of the patent application, wherein the above-mentioned co-bleeding conductive bit line contains at least one polymorphite layer fabric A second dose of dopant is implanted with a dopant and is covered with a tungsten silicide (WS i 2) or tungsten (W) layer. 1 7 · As described in item 4 of the scope of the patent application, the non-contact, scalable, split-gate flash memory array, centering the above-mentioned control gate conductive islands includes at least one doped polycrystalline silicon island and the planarization control The gate conductive islands include at least one tungsten silicide (WSi2) or tungsten (w) island. Non-contact, micronizable, switch-off type 18. As described in item 14 of the scope of patent application, it includes a copper (Cu) flash memory array, in which the above-mentioned metal characters ^ titanium nitride (TiN) or inscription (A 1) The layer is formed on a barrier metal layer or a nitride layer (T a N). A contactless, scalable, open-type 19 · An ion implanted area flash memory array as described in item 14 of the scope of the patent application, where the above-mentioned adjustment of the / conductor voltage and a Contains at least one shallow ion implantation area to serve as a ^: deep ion implantation area to form a resistance to forbidden soil & no-contact micronizable separation type 2 〇 · As described in item 4 of the patent application scope " ,, 567611 Page 41