TW525298B - Manufacturing method of stacked-gate flash memory array - Google Patents

Abstract

A manufacturing method of stacked-gate flash memory array is disclosed, wherein a shallow trench isolation (STI) structure that comprises plural parallel arranged STI lines and plural active region lines among the STI lines is formed on a semiconductor substrate. Each active region line has a main floating gate put on a thin tunneling dielectric layer and each STI line has two separated extending floating gates put on the sides of a planarized field oxide layer. The main floating gate and two extending floating gates are connected to be a self-aligned integrated floating gate layer to greatly increase the coupling ratio of the stacked gate flash memory cell. The plural word lines and STI lines are vertically arranged by each other on the STI structure, wherein the control gates are composed by a complex conduction layer that consists of a metal or metal silicide, a barrier metal and a highly doped polycrystalline or amorphous silicon and the top, bottom and two sides are enveloped by a dielectric layer. The word line parasitic capacitor is greatly reduced. The common source/drain of the stacked flash memory cell uses self-aligned source/drain landing island to form contacts and proceed a self-aligned shallow/heavy doped ion implantation. The contacts problem of shallow source/drain area and punch-through of short channel length are then prevented. The self-aligned source/drain landing island is composed by a silicide heavy doped polycrystalline or amorphous silicon. The inter-connection resistance among stacked flash memory cells is also greatly reduced. The self-aligned source/drain lines are composed by a silicide heavy doped polycrystalline or amorphous silicon and located on the flat plane that is formed by a common source/drain area and a field oxide layer to be the contact and self-aligned shallow/heavy doped source/drain area. The contact issue of shallow source/drain is thus solved. Besides, the self-aligned common source/drain resistance, parasitic capacitor between the source/drain and substrate and junction leakage are greatly reduced.

Description

525298 V. Description of the invention (1) ---, Background of the invention: (1) The scope of the invention The structure of the flash memory array (f 1 ashmem 〇ryarray) and its manufacturing method from the 14th to the 14th of March, especially the high density It is related to the structure of a high-performance stack-gate flash memory array and its manufacturing method. (2) Description of conventional skills Flash memory elements can be divided into two types: stack gate type (stack_gate) φ structure and split gate type (spl i t ~ gate) structure. The flash memory cell of the stacked gate structure is an element composed of an transistor, and the gate length can be defined by the minimum line width of the technology. The flash memory cell of the gated structure is composed of a The structure of a stack gate and a selection gate is generally composed of a total gate length of approximately .5 times the minimum line width. Therefore, it is regarded as an element composed of i · 5 transistors. Therefore, stacked gate flash memory elements are all used in high-density flash memory systems. A typical stacked-gate flash memory device is shown in Figure 1. The structure in Figure 1A uses channel hot electron injection method ^^ ㈣ ^ hot-electron in jection) to pass channel hot electrons across the thin gate oxide layer. 〇1 Energy barrier injection_ to the floating gate 10 2 'to execute the program or write (pr 0 gramm 丨 ng); Then, the electrons stored in the floating gate 10 2 are fuller-Nordham The penetration method (Fowler-Nordheim tunneling) penetrates through the thin gate oxide layer 101 to the double-diffused source regions 105a and 107a.

525298 V. Description of the invention (2) The action of scrubbing (er a s i n g). The formation of the dual diffusion source region is mainly to provide a large overlap area between the floating gate and the source diffusion interval to reduce the time required for scrubbing. At the same time, the source is connected to a positive voltage for scrubbing action. -t 〇-B andtu η ne 1 ing) effect. However, when the gate length is shortened, the structure of the dual diffusion source is prone to element punch-through effect during the write operation of channel hot electron injection, thus becoming a fatal obstacle to the miniaturization of the element. In addition, the write efficiency of channel hot electron injection is low, and most of the channel current is wasted. For a limited load charge pump (c h a r g e p u m p) circuit, a high-density memory system will require a longer write time. The stacked gate structure shown in FIG. 1B has a symmetrical source / drain diffusion region 107a, and its operation method can be divided into two types. The first method is to perform electron scrubbing by passing electrons stored in the floating gate 102 through the thin gate oxide layer 101 in the channel region to the semiconductor substrate 100 using the Fuller-Nordheim penetration method. ; And the writing operation is still performed by channel hot electron injection. In such writing and scrubbing operations, the junction depth of the source / drain diffusion region can be reduced, but its dopant concentration is higher, and the device's anti-pass effect can be reduced, but it is still the main bottleneck of miniaturization. Another operation method is to perform the scrubbing action by passing electrons in the source diffusion region 1 0 7 a through the thin gate oxide layer 1 101 to the floating gate 10 2 by the Fuller-Nordheim penetration method; The electrons on the floating gate layer 102 penetrate the thin gate oxide layer 101 to the leak diffusion region 107a by the Fuller-Nordheim penetration method to perform a write operation. In this writing and scrubbing operation, the junction depth of the source / bubble diffusion region needs to be deeper, and its dopant concentration can be reduced, and the element's penetration effect is less likely to occur, but the junction depth of the source / drain diffusion region Need to follow the brakes

Page 6 525298 V. Description of the invention (3) The length is reduced and lightened, so the time for writing and scrubbing is bound to be longer. When the stacked gate type flash memory element is integrated to form a memory array, the first problem that must be considered is the isolation method of the element and the contact and connection of the end points of the element. Element isolation methods can be basically divided into silicon local oxidation method (L 0 C 0 S) and shallow groove isolation method (STI). The shallow groove isolation method occupies a smaller area of the silicon surface, which is suitable for high-density memory. Manufacturing. The contact and connection of the end points of the elements (cells) in the memory array are arranged according to the structure of the memory system and arranged in a matrix manner to achieve the highest built-in density. The architectures of flash memory arrays include N 0 R, N A N D, A N D, and D I N 0 R. Among them, NOR and NAND architectures are the most commonly used. For all architectures, a plurality of parallel isolation area lines (i s0 1 ati on-region 1 ines) and a plurality of active area lines between the isolation area lines (act ive -r eg i on 1 i ne s), and the flash memory cell is neatly fabricated on the active area line 'and the control gate layer of the flash memory cell is placed across the field-oxide (FOX) layer on the isolation area line To form a complex digital line (w 0 rd 1 ines) that is perpendicular to the complex isolation area line, and the flash memory cells on each active area line form a line (c 0 1 umn), and all use a common source / drain The diffusion regions are connected in series. Taking the NOR-type architecture as an example, the co-leakage diffusion area of the flash memory cell on each row forms a contact point and then connects to a bit line (b 11 1 1 ne) 'perpendicular to the complex digital line to form a complex Digital line; and the co-source diffusion area of the flash memory cell in each column forms a co-source line (c0mm_n_urce line) parallel to the sub-line in various possible connections. The traditional common source official line is added to remove the field oxide layer (F 0 X) on the isolation area line, and then a high-dose dopant is implanted on the common source pipeline.

Page 7 525298 V. Description of the invention (4) The semiconductor surface of the moving area and the isolation area to form a bur ied common-source lines, as shown in Figure C and Figure D, where Figure C shows A cross-sectional view of the common source line of the buried layer of the silicon partial oxidation isolation structure; Figure 1: C shows a cross-sectional view of the common source line of the buried layer of the shallow groove isolation structure. According to the figure, it can be seen that the bird's beak part 1 7 c of silicon is not easy to be implanted with uniform ions, which results in high buried resistance; however, the steep groove edge 1 0 7c of the shallow groove isolation structure is more difficult to uniform ions. Planting. It is worth noting here that implantation or doping of deep junction buried layers conflicts with the shallow source / drain diffusion regions required for the miniaturization of stacked gate flash memory devices. In addition, the stray junction capacitance and leakage between the buried source layer and the semiconductor substrate cannot be ignored. The conventional bit line is connected to the co-leakage diffusion region by using a first connection metal layer and passing a tungsten plug and a barrier metal (b a r r e r m e t a 1) layer covering the silicide. The layout of the contact hole usually needs to be larger than the minimum line width in order to obtain a good contact area of the co-leakage diffusion region. For high-density flash memory arrays, it is still a technical bottleneck to be overcome. In addition, the junction depth of the co-leakage diffusion area will become shallower with the miniaturization of stacked gate flash memory devices, and the contact between the bit line and the co-leakage diffusion area cannot be ignored. For a NAND-type architecture, each row of the active area line has a byte (b y t e) of flash memory cells added to the internal concatenation with a co-source / leak diffusion area. When the depth of the junction of the common source / diffusion diffusion zone becomes shallow, the series resistance generated by this connection method has a bad effect on high-speed reading of data and Lu also has a source selection transistor (source se 1 ecttransist 〇). The series resistance of the buried source common line at the end of r), the high density advantage of the NAND type architecture will be lost.

525298 V. Description of the invention (5) In addition, the word line is connected with stacked gate flash memory cells on each column by the control gate layer. Above or silicified polycrystalline silicon, but this control gate structure will show a higher sheet resistance as the control gate narrows, this phenomenon is called agglomeration of agglomerates (agg 1 omerati ο n) effect. A high-density memory array represents more flash memory cells connected to the word line. The stray series resistance of the word line will increase significantly, the RC delay of the word line will be more serious, and the operation speed of the flash memory will be worse. According to the above explanation, no matter what memory architecture the traditional flash memory array uses, it faces the following basic problems to be overcome: (1) High stray series resistance and stray capacitance of the buried common source / drain pipeline; (2) Shrinking and contact problems of the contact hole openings of the shallow source / drain diffusion region to the bit line; (3) The high stray series resistance of the shallow source / drain diffusion region as the internal connection of the flash memory element; (4) long word High stray series resistance of the wire; and (5) the problem of the puncture effect of miniaturized flash memory cells.

525298 V. Description of the invention The plural active zone lines have isolation wire layers on the side connected to form a self-floating sluice on the main float. A micro-wire of the dynamic alignment structure can automatically align the control metal layer under the sluice. Up and down can have a big effect. The contact area of the highly doped source is placed on this area > it is automatically determined. (6) The area line 'main float has two sides, and the dynamic alignment is based on the use of the micro layer of the gate layer. The word line and the integration are lowered on the side of the first-level structure / south change, and there is an automatic / extended expansion problem in the Ming Dynasty. The source / stacking gate is formed on each main integration and separated by the gate. On both sides, the quasi-error floating gate shadow is etched with multiple shallow floating gates and the second complex curtain is composed of a dielectric and does not stack gate-type positioning source scattered areas to avoid the leak-type cells on a semiconductor substrate for thin penetration. The extended floating gate layer above the dielectric layer is placed on the flat floating gate layer and two extended floating gate layers. The self-layered technology described above is more advantageous because it does not require an additional cover, that is, the surface that can obtain a higher coupling layer is relatively flat. The trench isolation lines are flat and shallow trench isolation perpendicular to each other. The dielectric layer is located above the gate. The control gate layer is covered by a metal or amorphous composite conductive layer, and each of the active parts of the long word line is caused by rapid annealing at high temperature: each surface field floating gate is aligned with the extended drift resistance ratio; Stacked shallow groove oxide layers are electrically integrated to form floating gates. In addition, the gate junctions are arranged on a structure, which is composed of an interlayer dielectric layer or a silicide / barrier layer, and is stray in series. Resistive silicide agglomerated flash memory cell common source / leakage diffusion / leakage landing island for contact and shallow auto-alignment diffusion source. Shallow source / leakage diffusion area and short channel length can resist the effect It can also reduce the series resistance of the internal series connection of the island-based siliconized highly doped complex or amorphous silicon cells.

Page 10 525298 The same pipeline system is located on a flat bed formed by two designated and field oxide layers. The shallow and highly doped source / diffusion diffusion zone contacts and locates the common pipeline system. The series resistance of the siliconized high common pipeline and the semi-conductive leakage can be greatly reduced. 5. Description of the invention (7) Decrease. According to the present invention, the common source / diffusion diffusion area between the common word lines is automatically used as a contact and an alignment diffusion source is formed. The common problem of the automatic positioning can be avoided. Similarly, the self-doped complex or amorphous silicon, stray capacitance between the substrates and the interface drawing number comparison description: 3 0 0 semiconductor substrate 301a thin penetrating dielectric layer 3 0 2a main floating gate layer 3 0 3 First mask dielectric layer 3 0 4a Second conductive layer 3 0 4c Automatic alignment with integrated floating gate 305a First dielectric pad layer 3 0 6 a Inter-gate dielectric layer 3 0 7 a Control gate layer 30 8a Second mask dielectric layer 3 0 9b Common leakage diffusion area 310b Third dielectric pad layer 3 1 1 a Auto-location common source pipeline 3 1 2 a Shallow highly doped common source diffusion area 301 Thin penetration dielectric Layer 3 0 2 First conductive layer 3 0 2b Main floating gate layer 30 3a First mask dielectric layer 3 0 4 b Extended floating gate layer 3 0 6 Inter-gate dielectric layer 3 0 7 Third conductive layer 3 0 8 Second mask dielectric layer 3 0 9 a Common source diffusion region 310 a Second dielectric pad layer 311 Fourth conductive layer 3 1 1 b Automatically locate common leak landing island 312b Shallow highly doped common leak diffusion region

525298 V. Description of the invention (8) 3 1 3 b Stone oxide layer 315a First barrier metal layer 317a Second barrier metal layer 3 2 0 a multiple crystal oxide layer 3 2,0 c multiple crystal oxide layer 3 1 3 a ^ The oxide layer 314a, the interlayer dielectric layer 3 1 6 a, the metal plug 318 a, the first connection metal layer 3 2 0 b, the polycrystalline oxide layer 3 2 1 b, and the contact hole.

Reference is now made to the diagrams in FIGS. 2A to 2E, wherein FIG. 2A shows a partial layout of the NOR flash memory array of the present invention; FIG. 2b shows a cross-sectional view in the direction A-A of FIG. 2a; 2c shows a cross-sectional view in the direction B-B of FIG. 2a, FIG. 1D shows a cross-sectional view in the direction C-C 'of FIG. 2a; and FIG. 2E shows a cross-section view in the direction D-D of FIG. 1A. FIG. 2 a shows that a plurality of shallow groove isolation lines (S T I 1 ine) are formed in parallel on the semiconductor substrate 300, and there are a plurality of active-region lines between the isolation region lines. Each active area line has a bit line (bi t 1 i ne; BL) 3 1 8a straddling it, and borrows a second barrier metal (barrier metal) layer 317a, metal piUg 316a, first A barrier metal layer 315a and a seif-registered drain landing island 3llb are connected to the leakage diffusion regions 3 1 2 b and 3 0 9 b of the stacked gate flash memory cell, as shown in Fig. 2b. Show. There is an arrangement of complex digital lines (wo rd 1 ine; WL) perpendicular to the direction of the complex isolation lines. Each word line is composed of a control gate line 3 0 7 a, and a plurality of automatic alignment under the control gate line 3 0 7 a The self-aligned integrated floating-gate layer 304c is shown in FIG. 2E. Plural automatic positioning

Page 12 525298 V. Description of the invention (9) A homologous pipeline (self-reglstered CDmmon_source bus Une; CSBL) 31 la is composed of a silicided, highly doped fourth conductive layer 31 la and is placed in a common source diffusion region 31 2a and the field oxide layer (Fox) formed on the flat bed surface, and is between the second dielectric pad layer 31〇a (Figure 2B), as shown in Figure 2C. The automatic positioning of the landing island 31 lb is composed of a siliconized highly doped second conductive layer 311b, and is placed on two second dielectric pads 31 ° (Figure 2B) and two third dielectric pads. Inside the contact hole above the common leakage area 3 1 2b surrounded by the layer 31Ob (Figure 20). The automatic positioning of the common source pipeline is also used as an automatic alignment diffusion source (diffusi0ns 〇urce) for the preparation of miscellaneous shells to form a shallow erbium-doped source diffusion region 3 1 2 a; the automatic positioning of the landing island 3 丨 b also As a highly doped bi-directional alignment diffusion source, a shallow highly doped drain diffusion region 3 is formed. First, look at the cross-sectional view shown in Figure 2B. Stacked gate flash memory cells are serially connected to the active area line with a common source / diffusion area. Ask ㊁quick = memory cell contains a second mask dielectric layer from top to bottom; the upper layer of the electric layer 307a, the gate dielectric (intergate dieUctric), the first conductive layer 302a and thin A through dielectric (thln tunneHng junction 1i2 :) layer is provided with 3: U ′ and is on a semiconductor substrate at 3 °. In the stacked gate type, +, ~ dielectric spacer 31〇a penetrates the dielectric layer 301a with a front edge. The second mask dielectric layer 308a can be a two-silicon layer, a silicon gas-nitrogen (si 丨 ic〇n_〇xyni) layer, or a silicon nitride layer from the two-silicon composite dielectric layer, completely depending on the control gate. The first and second control gate layers 307a of the third conductive layer of the layer are composed of doped polycrystalline stone, and all of them are made of silicon nitride. If the control gate layer is composed of a composite conductive layer of silicon 〃 禝 日 B silicon, the second mask dielectric

Page 13 525298 V. Description of the invention (ίο) The layer 3 0 8 a is preferably a silicon oxygen nitrogen layer. The control gate layer 3 〇7 作 is also used ~ The series resistance generated by doped polycrystalline silicon is too large and not too high for two-word flash memory arrays; if the control gate layer 307a is silicified ^) Dashi Xi's composite conductive layer Under the rapid annealing at high temperature, the silicide agglomeration effect will be generated between the broken silicon and the silicon, which will lead to the high control layer of the moon and the moon. 3 0 7 a is based on stone yam / barrier gold ^ _ non Crystalline composite conductive layer or metal / barrier metal / doped silicon composite conductive layer structure, wherein the barrier metal layer is used to describe the reaction between high melting point metal and doped polycrystalline or amorphous silicon. As a result, high conductivity of tungsten or high melting point metals. The barrier metal layer is a refractory metal-nitride layer] (20iN) or tantalum nitride (TaN), etc .; the metal layer is a high point = such as tungsten; the second mask dielectric layer 3 0 8a uses a nitride stone / two-layer structure or silicon oxynitride. The inter-gate dielectric layer 3 0 6 a is a combination of dioxyl fossil / silicon dioxide (0N0) or silicon nitride / silicon dioxide; the first conductive layer 3 0 2 a is made of doped amorphous silicon Or doped with polycrystalline spar / special teeth through dielectric layer 301 a series of thermal ~ oxide nitrided thermal-oxide; second and electrical cushion layer 3 1 0 a, 3 1 0 b is composed of silicon nitride. Now referring to the common source diffusion regions shown in FIG. 2B and FIG. 2C at the same time, the common source pipeline is positioned, wherein the source diffusion region 3 0 9 a is doped with the opposite dopant type of the gate structure semiconductor substrate 3 0 0 Quality, and can be planted with barrier layers of different structures (not shown). The first type is a conductive layer 3 0 2b and a thin penetrating oxide layer 301a placed therebelow; the second line is to pick up the amount quickly # compound crystal holding mixed compound ° the present compound crystal or amorphous tungsten Change the refracted titanium nitride layer used by Shi Xi, the silicon hair-generating / air-dielectric layer & the second line of the hot stomach and the automatic implantation and crossover

Page 14

525298 V. Description of the invention (11) Thin penetrating oxide layer 3 0 1 a. The implanted dopant can be phosphorus or arsenic ions, and can be implanted separately or simultaneously from the diffusion diffusion zone to form an asymmetric or symmetrical source / release diffusion zone, depending on the operation of the flash memory cells. If the source and vent diffuse areas are planted separately, the source diffuse area 309a can be planted using the non-rigid mask PR3 of the flattened bed of the common source pipeline, without the need for an additional mask photoresist step. Therefore, the source / bubble diffusion regions 3 0 9 a and 3 0 9 b in Fig. 2B are only schematic diagrams and not actual dopant distributions. The actual dopant distributions are related to the operation of the cell and will be explained later. The shallow source / diffusion diffusion areas 3 1 2 a and 3 1 2 b are both formed by automatically locating the common source pipeline 3 1 1 a and the automatic locating leakage landing island 3 1 1 b as the impurity automatic alignment diffusion source. FIG. 2C shows that the common source line 31 la is automatically positioned on the flat bed formed by the source diffusion region 312 a and the etched field oxide (FOX), and a highly conductive silicide layer is formed by auto-aligned silicidation 3 1 3 a. It can be clearly seen from FIG. 2C that the common source pipeline of the present invention not only has low pipeline resistance, but also the stray capacitance of the pipeline to the semiconductor substrate 300 is greatly reduced, and the leakage current at the interface of the pipeline is also greatly reduced. cut back. In addition, the present invention uses the remaining first conductive layer 3 2b to protect the semiconductor surface of the active region, so that the etching of the planarized bed surface does not affect the integrity of the semiconductor surface and the side of the isolation region. Reference is now made to the cross-sectional views of the self-locating shared venting landing island shown in FIG. 2B and FIG. 2D at the same time, where the auto-locating common venting landing island 3 1 1 b is a second dielectric cushion layer formed by a stacked gate structure Between 310a and the third dielectric pad layer 3 1 0 b on the side of the field oxide layer (FOX), the silicide layer 313b is formed by automatic alignment silicidation. The planarized interlayer dielectric layer 3 1 4a covers the entire structure and forms a self-locating island

Page 15 525298 V. Description of the invention (12)-Self-aligned contact (SAC) hole 321b, then # Add the hole to the thin first barrier metal 315a and tungsten inspection 316a, repeat again The barrier metal layer 3 1 7 and the first connection metal layer 3 丨 8. Then, using the technique of photoresist, the first connection metal layers 3 丨 8 and 8 3 1 7 are etched to form a plurality of bit openings perpendicular to the word line to the metal layer -D ^ ^ ^ «auto-alignment diffusion Source to form shallow ancient A, but as a dopant for a good bit line connection; the second scattered area 312b, and the integrity of the touch ...…, the stack of idle contact contacts and pads of the present invention The height of the automatic fixed landing island can be reduced by the size of the opposite 32 lb, and then the contact hole surface diagram under j is shown, which shows the cross-section structure in the direction of the hairline = word line. As shown in Figure IIE, the preparation of the floating gate layer 3 0 4c of the pollution gate layer 3 4c includes a main frame, i M sf element, and two automatic alignment on the integrated drift layer. Two extended floating gates; ^ IS 〇2a and two separate extended floating gate layers 30, ^ ^ on the oxide layer adjacent to the field to shrink, to greatly enhance the automatic use of cushion technology to add, while making accumulation in Inter-gate dielectrics> The coupling ratio of 3Qf ^ ice fouling layer 304c is a relatively flat surface, so that the control layer Wa is obtained from the control layer of 士: 士, which is the present invention. = Length of the lithograph surname engraved. This value does not require an additional mask photoresistive step: align the integrated floating interlayer 304. The above explanation is directed to the NO RR type field array, however, the present invention discloses: = The key technology of the array of flash memory arrays can also be applied to other 525298 V. Description of the invention (13) architecture To manufacture high-density and high-performance stacked gate flash memory arrays. The key technologies and features of the stacked gate flash memory array of the present invention are summarized as follows: (a) The flat shallow groove isolation structure of the present invention has automatic alignment of the integrated floating gate layer, which can provide control. The flattened surface of the gate layer facilitates the lithographic etching of a plurality of narrow gate lengths, and provides a ratio of floating gates with a large stack of gated cell elements without the need for an additional mask photoresist step; (b) the present invention The control gate of the stacked gate structure is composed of a metal or silicide / barrier metal / doped complex or amorphous silicon composite conductive layer, and the upper, lower and both sides are covered by a tight dielectric layer. However, the silicide agglomeration effect does not occur under high temperature annealing, so the nature of the highly conductive metal or silicide can be unchanged, and the series resistance of the control gate layer as the word line can be greatly reduced, making the signal delay time of the long word line variable. Short; (c) The self-locating common source / drain line of the present invention is composed of a silicided highly doped complex or amorphous silicon, and is placed on a flattened bed formed by a source / drain diffusion region and a field oxide layer. On the surface, the stray series resistance of the common pipeline can be Significantly reduced, and the stray capacitance between the common pipeline to the semiconductor substrate and the leakage of the interface can also be greatly reduced. Doping high instead of chemical zone fragmentation is caused by the expansion of the system, the ground is shallow, the source is leaked, the source is raised but the position is not fixed ’, and it is turned into a self-organized crystal. The crystal is not} or d C is aa complex.

Page 17 525298 V. Description of the invention (14) Quality automatic alignment of the diffusion source, and as a cushioning buffer for the connection between the bit line and the shallow leakage diffusion area to improve the integrity of the contact and reduce the contact opening At the same time, the size of the contact opening can be reduced by automatically aligning the contact structure. In addition, the automatic positioning of the source / discharge landing island can also reduce the series resistance inside the cascaded cell; and (e) the formation of the stack gate flash memory cell and the source and the leakage diffusion region can be formed without adding a mask photoresist step Next, a symmetrical or asymmetric dopant distribution is formed by manufacturing the planarized common pipeline. Reference is now made to the diagrams in FIGS. 3A to 3I, which disclose the process steps and cross-sectional views of a planarized shallow groove isolation structure with a plurality of automatically aligned integrated floating gate layers. FIG. 3A shows that a thin penetrating dielectric layer 301, a first conductive layer 302, and a first mask dielectric layer 303 are sequentially formed on the semiconductor substrate 300, and the first mask dielectric layer 303 is formed. A photoresist PR1 is coated thereon and patterned to define a plurality of parallel active area lines (below PR 1) and a plurality of isolation lines (between PR1) parallel to each other. The semiconductor substrate 3 0 0 can be a p-well or a P-type semiconductor substrate to make an n-channel memory element; the semiconductor substrate 3 0 0 can also be an n-well or an n-type semiconductor substrate to make P-channel memory element. Subsequent illustrations are mainly made of η-channel memory elements, and ρ-channel memory elements can also be manufactured by changing the dopant morphology. The thin penetrating dielectric layer 3 0 1 is composed of thermal silicon oxide or nitrided thermal silicon oxide; the first conductive layer 3 0 2 is composed of polycrystalline silicon or amorphous silicon; the first mask dielectric layer 3 The 0 3 system is composed of silicon nitride.

Page 18 525298 V. Description of the invention (15) Figure 3B shows anisotropic ground (anis 〇tr 〇pica 1 1 y) | The first mask dielectric layer 303 outside the worm-etched mask photoresist PR1, the first A conductive layer 302 and a thin penetrating dielectric layer 301 ′ form a plurality of shallow trenches in the semiconductor substrate 300, and then the mask photoresist PR 1 is removed. Then, the structure of the plurality of shallow grooves shown in β in FIG. 3 is filled with a planarized (P 1 a n a r z d) field oxide layer (F 0 X), as shown in FIG. 2C. The structure shown in FIG. 3c is a structure in which a thick silicon dioxide layer is first deposited on the structure of FIG. 3B. The chemical-mechanical polishing (chemical-me < flattening, and the first stop (polishing stop). Here is the value The structure shown in FIG. 3C can be formed with pre-oxidation, and a thin oxide layer can be formed on the first conductive layer to eliminate shallow grooves, and then a planarized oxide is formed. The planarized oxide shown in FIG. 3C is not etched. Before the shallow groove, firstly, the side of the first mask dielectric layer 303a and the layer 3 0 a behind the mask is formed into a thin dioxygen conductor substrate 300 to form a shallow groove surface to form a thin oxide layer, and then thin Part of the silicon dioxide underlayer and the thin oxide field oxide layer. The first channel width of the active region; the second method without losing the channel width of the active region, using the etch back method or 'hanical polishing; CMP) method The dielectric layer 3 0 3 a is used as a polishing stop layer. There are two other methods. The first method is to use the side and shallow grooves of the structure 3 〇 2a in FIG. 3B. The surface of the surface of the semiconductor layer is formed by the helium layer. A portion of the layer. The second method is to remove the photoresist PR1, and then etch the first conductive layer 302a and the thin penetrating dielectric pad layer, and then anisotropically engrav the half, and then oxidize the semiconductor surface of the shallow groove to form a planarization. The field oxide layer at this time is regarded as the planarization method shown in FIG. 3C, which will be slightly lost due to oxidation, mainly due to the formation of the thin dioxide layer.

525298 V. Description of the invention (16) Figure 3D shows the groove of the planarized field oxide layer of Figure 3C after the thickness of the first mask dielectric layer is slightly larger than the thickness of the first mask dielectric layer 3 0 3 a. The backfill planarizes the second conductive layer 304. The planarized second conductive layer 304 is filled with the second conductive layer 304 in the etched-back recess, and then flattened by the CMP method, and the first mask dielectric layer 303a is used as a polishing stop layer. Then etch back the planarized second conductive layer 304 to a depth approximately equal to the thickness of the first mask dielectric layer 303a, so as to obtain the planarization of the surfaces of the first conductive layer 302a and the second conductive layer 304a, as shown in FIG. 3E. Show. It is worth mentioning here that the depth of the etch-back planarized second conductive layer 304 can also be smaller than the thickness of the first mask dielectric layer 3 0 3 a, but the first conductive layer 3 0 2 a and the second conductive layer The surface of layer 3 0 4 a forms a stepped uneven surface, which is not good for subsequent lithographic etching stack gates, but the coupling is relatively large. Figure 3F shows two of the first mask dielectric layer 3 0 3 a A first dielectric rhenium layer 305a is formed on each side. The first dielectric pad layer 305a is formed by first depositing a good covering dielectric layer 305 in the structure of FIG. 3E, and then anisotropically etching back the thickness of the covering dielectric layer 305. The first dielectric pad layer 3 0 5 a is composed of silicon nitride. Next, the first mask dielectric layer 3 0 3 a and the first dielectric pad layer 3 5 5 a are used as hard etching masks, and the second conductive layer 3 0 4a between the first dielectric pad layer 3 0 5 a is etched. , As shown in Figure IIIG. Then, the first mask dielectric layer 3 0a and the first dielectric pad layer 305a are removed, as shown in Fig. 3 (a). The removal method includes high-temperature phosphoric acid cleaning or non-isotropic dry etching. It is worth mentioning here that the first conductive layer 3 0 2 a and the two second conductive layers 3 0 4 b form an automatic alignment integrated floating gate layer 3 0 4 c. FIG. 3I shows the formation of an inter-gate dielectric layer 3 0 6 on the structure of FIG.

Page 20 525298 V. Description of the invention (17) The rear implantation and the semiconductor substrate 3 0 0 push the opposite amount of the impurity type to replace the impurities in the automatic alignment integrated floating gate 3 0 4c (not shown), A third conductive layer 3 07 is then deposited on the inter-gate dielectric layer 3 06. Inter-gate dielectric layer 3 0 6 series silicon dioxide / silicon nitride / silicon dioxide (ONO) composite dielectric layer or silicon nitride / silicon dioxide composite dielectric layer. The third conductive layer 307 is a metal / barrier metal / doped complex or amorphous silicon composite conductive layer or a silicide / barrier metal / doped complex or amorphous composite conductive layer, wherein the barrier metal is a refractive metal Refractory metal-nitride, such as titanium nitride (T i N) or tantalum nitride (TaN); metal based high melting point metal, such as tungsten; silicide, high melting point silicide, such as tungsten silicide (WS i 2) ◦ It is worth mentioning here that the barrier metal layer is used to prevent the silicide agglomeration effect formed by the reaction between the metal layer / silicide layer and the doped polycrystalline or amorphous silicon, thereby avoiding a substantial increase in metal Sheet / silicide sheet resistance; doped polycrystalline or amorphous silicon system implants a high-dose dopant opposite to the semiconductor substrate 3 0 0 dopant across the barrier metal layer, and acts as an inter-gate dielectric layer 3 0 6 Buffer zone with barrier metal layer. Reference is now made to the diagrams in FIGS. 4A to 4G, which show a method of manufacturing a plurality of cells and an array thereof, and a sectional view thereof. FIG. 4A shows that a second mask dielectric layer 308 is formed on the structure of FIG. 3I, and a mask photoresist PR2 is coated on the second mask dielectric layer and is formed to define that the plurality of isolation lines are mutually Vertical complex digital lines (under PR 2). The second mask dielectric layer 308 is a silicon oxide nitrogen layer or a compound dielectric layer of nitrogen fossil / titanium dioxide. Fig. 4B (a) shows the structure of the anisotropic ground engraved figure 4A. The second mask dielectric layer 3 0 8, the third conductive layer 3 7, and the gate between the mask photoresist PR 2 Introduce

Page 21 525298 V. Description of the invention (18) Automatic alignment integration of the electric layer 3 0 6 and the thickness equal to the extended floating gate 3 0 4 b The floating gate layer 3 0 4 c is etched. Figure 4B (b) shows the cross-section of the common source / drain line outside the gate (directions B-B 'and C-C' in Figure 2A), where the floating layer above the field oxide layer (FOX) 3 0 4b are all etched. Then, dopants of opposite types to the semiconductor substrate 300 dopant are implanted in an automatic alignment manner to form symmetrical source / drain diffusion regions 3 0 9 a and 3 9 9 b. The implanted dopant can be arsenic or phosphorus, and the implanted dopant can be a high or medium dose, depending on the cell writing and scrubbing operations. FIG. 4C (a) shows that the formed mask photoresist PR3 is placed on the drain diffusion region line (DL) and a part of the second mask dielectric layer 3 0 a to expose the common source line (B-B '), And then the field oxide layer (FOX) on the common source line is etched, and the thickness of the etching is approximately equal to the thickness of the residual floating gate layer 3 2 b, as shown in FIG. 4C (b). The diffusion line (DL) is covered by the mask photoresist PR3, and the field oxide (FOX) is not etched, as shown in Figure 4C (c). It is worth mentioning here that with the structure of the mask photoresist, dopants can be implanted in this step to form an asymmetric source / drain diffusion region. For example, the dopants in the middle dose are implanted to form a deeper source diffusion region, and then the photoresist PR3 is removed, and then the high-dose dopants are implanted to form a shallow highly doped source / drain diffusion region, followed by rapid thermal treatment. annealing. The impurity implanted in the deeper source diffusion region can be phosphorus, and the impurity implanted in the shallower highly doped source / bleed diffusion region can be arsenic. FIG. 4D (a) shows that the residual floating gate layer 3 2 b on the source / drain diffusion line is removed by anisotropic etching. Figure 4D (b) shows that the common source line (B-B ') shows a flat surface; Figure 4D (c) shows that the diffusion diffusion line (C-C') shows a step-like structure, in which the field oxide layer ( F 0X) has a thinner surface than the dielectric

Page 22 525298 V. Description of the invention (19) The surface of 3 0 1 a is high. FIG. 4E (a) shows that the second dielectric pad layer 3 1 0 a is formed on both sides of the gate structure of FIG. 4 D (a), and is placed on top of the thin penetrating dielectric layer 3 0 1 a. Hydrofluoric acid (HF) bubble immersion removes a thin penetrating dielectric layer 3 1 0 a other than the second dielectric pad layer 3 1 0 a. The surface of the common source line (B-B ') also remains flat, as shown in Figure 4E (b);: ¾ diffusion line (C-C') forms the structure shown in Figure 4E (c), The third dielectric pad layer 3 1 0 b is also formed on both sides of the field oxide layer and placed on top of the thin penetrating dielectric layer 301 a. However, because the thin penetrating dielectric layer is removed, the field oxide layer (FOX) is also etched to show a slight depression. The second and third dielectric pads 3 1 0 a and 3 1 0 b are composed of silicon nitride, and the formation method is the same as that of the first dielectric pad. Next, a thick fourth conductive layer 3 1 1 is deposited on the structure of FIG. 4A, and then the thick fourth conductive layer 3 1 1 is polished by a CMP method (not shown), and then the fourth conductive layer is etched back and planarized. , As shown in Figure 4F (a). The fourth conductive layer is composed of polycrystalline silicon or amorphous silicon. It is worth mentioning here that the depth of the etch-back planarized fourth conductive layer is about the top of the third dielectric pad 3 1 0 b. FIG. 4F (a) shows that a thin polycrystalline oxide layer 3 2 0 a, 3 2 0 b is grown on the surface of the fourth conductive layer 3 1 1 a, 3 1 1 b after the etch-back, and the oxidation may remain in the field oxide layer. (FOX) the remaining fourth conductive layer. Next, a high-dose dopant of the opposite type to that of the semiconductor substrate is implanted across the thin polycrystalline oxide layers 3 2 0 a and 3 2 0 b in the fourth conductive layer 3 1 1 a and 3 1 1 b. The 3 1 2a, 3 1 2b dopant auto-aligned diffusion source is used as the shallow highly doped source / drain diffusion region. F (b) in FIG. 4 is a cross-sectional view showing the direction of the common source line (B-B ′), in which the fourth conductive layer 3 1 1 a after the etch-back is used as an automatic positioning common source pipeline, and grows thereon.

Page 23 525298 V. Description of the invention (20) The thin multicrystalline oxide layers 3 2 0 a and 3 2 0 b are sacrificial oxide layers implanted as ions (s a c r i f i c i a 1 — 0 x i d e). FIG. 4 F (c) is a cross-sectional view showing the leakage diffusion line (c — c,), in which the fourth conductive layer 3 1 1 a, 3 1 1 b after the etch-back is placed on the two first dielectric pad layers 31oa and two third dielectric pads 310b on the bubble and scattered area 3 009b as an automatic positioning of the landing island, and a thin polycrystalline oxide layer 3 2 0 b is grown on it as an ion cloth Planted sacrificial oxide layer. Figure 4G (a) shows that the structure of Figure 4F (a) is subjected to rapid thermal annealing to form shallow highly doped source / drain diffusion regions 312a, 312b 'in the source / wave diffusion regions 3 0a, 3 0b. Then, the thin polycrystalline oxide layers 32 0a, 320b, and 3 2 0 C are removed, and then a self-aligned silicidation process is performed.

1 complex, the removal of the oxide layers 32 0a, 32 0b, and 3 2 0c can be made by diluting the gas I bubble β or anisotropic dry etching. The automatic alignment silicidation process is first to deposit the refracted metal M ′, and then quickly in the environment of nitrogen or argon: = occupying the automatic positioning Maodao Island and the automatic positioning common source tube will == dagger layer 313a, 313b, the rest Unreacted in seconds 4 = Pre / Fenji added to remove. Refractive metal system uses titanium (T = (=), indium (M.), nickel (Ni), platinum (Pt) or tungsten (w), etc.), '〇 to b) not automatically locate the common source pipeline 3Ua's spines Back to 313a ', the surface of the source diffusion region 309a forms a shallow highly doped material. The common source line 3 1 1 a is located at the shallow highly doped source sound 2: 3 1 2a. On the flat bed formed by the field oxide layer (Fox), the bean has two and two regions 31 2a and is much shorter than the traditional buried structure. Therefore, the length of the substantially reduced length will be the same, and the common source pipeline 311ay is automatically positioned. The resistance of W; the stray capacitance and interface power are also greatly reduced. Figure 4 G (0 shows automatic

Page 24 525298 V. Description of the invention (21)

The surface of the positioning landing island 3 1 1 b has been converted into silicide 3 1 3 b, while the surface of the leak diffusion region 3 9b forms a shallow highly doped leak diffusion region 31 2b. Automatically positioning Mao landing island 3 1 1 b not only solves the contact problem of the shallow diffusion zone, but also provides a heightened contact point to reduce the depth of the bit line connection. The size of the contact hole 3 2 1 b of the bit line is also variable. Smaller, thereby increasing the density of the memory array. It is worth mentioning here that 'automatically locate the common source pipeline and automatically locate the landing island can use the existing auto-alignment silicidation technology to convert all of them into silicide (not shown). The contact resistance to the source diffusion region can be further reduced, and the contact resistance of the auto-locating steam landing island to the leakage diffusion region can also be reduced. In addition, for the “⑽” type structure, the cell elements are connected in series by a common source / diffusion diffusion zone, and the fully silicified automatic positioning of the landing island will greatly reduce the cell resistance in series. Then on the structure of Figure 4G First form a planar interlayer dielectric (ILD) 314a, and then use a mask

The photoresist step (not shown) excavates the contact opening 3 2 1 b with the automatic positioning of the landing island, and then sequentially deposits a thin first barrier metal layer 3 1 5 and a thick plug metal layer 3 1 6, and uses c MP or etch-back method to planarize to form Figure 2B

The first barrier metal layer 3153 and the metal plug (11 ^ 7 & 1011 ^) 3163 are shown. Then, a thin second barrier metal layer 3 1 7 and a first connection metal layer 3 1 8 ′ are deposited, and then another first photoresist step (not shown) is used to selectively etch the first connection metal layer. 3 1 8 and the third barrier metal layer 3 1 7 to form a plurality of bit lines 3 1 8 a perpendicular to the word line, as shown in FIG. 2B. Fig. 2C is a cross-sectional view showing a common source pipeline direction (BB,); Fig. 2D is a cross-sectional view showing a leak diffusion line direction (CC); Fig. 2E is a cross-sectional view showing a word line direction (D-D ') 525298 V. Description of Invention (22). The interlayer dielectric layer 3 1 4 a is composed of silicon dioxide or doped silicon dioxide, such as pure glass (g 1 ass), phosphorous glass (P-g 1 ass), or boron filled glass (BP -g 1 ass); the first and second barrier metal layers are composed of refracted metal nitrides, such as nitride (T i N) or nitride group (T a N); the metal detector is composed of cranes or aluminum; A connection metal layer is composed of aluminum, aluminum silicon copper alloy or copper. It is worth noting here that FIGS. 2A to 2E are examples of stacked-gate flash memory arrays of the NOR type. Other well-known stacked-gate flash memory array architectures can use the key technology of the present invention. It is pre-manufactured to show the advantages of the present invention. In addition, the stacked gate flash cells shown in Figs. 2A to 2E have symmetrical source / drain diffusion regions. For the stacked gated cells in common asymmetric source / drain diffusion regions, It can also be manufactured without additional mask photoresist steps. Although the present invention is particularly illustrated and described with reference to the attached examples or connotations, it is only a statement and not a limitation. Furthermore, the present invention is not limited to the listed details. For those skilled in the art, it can be understood that changes of various shapes or details can be made without departing from the true spirit and scope of the present invention. References US Patent 4, 698, 787 10/1987 Mukherjee

Page 26 525298 V. Description of the invention (23) 5, 918, 141 6/1999 Merrill 6, 1 0 3, 5 74 8/2000 Iwasak i 6, 21 1,020 B1 4/2001 Tripsas et a 1. 6, 215, 145 B1 4/2001 Noble 6, 2 7 7, 6 9 3 B1 8/2001 Chen Other publications S. Ar i tome, 丨 'Advanced Flash Memory Technology and Trends for File Storage App 1 i cal: i on n , IEDM (2000), pp. 763 ~ 766. JD Choi eta 1., HA 0.15 // m NAND Flash Technology With 0.11 // m2 Cell Size for 1Gbit Flash

Memory ", IEDM (2000), pp.767-770.

Page 525298 Brief Description of Drawings Figures 1A to 1D show the structure and cross-sectional views of the prior art, of which Figure 1A shows a cross-sectional view of a stacked gate flash memory device with asymmetric source / drain diffusion regions Figure 1B is a cross-sectional view of a stacked gate flash memory device with a symmetrical source / diffusion diffusion region; Figure 1C is a cross-sectional view showing a buried common source pipeline across a trench of local oxidation isolation of silicon; and Fig. 1D is a cross-sectional view showing a buried common source pipeline crossing a trench isolated by a shallow groove; Figs. 2A to 2E are diagrams showing a structure and a cross-sectional view of a stacked gate flash memory array according to the present invention. Figure 2A is a top view of the NOR-type architecture of the present invention; Figure 2B is a cross-sectional view of the stack gate flash memory cell of the present invention in the channel length direction (AA 'direction of Figure 2A); FIG. 2C is a cross-sectional view showing the direction of the common source pipeline (CSBL) of the present invention (direction BB ′ in FIG. 2A); FIG. C-C ') cross-sectional view; and FIG. 2E shows the zigzag direction of the present invention ( 2A, D-D 'direction); Figures 3A to 3I show the process steps and cross-sectional views of the shallow groove isolation structure of the present invention with an auto-aligned integrated floating gate layer; and Figure 4A, Figure 4B (a)-(b), Figure 4C (a)-(c), Figure 4D (a)-(c), Figure 4E (a)-(c), Figure 4 F (a)-(c) and Figure 4G (a)-(c) show the process steps of the stacked gate flash memory array with automatic positioning of the common source pipeline and automatic positioning of the landing island in the present invention and Sectional view.

Page 28

Claims (1)

52 1. Overlay this method to have at least a plurality of methods, each oxide of the conductive layer in one of the active area lines is formed, and the second conductive conductive layer is formed on a word line, and the number of conductive layered fields between the gates is Mainly, the plurality is formed through the dielectric, the plurality is called a common non-parallel, and the thin through-bars each have two stacks of gate-type flash memory arrays on a semiconductor substrate. Each of the parallel shallow and shallow groove active area lines has A main dielectric first extension groove isolation line and a plurality of flat isolation structures therebetween are formed on the semiconductor substrate and its plurality of parallel shallow groove isolation lines. A second conductive layer is formed in a planarized field layer. The shallow shape is electrically connected in series with the first parallel automatic layer cloth parallel to the dielectric thick oxide layer in parallel to the source / isotropic main gas connection to form a gate groove to isolate the complex sequence. The insect layer and the degree, the conductive layer on the physical layer is aligned with the active area of the square plant and the semi-active area diffusely to the first to form an inter-dielectric ionization structure in parallel. The complex number described in the above section still crosses the semi-conductor's baseline on the conductor, and the worm guides the electric automatic layer. The worm is covered with a complex extension of the quasi-product. The worm is engraved with the conductor layer of the complex plate. The third conductive isolation screen is aligned with the two, and the mediator is flat and the second, and the doped substrate line and the mutual electric layer are floating. The conductive lines are electrically conductive in the left-quality type, and adjacent to the extension. The first floating gate layer; the layer and the second screen are vertical, and the outer layer of the gate line has a plurality of leads and a conducting phase in a straight shape and a third lead to the extension and is placed in the parallel parallel electric layer. ; The electrical layer and the reverse doped with a plurality of parallel electrical layers, extending a second complex plane, and the thin penetrating impurities outside the complex line to the complex plane of the first pair of common pipelines Page 29 525298 6. Apply for a patent application Field oxide layer to a depth approximately equal to the thickness of the plurality of retained first conductive layers, and then anisotropically remove the plurality of retained first conductive layers in an automatic alignment manner; form a second A dielectric pad is formed on the side wall of the plurality of parallel word lines, and a third dielectric pad is formed on the side wall of the plurality of planarized field oxide layers without being removed; the plurality of parallel active layers are removed in an automatic alignment manner. The thin penetrating dielectric layer on the semiconductor substrate of the area line and simultaneously etches the plurality of planarized field oxide layers on the plurality of parallel shallow groove isolation lines to form a flat surface on each line of the designated common pipeline The surface of the bed is exposed with a plurality of common source / drain contact openings; a plurality of fourth conductive layers are placed on the plurality of flat bed surfaces as a plurality of automatically positioned common pipelines and simultaneously placed on the plurality of common source / drain contact openings as a plurality of automatic Positioning a common source / bubble landing island; implanting a high-dose dopant of the opposite type to that of the semiconductor substrate in the plurality of fourth conductive layers to form a plurality Automatic alignment of dopant diffusion sources in highly doped source / drain diffusion regions within the plurality of first symmetrical source / drain diffusion regions; and automatic alignment of silicified common automatic positioning common pipelines and the plural automatic positioning sources / bubbles landing Islands to form a plurality of self-aligned layers 2. The method described in item 1 of the scope of patent application, which further comprises forming a planarized interlayer dielectric layer on the formed structure, and then Page 30 525298 VI. A plurality of siliconized automatic positioning common source / discharge landing islands specified in the scope of patent application form a plurality of automatic alignment contact holes, wherein each of the plurality of said automatic alignment contact holes fills the first obstacle A planarized metal plug surrounded by metal; sequentially forming a second barrier metal layer and a first connection metal layer on the planarized interlayer dielectric layer, a plurality of planarized metal plugs, and a plurality of first barrier metal layers, and Forming and anisotropically etching the first connecting metal layer and the second barrier metal layer to form a plurality of parallel bit lines above the plurality of parallel active area lines. 3. The method according to item 1 of the scope of patent application, wherein the shallow groove isolation structure is manufactured by the following method, the method at least comprises: sequentially forming the thin penetrating dielectric layer, the first conductive layer Layer and a first mask silicon nitride layer on the semiconductor substrate to form a multilayer structure; forming the multilayer structure to define the plurality of parallel active area lines does not etch the multilayer structure and the semiconductor isotropically A substrate to form a plurality of parallel shallow grooves; oxidize the etched sidewall of the multilayer structure and the etched semiconductor surface of the plurality of parallel shallow grooves; and then deposit a thick silicon dioxide film to fill the plurality of parallel shallow grooves The gap formed by the groove is then planarized by etch back or chemical-mechanical polishing to form a thick planarized field oxide layer, and a first mask silicon nitride layer is formed. As a polishing stop layer; anisotropically etch back the complex planarized field oxide layer to a little larger than the Page 31 525298 6. The scope of the application for a patent is to use a small layer and an electrically-etched material to form lithium silicon or wall erosion to conduct flattening to the edge as dioxygen and separate nitrogen and other layers as the first spacer. Add the curtain to the layered surface pad, the slot film, the silicon layer, the flat silicon cavity, the electrocavity, the electrochemical breakup, and the shallow conduction. And the first layer, the first layer of the cover, the first degree, the first layer and the gate, the full thickness of the first layer of the circuit and the floating fill the level of the layer and the guide; The depth of the layer is used to etch the derivative on the electrical layer. The two-layer thick layer is used to conduct silicon etching. The lateralization volume is electromilled. The second layer is stretched to form a nitrogen product. The second nitrogen extended two scenes of the quasi-layer and two-machine surface. The reversion of the curtain to the number of masks on the two planes, such as the nitrogen and nitrogen masks, which are activated on both sides, is a number of tentative curtains, one is flat, and the other is not the first. The number of scenes accumulated into a grind, etc. One after the other, the shape of the screen, except for the complex mask pile or the shape of the non-form borrowing mask, every time there is more than one thought that the # quality, the first time, made back to the hard layer. 4. The method according to item 1 of the scope of patent application, wherein the shallow groove isolation structure is manufactured by a method including at least: sequentially forming the thin penetrating dielectric layer and the first conductive layer Layer, and a first mask silicon nitride layer on the semiconductor substrate to form a multilayer structure; forming the multilayer structure to define the plurality of parallel active area lines, rather than isotropically etching the multilayer structure; forming Side wall of the multi-layer structure of the silicon dioxide cushion layer after the etching and the half Page 32 525298 VI. Patent application scope Conductor substrate, and then anisotropically etch the semiconductor substrate to form a plurality of parallel shallow grooves; oxidize the semiconductor surface after the meal of the plurality of parallel shallow grooves, and then deposit Silicon dioxide film to fill the plurality of parallel shallow grooves, and then use the money back or chemical-mechanical polishing method to planarize the thick dioxide film to form a complex planarized field oxide layer, and The first mask silicon nitride layer is used as a polishing stop layer; the multiple planarization field oxide layer is anisotropically etched back to a depth slightly larger than the thickness of the first mask nitride layer; The conductive film is used to fill the gap after the etch-back, and then the thick second conductive film is planarized by etch-back or chemical-mechanical polishing to form a plurality of planarized second conductive layers, and a first mask is used. The silicon nitride layer is used as a polishing stop layer; the plurality of planarized second conductive layers are anisotropically etched back to a depth equal to or smaller than the thickness of the first mask silicon nitride layer; a first silicon nitride pad layer is formed on The first hood The side wall of the curtain silicon nitride layer and the plurality of etched back planarized second conductive layers; the first mask silicon nitride layer and the first silicon nitride pad layer are used as an etching hard mask, anisotropic Etch the etched back plurality of planarized second conductive layers to form two sides of the two extended second conductive layers above each of the remaining plurality of planarized oxide layers; and remove the first Mask a silicon nitride layer and the first silicon nitride pad layer to form the shallow groove isolation structure with a plurality of automatic alignment integrated floating gate layers 525298, page 33. Application scope of patent 5. The method as described in item 1 of the scope of patent application, wherein the thin penetrating dielectric layer is a thermal silicon oxide layer or a nitrided thermal silicon oxide layer, and the gate The dielectric layer is a silicon dioxide-silicon nitride-silicon dioxide (ONO) or silicon nitride-stone dioxide composite dielectric layer. 6. The method according to item 1 of the scope of patent application, wherein the first conductive layer, the second conductive layer, or the fourth conductive layer is composed of polycrystalline silicon or amorphous silicon. 7. The method according to item 1 of the scope of patent application, wherein the third conductive layer is composed of a metal / barrier metal / doped polycrystalline or amorphous silicon composite conductive layer, and the metal is composed of The point metal is composed of, for example, a crane, and the barrier metal is composed of a refractive metal nitride, such as nitride (TiN) or tantalum nitride (TaN). 8. The method according to item 1 of the scope of patent application, wherein the third conductive layer is composed of a silicide / barrier metal / doped polycrystalline or amorphous silicon composite conductive layer, and the silicide is composed of Refractive metal silicides, such as Shi Xihua, and the barrier metal is composed of refractive metal nitrides, such as titanium nitride (T i N) or nitride group (T a N). 9. The method according to item 1 of the scope of patent application, wherein said second dielectric pad or said third dielectric pad is composed of nitride nitride, and said first 525298 6. The scope of the patent application. The second mask dielectric layer is composed of silicon oxynitride or silicon nitride / silicon dioxide. 10. The method according to item 1 of the scope of patent application, wherein the plural number is automatically positioned. The common pipeline or the plurality of automatic localization common source / discharge landing islands is manufactured by the following method, which at least includes: depositing a thick fourth conductive film on the formed structure, Planarize the thick fourth conductive film by etch back or chemical-mechanical polishing, and use the second mask dielectric layer as a polishing stop layer to form a plurality of planarized fourth conductive layers; and etch back the plurality of planes The fourth conductive layer is formed to a level approximately equal to the top of the third dielectric pad layer. 1 1. The method according to item 1 of the scope of patent application, wherein the plurality of automatic alignment silicide layers are formed on the plurality of automatic positioning common pipelines or the plurality of automatic positioning common source / discharge landing island-based refractive metal silicides. Composition, such as Titanium Silicate (T i S i 2), Titanium Silicate (CoS i 2), Nishi Sulfur (N i S i 2), Molybdenum Silicide (MoSi2), TaSi2 (TaSi2 ), Platinum silicide (PtSi2) or tungsten silicide (WSi2), etc. 1 2. The method according to item 1 of the scope of patent application, wherein the plurality of automatic positioning common pipelines or the plurality of automatic positioning common source / discharge landing islands are formed by depositing a thick layer of refracted metal or changing automatic alignment to Shi Xi The annealing temperature or time in the chemical process is completely converted into a thick silicide layer. Page 35, 525298 6. Application for patent scope 1 3. The method as described in item 2 of the patent application scope, wherein the first barrier metal layer or the second barrier metal layer is composed of a refractive metal nitride, such as Nitride (T i N) or nitride group (T a N). 14. The method as described in item 2 of the scope of patent application, wherein the bolt metal is composed of iron or Ming, and the first connection metal layer is composed of Ming, I-Si-Cu alloy or copper . 15. A method of forming a slotted isolation line, a chemical field oxide of the main floating gate slot isolation line, wherein all of the chemical field oxides are electrically connected to form a complex gate layer as described in the complex line; forming the diffusion region, and seeding The method consists of stacking a number of parallel and flat numbering piles in each layer, including at least a few parallels. The main floating gates, which have two on the thin penetrating strip, are automatically aligned with the stack gate type. The number of lines of the fast flash line and the flash line of the row word line are parallel to one extended drift side of the main dielectric layer; the layer system and the phase-integrated flash memory are stored in a thin and complex parallel array on the semiconductor substrate in between. Each of the plurality of parallel shallow concave moving area lines has one on it, and the plurality of parallel shallow concave concave floating gate layers are formed on a plane adjacent to the two extended floating gate floating gates; 'Mu', each of which contains at least one continuous control complex stacked gate flash memory cell multiple shared source Page 36 525298 6. The scope of the patent application is based on the specified memory array structure to form a complex planarized bed surface composed of the complex shared source / drain diffusion region and the complex planarization field oxide layer on the designated common pipeline; Forming a plurality of silicified automatic positioning common pipelines on the specified plurality of flattened beds and forming a plurality of silicified automatic positioning common sources / discharge landing islands on the specified plurality of common source / discharge diffusion regions; forming a plurality of parallel bit lines It is perpendicular to the plurality of parallel word lines, wherein the plurality of parallel bit lines are automatically aligned with the contact holes through a plurality of planarized thick interlayer dielectric layers, according to the specified memory array structure and the specified The multiple silicified automatic positioning common source / discharge landing island connection 16. The method as described in item 15 of the scope of patent application, wherein the automatic alignment integrated floating gate layer is made of polycrystalline silicon or amorphous A high-dose dopant composed of silicon and implanted with a type opposite to that of the semiconductor substrate. 17. The method according to item 15 of the scope of patent application, wherein said continuous control gate layer is composed of metal / barrier metal / doped polycrystalline or amorphous silicon or petrochemical / barrier metal / doped It is composed of polycrystalline or amorphous stone, the metal is composed of thorium, the stone is composed of Shixi Chemical Crane, and the barrier metal is made of titanium nitride (TiN) or tantalum nitride (TaN) Composed of. 18. The method according to item 15 of the scope of patent application, wherein said plural automatic positioning common pipelines or said plural automatic positioning common source / discharge landings Page 37 525298 6. The scope of the patent application The island is composed of complex crystals or amorphous fragments and is implanted with a high-dose dopant that is opposite to the impurity type of the semiconductor substrate to form a plurality of shallow highly doped sources / Automatically aligning the dopant diffusion source with the leak diffusion region. 19. The method as described in item 15 of the scope of patent application, wherein the plurality of automatic positioning common pipelines or the plurality of automatic positioning common source / discharge landing islands can be added to a part or All silicides, and the silicide is composed of refracted metal silicides, such as titanium silicide (TiSi 2), Shi Xi 4 Ding Jiang Gu (CoSi 2), Shi Xi 4 D I (Dan Si 4), Shi Xi 4 D I mesh (MoSi 2), nickel silicide (NiSi2), platinum silicide (PtSi2) or tungsten silicide (WSi2), etc. 20. A method of forming a line on the isolation between the complex lines as a cell layer, thinning a flattened expansion of each of the complex number to one, and the self-transmitting dielectric planarization field forming the manufacturing method to several stacks The stack gate word line formed by the reactor plus a cell dynamic alignment layer on top of the oxide complex stack gate include: a gate flash, a plurality of flat flashes are connected, and the element is at least inclusive Above the side layer; a stack gate type flash memory array on a semiconductor substrate memorizing cells on the active area line of a plurality of parallel shallow grooves, wherein each column memory cell is controlled by a continuous control gate and the plurality of stacked gates The flash memory contains a self-aligning integrated floating gate. The floating gate is composed of a main floating gate on the side and two extended floating gates on the two flash memory cells. The specified memory array structure forms a plurality of flat beds on the specified Page 38 525298 VI. The common shared source / diffusion diffusion zone and complex planarization field oxide layer of the common pipeline in the scope of patent application; forming a complex automatic positioning common 'pipeline on the complex flat bed and forming a complex automatic positioning The common source / discharge landing island is located on the plurality of common source / discharge diffusion regions, wherein the plurality of automatically positioned common pipelines or the plurality of automatically positioned common source / discharge landing islands are arranged opposite to the doped type of the semiconductor substrate. High-dose dopants for automatic alignment of dopant diffusion sources forming a plurality of shallow high dopant sources / diffusion diffusion regions; perform an auto-alignment silicidation process and share the complex automatic positioning common pipeline and the complex automatic positioning The source / drain landing island is partially or fully converted into a complex auto-aligned silicide layer, wherein the complex auto-aligned silicide layer is composed of a refracted metal silicide; and a plurality of parallel bit lines are formed in the plurality of parallel Above the active area line, the plurality of parallel bit lines are formed by planarizing the thick interlayer dielectric layer according to the specified memory array architecture. The formed plurality of auto-aligned contact holes are connected to the designated multiple silicified auto-location common source / discharge landing island. Page 39