TW522478B - Self aligned method of forming a semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling, and a memory array made thereby - Google Patents

Abstract

A sell aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction, and an apparatus formed thereby. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that include indentations or different widths. The trenches are filled with a conducting material to form blocks of the conducting material that constitute source regions with a first portion that is disposed adjacent to but insulated from the floating gate, and a second portion that this disposed over but insulated from the floating gate.

Description

522478 A7 _____B7_ V. Description of the Invention (1) Field of the Invention The present invention relates to a self-aligning method of a semiconductor memory array that forms a floating gate memory cell of a split gate type. The invention also relates to a semiconductor memory array of the aforementioned type of floating gate memory cell. BACKGROUND OF THE INVENTION It is well known in the art to use non-electrostatic semiconductor memory cells that use floating gates to store charge thereon and the memory of such non-electrostatic memory cells that are formed in a semiconductor substrate. Body array. Typically, these floating gate memory cells have been separated gate type, or stacked gate type, or a combination thereof. One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays is the alignment of various components such as source, non-polar, control gate, and floating gate, especially in the reduction of memory cell size Time. As the design rules for the integration of semiconductor processing are reduced to minimize the lithographic appearance, the need for precise alignment becomes more important. The alignment of various components also determines the manufacturing capacity of semiconductor products. Self-alignment is well known in the art. Self-alignment refers to an action that involves one or more steps of one or more materials, so that the process automatically aligns the appearance relatively in this process step. Accordingly, the present invention uses self-alignment technology to achieve the fabrication of a semiconductor memory array of floating gate memory cell type. Two major issues are often implicated when the size of the memory cell is reduced. First, the resistance on the source line increases with smaller memory cell sizes, and a higher resistance makes the desired cell current during a read operation. Second, the paper size is suitable for Chinese National Standard (CNS) A4 specifications (210X297 mm) 4 (Please read the precautions on the back before filling this page)-Order 丨 522478 A7 B7 V. Description of the invention (2 smaller Memory cell scale results in a lower breakdown voltage VPT between the source and bit line junctions, which limits the maximum floating gate voltage Vfg that can be achieved during a program operation. Through voltage coupling from the source region, transmission A coupling oxide layer is connected between the source and the floating interrogator to reach the floating gate voltage Vfg. In a source-side injection mechanism, a high vfg (and therefore a High breakdown voltage νρτ) 〇 Invention _ The present invention solves the above problems by providing a (T-shaped) source region, in which a wider conductive upper portion reduces the resistance of the source line, while a narrower lower portion of the source line Promote smaller memory cell size. In addition to coupling the oxide through the bottom, the memory cell structure also promotes the coupling of the source voltage to the floating gate through an oxide on the upper part of the floating gate. Strengthen source Consumption efficiency between an electrode and a floating gate. The present invention is a self-aligning method for forming a semiconductor memory array, which is a floating gate memory cell, in a semiconductor substrate, and each memory cell has a floating gate. Electrode, a first terminal, a two terminal with a channel region in between, and a control gate, the method includes the following steps: a) forming a plurality of spaced-apart isolation regions on the substrate, the isolation regions are mutually Approximately parallel and extending in a first direction, there is an active region in each pair of adjacent isolation sections, each of the active regions includes a first layer of insulating material on the semiconductor substrate, and on the first layer of insulating material A first layer of conductive material: b) forming a plurality of spaced apart first channels across the active area and the isolation area. The first channels are substantially parallel to each other and substantially perpendicular to the first paper. SS Standard (CXS) A4 Specification (210X297mm) (Please read the note on the back before filling this page)-Installation,

•, I: line 522522 A7 _B7_ V. Description of the invention (3) Extending in a second direction, each of the first trenches has a side wall containing a contraction formed therein; c) a A first conductive material fills each of the first trenches to form a first block of the conductive material, and for each of the first blocks in each of the active regions: the first block includes a first block formed in the first A lower part of the trench side wall below the contraction, the lower part is disposed adjacent to and insulated from the first layer of conductive material; and the first block includes a An upper part of the reduced grid is disposed above the first layer of conductive material and is insulated therefrom; d) forming a plurality of first terminals in the substrate, wherein each of the active areas Each of the first terminals is adjacent to and electrically connected to one of the first squares of the conductive material; and 0, a plurality of second terminals are formed in the foundation ceremony, each of which is in each of the active areas The second terminals are related to the first terminals Separated. In another aspect of the invention, an electrically programmable and erasable memory device includes a substrate of a first conductivity type semiconductive material, and a first and a first of the second conductivity type substrates. Two spaced regions with a channel region in between, a first insulating layer disposed above the base, a first insulating layer disposed above the first insulating layer, and extending over a portion of the channel region and a portion of the first region An upper electrically conductive floating gate, and an electrically conductive source region disposed above the first region in the base body and electrically connected to the first region. The source region has a lower cover sheet adjacent to the buoyancy gate and its insulation. This is also a standard (CNS) Α4 specification (2ΐ〇χ297 公 爱) (Please read the back first (Notes on this item will be refilled on this page): ^ τ— 6 522478 A7 ____ B7_ V. Description of the invention (4) and an upper part which is arranged above the floating gate and insulated from it. In yet another aspect of the present invention, an electrically programmable and erasable device of an array includes: a substrate of a first conductive type semiconductor material, formed on the substrate, substantially flat to each other, and a The plurality of spaced apart isolation regions extending in the first direction have an active region in each pair of adjacent isolation intervals, and each active region includes a row of multiple pairs of memory cell cells extending in the first direction. Each memory cell pair includes a first region and a pair of second regions separated in a matrix having a second conductivity type, and a channel region is formed in the matrix between the first region and the second regions. A first insulating layer disposed above the substrate and including the channel regions, disposed above the first insulating layer and extending over a portion of one of the channel regions and a portion of the first insulating layer A pair of electrically conductive floating gates above a region, and an electrically conductive source region disposed above the first region in the base body and electrically connected to it. The source region has a lower portion disposed adjacent to and insulated from the pair of floating gates, and an upper portion disposed above and insulated from the pair of floating gates. Other objects and features of the present invention will become apparent from a review of the specification, patent application scope, and appendixes. Brief description of Zhou Shiji Figure 1A is a top circle of a semiconductor substrate used in the first step of the method of the present invention to form an isolation region; Figure 1B is a cross-sectional view taken along the line M; Figure 1C The top view of the next step in the processing of the structure of 1B 囷, in which the isolation zone is formed; the scale of the paper method is small; the national standard (CNS) A4 specification (210X297 mm) in η -------- ------------ Install ------------------ 1T --......-........ line · (Please read the notes on the back before filling in this page) 522478 A7-^ s_! Z ___ V. Description of the invention (5) Figure ID is taken along line 1-1 in Figure 1C to show the formation on the structure The horizontal loading surface of the structure of the isolation strip in 圊; ......: (Please read the precautions on the back before filling this page) Figure 1E is taken along line 1-1 in Figure 1C. To show the two types of isolation areas that can be formed in the structure: the cross-sectional view of the structure of LOCOS or shallow trenches; Figures 2 A-2N are shown in Figure 1C along the 2-2 line to sequentially display In processing the structure shown in Figure 1C, one of the floating-memory cell cells forming a separate gate type is formed. Cross-sectional view of the subsequent steps of the electromechanical memory array; FIG. 20 is a diagram showing the row and bit lines in a non-electrostatic memory array forming a floating gate unit cell of the separation gate type. Above view of the terminals connected to each other in the active area; 3A-3I® is adopted along line 2 and 2 of Figure 1C to sequentially display in the structure shown in Figure 1C of the first replacement process to form a separation gate Figure 4A-4J, which is taken along the line 2-2 of Figure 1C, is used to sequentially display the cross-sections of the steps of a non-electrically-regrettable array of floating memory cells. In the structure shown in FIG. 1C of the second replacement process, a cross-sectional view of a step of forming a non-electron-dependent memory array of a floating-gate floating-memory cell is shown in FIG. 5A and FIG. Lines 2-2 of FIG. 1C are used to sequentially display the steps of forming a non-electrolytic memory array in the structure shown in FIG. 1C to form a separate gate-type floating memory cell in the third replacement process. Cross loading surface 圊. Detailed description of the best example of bismuth description of bismuth paper to send to the national standard (®s) A4 specification (21〇χ297 public love) 522478 A7 B7 5. Description of the invention (6) Please refer to section 1A 囷, it shows that there is better Top view of a semiconductor substrate p-type and well known in the art. A first layer of insulating material 12 such as silicon dioxide (oxide) is deposited thereon as shown in FIG. 1B. The first insulating layer 12 is formed on the substrate 10 by a well-known technique such as oxidation or deposition (for example, chemical vapor deposition or CVD) to form a layer of silicon dioxide (hereinafter referred to as "oxide"). A first layer of polycrystalline silicon 14 (FG polycrystalline silicon) is deposited on the first layer of insulating material 12. The deposition and formation of the first polycrystalline silicon layer 14 on the first insulating layer 12 may be performed by a well-known procedure such as low-pressure CVD or LPCVD. A silicon nitride layer 18 (hereafter "argonide") is deposited over the polycrystalline silicon layer 14, preferably by CVD. This halide layer 18 is used during isolation formation to define the active area / of course, all the aforementioned parameters and thereafter The parameters described depend on design rules and program technology generation. The description herein is for 0.18 micron programs. However, those skilled in the art will understand that the present invention is not limited to any specific program technology generation, nor is it limited to the following description Once the first insulating layer 12, the first polycrystalline silicon layer 14, and the silicon nitride layer 18 have been formed, a suitable photoresist material 19 is applied on the silicon nitride layer 18, and a A photomask step is performed to selectively remove the photoresist material from certain areas (strip 16). Where the photoresist material 19 is removed, standard etching techniques (ie, non-isotropic etching procedures) are used as shown in Figure 1C 囷. ) To etch away silicon nitride 18, polycrystalline silicon 14, and the underlying insulating material 12 in the strip 16 formed in the Y direction or the row direction. The distance W between adjacent strips 16 can be as small as the smallest procedure used Lithography appearance. Where the resistance 19 is not removed, the silicon nitride 18, the first polycrystalline silicon region 14 and the underlying insulating region 12 are left. The resulting structure is illustrated in Figure 1D. For example, (please read the back. Jiangyi matters 洱 媾(Write this page) • Binding-Binding-Lines, Paper Size (CNS) A4 Specification (210X297 mm) 9 522478 A7 _B7_ V. Description of the Invention (7) will be described in the formation of the isolation zone. Two embodiments: LOCOS and STI. In the STI embodiment, the etching continues to a predetermined depth in the substrate 10. The structure is further processed to remove the remaining photoresist 19. Then, an isolation material such as silicon dioxide 20a or 20b is Areas or "recesses" 16. The nitride layer 18 is then selectively removed to form the structure shown in Figure 1E. The well-known LOCOS procedure that results in local field oxides 20a (eg, by oxidizing the exposed substrate) Isolation may be formed, or it may be formed by a shallow trench process (STI) that results in the formation of silicon dioxide in the region 20b (such as depositing an oxide layer and then etching by a chemical mechanical polishing or CMP). Please note During the formation of LOCOS, A spacer is required to protect the sidewalls of the polycrystalline silicon layer 14 during the formation of the local field oxide. The remaining first polycrystalline silicon layer 14 and the first insulating material 12 below form an active region. Therefore, the substrate 10 has The active area, the isolation area, and the isolation area of the staggered stripe are formed by the LOCOS insulating material 20a or the shallow trench insulation material 20b. Although FIG. 1E shows the formation of both a LOCOS area 20a and a shallow trench area 20b, LOCOS Only one of the program (20a) or the shallow trench program (20b) is used. In the preferred embodiment, the shallow trench 20b will be formed. The shallow trench 20b is better because it can be formed more accurately with smaller design rules. .

The structure of Fig. 1E represents a self-aligning structure which is more compact than a structure formed by a non-self-aligning method. A well-known and conventional non-self-aligning method for forming the structure shown in Figure 1E is as follows. An isolation region 20 is formed in the substrate 10 first. This can be done by depositing a layer of silicon nitride on the substrate 10, depositing a photoresist, patterning the silicon nitride using a first photomask step to expose selected portions of the substrate 10, and then using silicon trench formation and trenches involved. Trench filling LOCOS 10 (Please read the notes on the back first, and then fill out this page) The meaning and standard of this company are 33 standards (CNS) A4 specifications (210 X 297 mm) 522478 A7 B7 V. Description of the invention ( 8 program or STI program is completed by oxidizing the exposed substrate 10. Thereafter, the emulsified stone is removed 'and a first layer of oxide 12 (to form the gate oxide) is deposited on the substrate 10. A first layer of polycrystalline silicon 14 is deposited over the gate oxide 12. Then, a second photomask step is used to pattern the first layer of polycrystalline silicon 14 and selected portions are removed. Therefore, the polycrystalline silicon 14 is not related to The isolation region 20 aligns itself and requires a second photomask step. Furthermore, the additional photomask step requires that the dimensions of the polycrystalline silicon 14 have an alignment margin relative to the isolation region 20. Please note that the non-self-alignment method does not use a nitride layer 18. To use self-alignment method or non-self-alignment The structure shown in Figure 1E produced by the uniform method is further processed as follows. Please refer to Figure 2A, which shows the structure from a line of sight perpendicular to Figures 1B and 1E. The subsequent steps in the procedure of the present invention are explained. A thick insulating layer such as silicon nitride (hereinafter referred to as oxide) is formed on the structure, and a thin protective layer 26 such as polycrystalline silicon (hereinafter referred to as `` polycrystalline silicon '') is subsequently formed. The resulting structure is illustrated in FIG. 2A. A photoresist applied to the polycrystalline silicon layer 26 is used to perform a conventional optical lithographic masking operation. A mask step is applied to a strip (ie, a mask area) defined in the X or column direction. Between adjacent strips The distance may be a size determined by the needs of the device to be manufactured. The photoresist is removed in the defined masking area (ie, the strip in the column direction), and is then etched using a conventional non-equival polycrystalline silicon etching process The polycrystalline silicon layer 26 dropped in the stripe under the removed photoresist to expose the lower nitride layer 24. Then, a non-isotropic nitride etching process was performed to remove the exposed portion of the silicon oxide layer 24 to Exposed Polycrystalline silicon layer 14. Then a trade-off polycrystalline silicon etching process can be performed to remove only one of the upper portions of the exposed polycrystalline silicon layer 14, so that the polycrystalline silicon layer 14 is relatively more effective than the rest of the nitride paper. This is a standard of 3 (CNS) Α4 specifications (210X 297 public love) 11 ............... -、 耵 ------------------ 绛 (Please read the notes on the back before filling in this page) 522478 A7 ___ _B7_____ V. Description of the invention (9) Floor 24 It is slightly recessed to form a sloped portion 28 of the polycrystalline silicon layer 14 touching the nitride layer 24. For each pair of mirrored memory cells, these etching procedures result in the formation of a single first trench extending down (and preferably slightly into) the polycrystalline silicon layer 14. The remaining photoresist is then removed, resulting in the structure shown in Figure 2B. A layer of insulating material 32, such as silicon dioxide (hereinafter referred to as "oxide"), is then formed over the structure using, for example, a thermal oxidation process. The portion of the oxide layer 32 formed on the polycrystalline silicon layer 14 in the trench 30 has a raised portion 34 caused by the inclined portion 28 of the polycrystalline silicon 14 and gives the oxide layer 32 in the trench 30 a lens shape. The resulting structure is illustrated in Figure 2C. An insulating spacer 40 is then formed in the trench 30 (FIG. 2E). The formation of spacers is well known in the art, by depositing a material over the structural outline and then performing an asymmetric etching process (such as RIE), whereby the material is removed from the horizontal surface of the structure while the material remains in approximate contact On the vertically oriented surface of the structure. The spacer 40 may be formed of any dielectric material. In the preferred embodiment, the spacers 40 are formed of nitride in the following manner. A conventional chemical vapor deposition (CVD) process is preferably used to form a thin insulating material (ie, oxide) layer 36 over the structure in FIG. 2C, and then a conventional nitride deposition process is preferably used to A thick insulating material (ie, nitride) layer 38 is formed over it, as shown in Figure 2D. A thick nitride etch process using the oxide layer 36 as an etch stop is then performed. This etch process removes all nitride layers 38 except for the side wall spacers 40 along the trench 30 side. An anisotropic oxide etching process using polysilicon layer 26 as an etch stop is then performed. This oxide etch removes the exposed portions of the oxide layers 36 and 32 above the nitride layer 24. The oxide etch also removes the oxide layers 36 and 32. The paper is smashed again and again. This standard is made by 33 domestic standard (CNS) A4 specifications (210X297 mm). 12 -------------- ------------- (Please read the notes on the back before filling out this page) * τ .¾. 522478 A7 ____ B7_ V. Description of the invention (10) In the trench 30 at intervals The exposed portion between the wafers 40 exposes the portion of the polycrystalline silicon layer 14 in the center of the trench 30. The resulting structure is shown in Figure 2E. A thick nitride etch process is performed to remove the spacers 40 from the trenches 30. Then, a polycrystalline silicon etching process is performed to remove the polycrystalline silicon layer 26 to expose the nitride layer 24, and to remove the polycrystalline silicon layer 14 from the exposed part of the center of the bottom of the trench 30 to expose the oxide layer 12. As shown in FIG. 2F, the trenches 30 each have a narrow lower portion 42 bounded by the polycrystalline layer 14 and the halide layers 32 and 36, and an upper wide portion bounded by the oxide layer 36. 44. Please note that the spacer 40 can be removed after the polysilicon etching process for removing a part of the polysilicon layer 14. Implement appropriate ion halide penetration across the entire surface of the structure. Where the ions have sufficient energy to penetrate the first silicon dioxide layer 12 in the trench 30, they then form a first region (terminal) 50 in the substrate 10. In all other regions, ions are absorbed by existing structures and they have no effect. An insulating spacer 46 (such as an oxide) is formed on the side wall of the lower portion 42 of the trench 30. Preferably, the oxide spacer 46 is performed by forming an insulating sidewall layer 48 (oxide) on the side of the polycrystalline silicon layer 14 exposed in the trench 3.0 (ie, by oxidizing the structure or by CVD). Formation. An oxide is then formed over the structure (ie, a CVD process), followed by an oxide anisotropic etching, which is removed from the structure except for the oxide spacers 46 formed on the sidewalls of the lower trench portion 42 The oxide formed above is also applied to the thickness of the vertical portion of the oxide layer 36 in the upper trench portion 44. The non-equivalence also removes one of the upper part of the oxide layer 36, as thin as the part of the oxide layer 36 above the oxide layer 32, and removes the oxide layer 12 each paper-killing standard. This is by SS Home Standard (CNS) A4 Specifications (210X297 mm) 13 ----------------------- install ------------------ ^ ------------------ line (please read the precautions on the back before filling this page) 522478 A7 ___B7_ V. Description of the invention (11) Between the spacer 46 and the channel The bottom of the groove 30 exposes the substrate 10. The resulting structure is shown in 2G 圊. A conductive layer 52 that adheres well to the exposed substrate 10, such as titanium nitride, is formed over the entire structure, which aligns the sidewalls of the trench 30 and the exposed substrate 10 therein. A conductive block 54 is then formed in the trench 30 by depositing a conductive material such as tungsten over the structure, followed by a tungsten planarization process (preferably CMP), and filling the conductive block 54 into the trench 30. form. A tungsten etching step is then performed to remove any tungsten outside the trench 30, and the upper surface of the conductive block 54 is defined below the upper portion of the halide layer 36. A conductive layer 56 (titanium nitride) is then formed over the conductive block 54, preferably by depositing titanium nitride over the structure, and then removing the conductive layer 56 except the conductive layer 56 above the conductive block 54 in the trench 30. One of the deposited titanium nitride planarization (CMP) procedures. A titanium nitride etch is then performed so that the conductive layer 56 is recessed below the upper portion of the oxide layer 36. An insulating material (oxide) layer 58 is then formed over the structure, followed by a planarization process (CMP) and an oxide etch process to remove the deposited oxide other than the portion above the conductive layer 56. The resulting structure is shown in Figure 2H, where the narrow / wide trench portion 42/44 results in a generally T-shaped tungsten conductive square 54 containing a narrow lower square portion 60 and a wide upper square portion 62, which is titanium nitride Surrounded by layers 52/56. The second channel trench 63 is formed between the pair of memory cells and adjacent to the first channel trench 30 in the following manner. It is preferred to use a first-level etching process to remove the nitride layer 24 to expose portions of the polycrystalline silicon layer 14 and the oxide layer 32 as shown in FIG. Then, a polycrystalline silicon etching process (ie, a dry etching) is performed to remove the exposed portion of the polycrystalline silicon layer 14 and scoop out the oxide layer 12. Then throw the scale through a stack of paper. This standard is used by the three national standards (CNS) A4 (210X297 mm> 14;-": 77 ： ...: (Please read the note 7S on the back before filling out this page). Order · 522478 A7 _____B7_ V. Description of the invention (U) Controlled oxide etching is used to remove the exposed portion of the oxide layer 12, exposing a base layer 10 °, preferably an oxide, and an insulating layer 64 is then formed over the entire structure. The structure shown in Figure 2J. The raised portion 34 of the oxide layer 32 results in the formation of a polycrystalline silicon layer 14 that touches the upwardly extending sharp edge 66 of the oxide layer 64. A gate polycrystalline silicon block is formed in the second trench 63 in the following manner ° A thick layer of polycrystalline silicon is deposited over the structure, followed by a non-equilateral polycrystalline silicon lithography process, which removes all but the polycrystalline silicon spacers (boxes) 68 formed immediately adjacent to the vertically oriented portion of the oxide layer 64 The polycrystalline silicon block 68 has a lower portion 70 disposed immediately adjacent to the polycrystalline silicon layer 14 and an upper portion extending beyond the polycrystalline silicon layer 14 including a portion of the sharp edge 66. The polycrystalline silicon block 68 is made of oxygen The physical layers 64 and 32 are insulated from the polycrystalline silicon layer 14. The resulting structure is illustrated in Figure 2K. The insulating spacer 74 is then formed adjacent to the polycrystalline silicon block 68 and is made of one or more layers of material. In the preferred embodiment, The insulating spacer 74 is made of two layers of material by first depositing a thin layer of oxide 76 and then depositing a nitride over the structure. A non-isotropic nitride etch is performed to remove the deposited nitride, The nitrogen spacer 78 is left. A second region (terminal) 80 is then formed in the substrate using ion implantation (such as N +) in the same manner as the first region 50. Then a controlled oxide etch is performed, It removes the exposed portion of the oxide layer 76 and the exposed portion of the oxide layer 64 to expose the base 10 and the second region 80. The resulting structure is shown in Fig. 2L. A metal such as metal, chain, platinum, or molybdenum is deposited on the structure, in the upper part of the substrate 10 next to the side wall spacer 74, and in a layer on the paper scale. This is the same as the S3 Standard (CNS) A4 (210X 297 mm) 15 ----------------------- f ------------------ IT ; ---------------- 绛 (Please read the precautions on the back before filling in this page) 522478 A7 __B7_ V. Description of the Invention (I3) Silicon metal silicon over the silicon block 68 84—Forming a layer of metalized silicon (silicide) 82 »The structure is quenched, allowing hot metal to flow and penetrate into the exposed upper portion of the substrate 10 to form a silicide 82, and penetrate into the exposed upper portion of the polycrystalline silicon block 68 to form metallization Silicon 84. A metal etching process is used to remove the metal deposited on the remaining structures. The siliconized silicon region 82 on the substrate 10 can be referred to as a self-aligned silicide (ie, silicide) because the spacers 78 are aligned in rows to the second region 80. The resulting structure is shown in Figure 2M. A covering such as BPSG 86 is used to cover the entire structure. A photomask step is performed to define an etched area above the silicide area 82. The BPSG 86 is selectively etched in the mask region to create a contact opening ideally above and in the center of the silicide region 82 formed between adjacent sets of paired memory cell cells. The contact opening is then filled back with a conductor metal by metal deposition and planarization etching to form the contact conductor 88. The silicide layer 82 facilitates conduction between the conductor 8.8 and the second region 80. A metal wire 90 is added by the metal above the mask BPSG 86 to connect all the conductors 88 on the memory cell row. The final memory cell structure is illustrated in Figure 2N. As shown in Figure 2N, the first and second regions 50/80 form the source and drain of each cell (one skilled in the art knows that the source and drain can be switched during operation). The channel region 92 of each unit cell is the part of the matrix between the source and drain 50/80. The polycrystalline silicon block 68 constitutes a control gate, and the polycrystalline silicon layer 14 constitutes a floating gate. The oxide layers 32, 36, 46, and 48 together form an insulating layer disposed adjacent to and above the floating gate 14. The oxide layers 36 and 64 together form an insulating layer that isolates the source line from the control gate 68. The control gate 68 has a side aligned with the edge of the second area 80 and is arranged in a part of the channel 16 (please read the precautions on the back before filling the rirT page) 夂 paper 尜 dimensions This is the same as the 33 Chinese standards (CNS ) A4 specification (210X297 mm> 522478 A7 B7 V. Description of the invention (M) above the area 92. The control gate 68 has a lower portion 70 (adjacent to the oxide layer 64) Insulation), and an upper protruding portion 72 (insulated by an oxide layer 64) disposed (extending) above a portion of the adjacent polycrystalline silicon layer 14. A notch 94 is formed by the protruding portion 72, which floats therein The sharp edge 66 of the gate 14 extends into the notch 94. The floating gate 14 is arranged above a part of the channel region 92, and is partially overlapped by one end by the control gate 68, and partially overlapped by the other end The first region 50. The conductive blocks 54 and the conductive layers 52/56 together form a source line 96 extending across a plurality of rows of memory cell cells. A portion 62 above the source line 96 extends beyond the floating gate 14 but is insulated therefrom, The lower part of the source line 96 is adjacent to but insulated from the floating gate 14. As shown in Figure 2 ^^ It is to be noted that the program of the present invention forms a pair of memory cell units that mirror each other. The mirrored memory cell units of each pair are formed by an oxide layer 76, a nitride spacer 78, and a BPSG 86 to form a unit cell pair. Insulation. Please refer to FIG. 20, which shows a top view of the generated structure, and the bit line 90 and the control line 68 are connected to the second area 80. The control line 68 is along the X or column direction and the last source line. 96 is connected to the first region 50β in the base body 10. Although the source line 96 (as should be understood by those skilled in the art, the block, the source, can be interchanged with the block "drain") throughout In the column direction, it is in contact with the base body 10, that is, in contact with the active area and the isolation area. The source line 96 is electrically connected to the first area 50 in the base body 10. In addition, a "source" is connected to each of the lines 96. The first region 50 is shared by two adjacent memory cells. Similarly, each of the second regions 80 connected to the bit line 90 is shared by adjacent memory cells in the memory cells of different mirror sets. It is a kind of non-electrostatic memory cell with multiple separated gates. It has the surface paper method standard (CNS). 4 Specifications (210X297 mm) 17 (Please read the precautions on the back before filling this page)-Binding · Binding —: Line · 522478 A7 ---- 2Z_ 5. Description of the invention (I5) There is a floating gate electrode 14, One of the control gates, which is adjacent to but separate from the floating gate 14 and connected to the length along the column direction and connected to other memory cells on the same column, is also controlled along the column direction and connected One source line 96 of the first region 50 of the memory cell pair in the same column direction and one bit of the second region 80 of the memory cell along the row or Y direction and connected in the same row direction Element line 90. The control gates, floating gates, source lines, and bit lines are all self-aligned. The non-dependent memory cell line has a floating gate to a controlled gate tunnel separation type as described in U.S. Patent No. 5,572,054, which discloses a non-dependent memory cell And the operation of an array formed by it is incorporated herein by reference. The present invention exhibits reduced source line resistance due to the wider upper portion 62 of the T-shaped conductive block 52, while still providing a smaller-scale memory cell scale due to the narrower lower portion 60 of the T-shaped conductive block 52. (That is, the side walls of the first trench 30 between the upper and lower portions 62/60 form a T-shaped source line). The upper portion 62 also extends but is insulated from the floating gate 14, which allows the source voltage to be coupled from the source line 96 through the oxide layer 32/36 to the floating gate 14 (which is added to the through oxide layer 46 / 48 via the lower portion 60 and the transmission oxide layer 12 via the first region 50). Therefore, the coupling coefficient between the source electrode and the floating gate is enhanced. First Alternate Embodiment 3A.31I illustrates a first replacement procedure similar to that illustrated in FIG. 2N, but using a polycrystalline silicon source line to form a memory cell array. This first replacement procedure starts with the same structure as shown in 2G 圊 'but continues as follows. ------- ΓΊνν-0 ^ ----- (Please read the precautions on the reverse side and fill in the ¾ page) Order-夂 Paper is light and light, this standard is 33 standards (CNS) Α4 size (210X 297 public love) .18-522478 A7 B7 V. Description of the invention (16 The conductive block 98 is formed in the trench 30, preferably by depositing a conductive material such as polycrystalline silicon on the structure, and then performing a polycrystalline silicon planarization procedure ( (Preferably CMP) to remove the polycrystalline silicon above the trench 30. Next, a polycrystalline silicon etching back step is performed to remove any polycrystalline silicon outside the trench 30, and the upper surface of the conductive block 98 is recessed below the upper portion of the oxide layer 36. The polycrystalline silicon block 98 may be in-situ doping or doping using implantation. An insulating material (oxide) layer 58 is then formed over the polycrystalline silicon blocks 98, such as by thermal oxidation or deposition by oxidation, followed by a CMP planarization process and a The oxide etching process causes the oxide layer 58 to be recessed below the upper portion of the oxide layer 36. The resulting structure is shown in Figure 3A, where the narrow / wide trench portion 42/44 results in a narrow lower square portion 60 Approximately T-shaped conduction of the upper square part 62 Crystal silicon block 98. The second trenches 63 are formed between the pair of memory cells and adjacent to the first trenches 30 in the following manner. It is preferable to use a first-level etching process to remove the nitride layer 24, as in the first step. Figure 3B shows the exposed polycrystalline silicon layer 14 and oxide layer 32. Then a polycrystalline silicon etching process (ie, a dry etch) is performed to remove the exposed portion of the polycrystalline silicon layer 14 and the exposed portion of the oxide layer 12 » A controlled oxide etch removes the exposed portion of the oxide layer 12, exposing the substrate 10. An insulating layer 64, preferably an oxide, is then formed over the entire structure, resulting in the structure shown in Figure 3C. The oxide layer 32 The raised portion 34 results in the formation of a polycrystalline silicon layer 14 that touches the upwardly extending sharp edge 66 β of the oxide layer 64. A gate polycrystalline silicon block is formed in the second trench 63 in the following manner. A thick layer of polycrystalline silicon is deposited over the structure , And subsequently implemented a non-equal sheet m free use by 33 standards (CNS) A4 specifications (210X 297 mm) 19------------------------ Install ------------------, but ------------------ line. (Please read the Please fill in this page if necessary) 522478 A7 _B7 _ V. Description of the invention (17) (Please read the precautions on the back before digging this page) Fang polycrystalline silicon etching process, except for the vertical alignment part that is close to the oxide layer 64 All of the polysilicon spacers (blocks) 68 are formed. The polycrystalline silicon block 68 has a lower portion 70 disposed immediately adjacent to the polycrystalline silicon layer 14 and a portion extending beyond the polycrystalline silicon layer 14 including a sharp edge 66 Upper part. The polycrystalline silicon block 68 is insulated from the polycrystalline silicon layer 14 by oxide layers 64 and 32. The resulting structure is illustrated in Figure 3D. An oxide etch is performed to remove exposed portions of the oxide layer 64 and the underlying oxide layer 58 to expose the polycrystalline silicon blocks 98 and the substrate 10. Preferably, a dry etching process with endpoint detection is used, which also removes the upper portion of the oxide layer 36 so that it is approximately the same shape as the upper surface of the polycrystalline silicon block 98. An oxide deposition process is then performed to form an oxide layer 100 over the structure and replace the oxide layer 64 over the substrate 10. The resulting structure is illustrated in Figure 3E. -The release spacer 74 is then formed adjacent to the polycrystalline silicon block 68 and is made of one or more layers of material. In a preferred embodiment, the insulating spacer 74 includes removing the deposited nitride by depositing a nitride over the structure, and then performing an anisotropic nitride etch (using the oxide layer 100 as an etch stop). ), Leaving the nitride 78 above the oxide layer 64 and adjacent to the polycrystalline silicon spacer 68, the compound spacer 100 formed by the oxide layer 100 and the nitride spacer 78 "nitride spacer 101 is also formed above the endpoints of the conductive block 98 as shown in FIG. 3F. A second region (terminal) 80 is then formed in the substrate using ion implantation (e.g. N +) in the same manner as the first region 50 is formed. Then, a controlled oxide etching is performed to remove the exposed portion of the oxide layer 100 to expose the polycrystalline silicon square paper: ¾ standard applicable 3 3 standards (CNS) A4 specifications (210X297 mm) 20 522478 A7 B7 V. Description of the invention (18 pieces 98, and the exposed part of the oxide layer 64 is removed to expose the substrate 10. The resulting structure is shown in Figure 3G. By using a tungsten, cobalt, titanium, nickel, platinum or molybdenum, etc. Metal is deposited over the structure, in the upper part of the base body 10 next to the sidewall spacers 74, and a layer of metalized silicon 84 above the crystalline silicon block 68 to form a layer of metalized silicon (silicide) 82. The structure is quenched, allowed Hot metal flows and penetrates into the exposed upper portion of the substrate 10 to form a silicide 82, and penetrates into the exposed upper portions of the polycrystalline silicon blocks 68 and 98 to form metallized silicon 84. A metal etching process is used to remove the metal deposited on the remaining structures The metalized silicon region 82 on the substrate 10 can be called self-aligned silicide (ie, silicide) because the spacer 78 is aligned in rows to the second region 80. The resulting structure is shown in Figure 3H. Uses such as BPSG 86 Covering To cover the entire structure. A photomask step is performed to define the etched area above the silicide area 82. The BPSG 86 is selectively etched in the masked area to create adjacent sets of cells ideally located in pairs of memory cells A contact opening is formed in the upper center of the silicide region 82 and extends down to it. The contact opening is then filled with a conductive metal by metal deposition and planarization etching to form a contact conductor 88. The silicide layer 82 helps the conductor 88 And the second region 80. The metal above the BPSG 86 is used to add a bit line 90 to connect all the conductors 88 in the memory cell row. The final memory cell structure It is illustrated in Figure 31. The first alternative embodiment exhibits a reduced source line resistance due to the wider upper portion 62 of the T-shaped polycrystalline silicon block 98 and the highly conductive metallized silicon layer 84 formed thereon. Due to the narrower lower part 60 of the T-shaped conductive block 98, it still provides a smaller scale of the memory boat. The upper part 62 also extends beyond 21 (please read the precautions on the back before filling in the unpaged pages) 夂 paper 尜The standard is to learn from Chinese S CNS) A4 specification (210X297 mm) 522478 A7 ___B7___ 5. Description of the invention (19) Floating gate 14, which allows the source voltage from polycrystalline silicon block 98 to be coupled to the floating gate 14 through the oxide layer 32/36 (the system (Apply to light transmission of the transmissive oxide layer 46/48 via the lower portion 60, and the transmissive oxide layer 12 via the first region 50.) Therefore, the coupling coefficient between the source electrode and the floating gate is enhanced. Second 4A-4I of the replacement paste embodiment illustrate a second replacement procedure similar to that illustrated in FIG. 2N but using a self-aligned contact design to form a memory cell array. This second replacement procedure starts with the same structure as shown in Figure 2J, but continues as follows. A thick layer of conductive material 102, such as polycrystalline stone, is deposited over the structure as shown in Figure 4A. A layer of nitride 104 is then deposited over the structure, followed by an IL compound planarization process (e.g., CMP). Then, a nitride money recovery step is performed to remove a portion of the nitride layer 104 above the lifted portion of the polycrystalline silicon layer 102, while leaving a portion of the argon layer 104 above the flat side portion of the polycrystalline silicon layer 102. An oxidation step is then performed to oxidize the exposed central portion of the polycrystalline silicon layer 102 to form an oxide layer 106 thereon. The resulting structure is shown in Figure 4B. A nitride etching process is used to remove the nitride layer 104, and then a non-isotropic polycrystalline silicon etching step is performed to remove the exposed central portion of the polycrystalline silicon layer 102 that is not directly below the oxide layer 106, as illustrated in FIG. 4C. An oxide deposition step is then performed to apply a thick oxide layer over the structure. A planarized oxide neodymium etch, such as CMP, is subsequently performed to planarize the structure, using a polycrystalline silicon layer 102 as an etch stop. Then perform a chemical etching back step, leaving oxides on each side of the polycrystalline silicon layer 102. The paper size is in the standard of a S family standard (CNS) A4 (210X297 mm) 22 ---- --- jv fee ...: (炝 Read the precautions on the back before filling this page). Order 522478 A7 B7 5. Box 108 of the description of the invention (20). The oxide layer 106 is also removed by the oxide planarization and etch-back steps, resulting in the structure shown in Figure 4D. The oxide block 108 is then used as an etch stop to perform a planarized polysilicon etch such as CMP, as shown in Figure 4E. Explained. Subsequently, a polycrystalline silicon etch-back procedure such as RIE is performed to remove the upper portion of the polycrystalline silicon layer 102, leaving only the polycrystalline silicon block 103 adjacent to the oxide block 108, and exposing the oxide layer 64. The polycrystalline silicon block 103 has a lower portion 70 disposed immediately adjacent the polycrystalline silicon layer 14 and an upper portion 72 extending beyond the polycrystalline silicon layer 14 including a portion of the sharp edge 66. The polycrystalline silicon block 103 is insulated from the polycrystalline silicon layer 14 by oxide layers 64 and 32. The oxide block 108 and the halide layer 36 are left to extend sufficiently above the surface of the polycrystalline silicon 103, as illustrated in FIG. 4F. A trade-off implantation step may be performed to dope the exposed polycrystalline silicon block 103. A metal deposition step is then performed to deposit a metal such as tungsten, cobalt, titanium, nickel, platinum or molybdenum over the structure. The structure is floated, allowing hot metal to flow and infiltrating the exposed upper portion of the polycrystalline silicon block 103 to form a metalized silicon conductive layer 84 thereon. A metal etching process is used to remove the metal deposited on the remaining structures. The metalized silicon layer 84 can be referred to as self-aligned because the oxide layer 64 and the oxide block 108 are aligned in a row on the polycrystalline silicon block 103. A protective nitride layer Π0 is formed between the polycrystalline silicon block 103 and the oxide block 108 in the following manner. The nitride is deposited over the structure, and then a planarized gaseous layer such as CMP is implemented, and the oxide block log is used as an etch stop layer, so that the nitride layer 110 is the same as the oxide block 108. The nitride layer 110 is aligned in rows from the oxide block 108 to the polycrystalline dream block 103. The resulting structure is shown in Figure 4G. Paper standard (CNS> Α4 size (210X297 mm) 23 .............-.......... ¥ ------------- ----------------------- Fate (谙 Read the precautions on the back before filling this page) 522478 A7 _B7_ V. Description of the invention (21) Then implement one Oxide etch to remove the exposed portions of oxide block 108 and oxide layer 64, as illustrated in Figure 4H. An insulating spacer 74 is then formed adjacent to the polycrystalline silicon block 103 and the nitride layer 110, and is made of one or more layers of material In the preferred embodiment, the insulating spacer 74 is made of two layers of material by first depositing a thin oxide layer 76 and then depositing a nitride over the structure. An anisotropic nitrogen Carbide etching is performed to remove the deposited nitride, leaving the argon spacer 78. Then using ion implantation (such as N +), a second region (terminal) is formed in the substrate in the same manner as the first region 50 is formed. 80. An oxide etch is then performed to remove the exposed portion of the oxide layer 76. By depositing a metal such as tungsten, cobalt, zinc, nickel, platinum, or molybdenum over the structure, between the substrate 10 and the sidewalls A layer of metallized silicon (fragmentation) 82 is formed in the upper part next to the sheet 74. The structure is floated to allow hot metal to flow and penetrate the exposed upper portion of the substrate 10 to form a silicide region 82. The deposition is removed by a metal etching process Metal on the remaining structure. The metallized silicon region 82 on the substrate 10 can be called self-aligned silicide (ie, silicide) because the spacer 78 is aligned in a row to the second region 80. The resulting structure is shown on page 41 Figure. A covering such as BPSG 86 is used to cover the entire structure. A photomask step is performed to define the etched area above the silicide area 82. BPSG 86 is selectively etched in the mask area to produce ideally paired A separate opening ^ nitride layer 110 in the upper center of the silicide region 82 formed between adjacent groups of the memory cell is wider than the silicide region 82. The nitride layer 110 is used in this etching process to protect the polycrystalline silicon block 103 and the silicon metallized silicon. 84. The contact opening is then filled with a conductive metal by metal deposition and planarization, whereby the entire area between the nitride spacers 78 of adjacent sets of pairs of memory cell cells is filled with deposited gold m. This degree 3] board under tiles on roof s g of Standards (OJS) A4 size (297 mm 21〇X) (Please read the back of the precautions to fill out this page)

24 522478 A7 B7 V. Description of the invention (22 properties) to form a contact conductor 88 (that is, a self-aligned contact design, or SAC) aligned with the silicide region 82 by the nitride spacer 78. The silicide layer 82 helps conduct Conduction between the body 88 and the second region 80. The metal above the BPSG 86 adds a bit line 90 to connect all the conductors 88 on the memory cell row. The final memory crystal The cell structure is illustrated in Figure 4J. Self-aligned contact design (SAC) removes one of the important restrictions on the minimum spacing requirement between adjacent pairs of memory cell pairs. In particular, Figure 4J illustrates the contact area ( And therefore, when the conductor 78) is perfectly positioned in the center above the silicide region 76, it is actually difficult to form the contact opening without some undesired horizontal displacement associated with the silicide region 76. With a non-self-aligned contact design, where There is no nitride protection layer above the structure before the formation of BPSG. If the contact area 88 is displaced and formed over the metalized silicon 84 and the polycrystalline silicon block 103, an electrical short may occur. In order to prevent non-self-aligned contact designs For electrical shorts, the contact openings must be formed sufficiently far away from the nitride spacers 78 so that they will not extend to or beyond the spacers 78 even with the greatest possible displacement in the contact area. This is of course at the minimum distance between the spacers 78 A restriction is added to provide a sufficient margin distance between adjacent pairs of paired mirrored unit cells. The SAC method of the present invention eliminates this restriction by using a protective material layer (halide layer Π0) under the BPSG. With this protective layer, the contact opening is formed in the BPSG. Even if the contact opening has a significant horizontal displacement during the formation, there is still sufficient width to determine that the contact opening and the silicide region 82 are heavy. The halide layer 110 allows partial contact. There is no short circuit in the area 88 during the 25 (please read the precautions on the back before filling in this page) The dimensions of each paper scale are from a 3 standard (CNS) A4 specification (210X297 mm) 522478 A7 _ _ B7_ 5 2. Description of the invention (23) It is formed above the polycrystalline silicon block 103 or the metallized silicon layer 84. The wide contact opening ensures that the contact area 88 completely fills the extremely narrow space between the spacers 78 and is silicided. 82 has good electrical contact. Therefore, the width of the contact area between the spacers 78 can be minimized, while preventing erroneous connections caused by filling the space between the spacers 78, allowing the entire cell size to be reduced. The second alternative embodiment has A further advantage is that the control gate 103 is substantially rectangular and includes a protruding portion above the floating gate 14 and a flat opposing surface that helps the formation of the spacer 74, which in turn promotes the self-aligned formation of the silicide region 82, and Formation of Self-Aligned Conductor 88. The third alternative embodiment, Figures 5A-5K, illustrates a third replacement procedure similar to the one described in Section 31, but using a self-aligned contact design to form a memory cell array. This third replacement procedure starts with the same structure as shown in Figure 3C, but continues as follows. A thick layer of conductive material 102, such as polycrystalline silicon, is deposited over the structure as shown in Figure 5A. A layer of halide 104 is then deposited over the structure, followed by a gaseous planarization process (e.g., CMP). Then, a gasification step is performed to remove a portion of the nitride layer 104 above the lifted portion of the polycrystalline silicon layer 102, while leaving a portion of the nitride layer 104 above the flat side portion of the polycrystalline silicon layer 102. An oxide step is then performed to oxidize the exposed central portion of the polycrystalline silicon layer 102 to form an oxide layer 106 thereon. The resulting structure is shown in Section 5B 囷. A nitride lasting process is used to remove the nitride layer 104, and then a non-equal polycrystalline silicon etching step is performed to remove the polycrystalline silicon layer 102. The oxide surface paper is not scaled in accordance with 33 standards (CNS) A4 (210X297). %) 26 ------- «Fee ------------------ Order ---------------- Xin (Please (Read the back of the page first: work items before filling out this page) 522478 A7 B7 V. Description of the invention (24) Those parts directly under layer 106, as illustrated in Figure 5C. An oxide deposition step is then performed to apply a thick oxide layer 108 over the structure. A planarizing oxide etch such as CMP is subsequently performed to planarize the structure, using the polycrystalline silicon layer 102 as an etch stop. An oxide etch-back step is then performed, leaving the blocks 108o of oxide on either side of the polycrystalline silicon layer 102. The oxide layer 106 is also removed by the oxide planarization and retrace steps. A nitride deposition step is then performed to apply a nitride layer over the structure. A planarized nitride etch such as CMP is subsequently performed to planarize the structure, and the polycrystalline silicon layer 102 is used as an etch stop. A nitride etch-back step is then performed, leaving a nitride layer 109 over the oxide block 108. The resulting structure is shown in Figure 5D. A planarized polycrystalline silicon etch such as CMP is then performed, using the nitride layer 109 for an etch stop. Subsequently, a polycrystalline silicon etching process such as RIE is performed to remove the upper portion of the polycrystalline silicon layer 102, leaving only the polycrystalline silicon block 103 adjacent to the oxide block 108, and exposing the oxide layer 64. The polycrystalline silicon block 103 has a lower portion 70 disposed immediately adjacent to the polycrystalline silicon layer 14, and an upper portion 72 extending a portion of the polycrystalline silicon layer 14 including a portion of sharp edges 66. The polycrystalline silicon block 103 is insulated from the polycrystalline silicon layer 14 by oxide layers 64 and 32. The oxide block 108 and the oxide layer 36 are left to extend sufficiently above the surface of the polycrystalline silicon 103, as described in Section 5F (i). A controlled oxide etch is performed to remove the exposed horizontal portion of the oxide layer 64 and the underlying oxide layer 58 to expose the polycrystalline silicon block 98. Preferably, a dry etching process with endpoint detection is used, which also removes the upper part of the oxide layer 36, as illustrated in Figure 5G. 27 (Please read the notes on the back before filling out this page) Each paper size is compatible with 33 standards (CNS) A4 specifications (210X297 mm) 522478 A7 ____B7_ 5. Description of the invention (25) A one-shot implantation can be implemented Steps to dope the exposed polycrystalline silicon block 103. A metal deposition step is then carried out to deposit a metal such as a town, start, drink, record, platinum or molybdenum on the structure. The structure is fired to allow hot metal to flow and penetrate the exposed upper portions of the polycrystalline silicon blocks 103 and 98 to form a metalized silicon conductive layer 84 thereon. A metal etching process is used to remove the metal deposited on the remaining structures. The metallized silicon layer 84 can be referred to as self-aligned because the oxide layer 64 and the oxide block 108 are aligned on the polycrystalline silicon block 103 in a row. A protective nitride layer 110 is formed between the polycrystalline silicon block 103 and the oxide block 108 in the following manner. The nitride is deposited over the structure, and then a planarized halide etch such as CMP is performed, using the oxide block 108 as an etch stop layer, so that the nitride layer U0 is the same as the oxide block 108. The nitride layer 109 is also removed by this procedure. The nitride layer Π0 is aligned from the halide block 108 to the polycrystalline silicon block 103. The resulting structure is shown in Figure 5. An oxide etch is then performed to remove the exposed portions of oxide block 108 and oxide 蜃 64, as described in Section 51 圊. The insulating spacer 74 is then formed adjacent to the polycrystalline silicon block 103 and the nitride layer 110, and is made of one or more materials. In the preferred embodiment, the insulating spacer 74 is made of two layers of material by first depositing a thin oxide layer 76 and then depositing a nitride over the structure. An anisotropic argon etch is performed using oxide layer 76 as an etch stop to remove deposited nitrides other than nitride spacers. A second region (terminal) 80 is then formed in the substrate using ion implantation (such as N +) in the same manner as the first region 50 is formed. An oxide etch is then performed to remove the exposed portion of the oxide layer 76. By using standards such as tungsten, cobalt, and tissue paper, this standard (CNS) A4 (210X297 mm) 28 .......----- (Please read the precautions on the back before (Fill in this page) Order — 522478 A7-~ --_— V. Description of the invention (26) A metal such as Qin, Lu, Shi or Sha is deposited above the structure and formed in the upper part of the base 10 next to the side wall spacer 74. A layer of metalized silicon (silicide) 82. The structure is quenched, allowing hot metal to flow and penetrate into the exposed upper portion of the substrate 10 to form a silicide region 82. A metal etching process is used to remove the remaining metal deposited on the remaining structures. The metalized silicon region 82 on the substrate 10 can be called self-aligned silicide (i.e., silicide) because the spacer 78 is aligned in a row to the second region 80. The resulting structure is shown in Section 5J 圊. A covering such as BPSG 86 is used to cover the entire structure. A photomask step is performed to define an etched area above the silicide area 82. The BPSG 86 is selectively etched in the mask region to create a contact opening that is ideally above the center of the stone material region 82 formed between adjacent sets of paired memory cell cells and wider than the stone material region 82. The nitride layer Π0 is used in this etch process to protect the polycrystalline silicon blocks 103 and the metallized silicon 84. The contact opening is then filled with a conductive metal by metal deposition and planarization, thereby filling the entire area between the gas spacers 78 of adjacent pairs of memory cell cells with deposited metal to form The contact spacers 88 (i.e., self-aligned contact designs, or SAC) are aligned with the silicide regions 82 by the nitride spacers 78. The silicide layer 82 facilitates conduction between the conductor 88 and the second region 80. A bit line 90 is added by the metal above the mask BPSG 86 to connect all the conductors 88 on the memory cell row together. The final memory cell structure is illustrated at 5κκ. The third alternative embodiment has the advantage of combining the advantages of the first alternative embodiment with the advantages of SAC. Please understand that the present invention is not limited to the embodiments described above and described here. CNTS) Α4 size (210X297 mm)

(Please read the notes on the back before clicking this page) 29 522478 A7 _-_____ B7_ V. Description of Invention (27) '~' — Includes any and all changes within the scope of the scope of the attached patent application. For example, 'While the foregoing method describes the use of appropriately doped polycrystalline stones as the conductive material used to form the memory cell, those skilled in the art will appreciate that any suitable conductive material can be used. In addition, any suitable insulator can be used in place of silicon monoxide or silicon nitride. Furthermore, any suitable material whose etching characteristics are different from silicon dioxide (or any insulator) and different from polycrystalline silicon (or any conductor) may be used in place of gasified rocks. Furthermore, as is clear from the patent application, not all method steps need to be performed in the order illustrated and applied, but in any order that allows the proper formation of the memory cell of the present invention. Finally, the upper and lower portions of the first trench need not be symmetrical, but the first trench only needs to have a shrinkage on its wall, so that the source line formed therein has a first adjacent to the floating gate. A part, and a second part disposed above the floating gate. Each paper m 3 of the three standard (CNS) A4 specifications (2ΐοχ297 Male f) ------- see ... (Please read the precautions on the back before filling this page), a t- 30 522478 A7 B7 V. Description of the invention (28) Comparison of component numbers 10 ... semiconductor substrate 12 ... first layer of insulating material 14 ... first polycrystalline silicon layer 16 ... strip 18 ... silicon nitride layer 19 ... photoresist material 20 ... isolation region 20a, 20b ... isolation material 22 ... thick silicon oxide layer 22a ... insulation layer 24 ... thick nitride insulation layer 26 ... polycrystalline layer 28 ... inclined portion 30 ... first trench 30, 30a ... trench 31 32, 58, 64 ... Insulating material layer 34 ... Lifting portion 36 ... Thin insulating material layer 38 ... Thick insulating material layer 40, 46, 74 ... Insulating spacers 42, 70 ... Lower portions 44, 72 ... Upper Section 48 ... Insulating sidewall layer 50 ... First regions 52, 56 ... Conductive layers 54, 98 ... Conducting block 60 ... Lower block portion 62 ... Upper block portion 63 ... Second trench 66 ... Sharp edge 68 ... Polycrystalline silicon spacers (squares) 76 ... thin oxide layers 78,101 ... nitride spacers 80 ... second regions 82,84 ... metalized silicon (silicide) layers

86 ... BPSG 88 ... conductor 90 ... bit line 92 ... channel area 94 ... notch 96 ... source line 100, 106 ... oxide layer 102 ... thick conductive material layer 103 ... polycrystalline silicon block 104, 109, 110 ... Nitride layer 108… Oxide block (please read the notes on the back before filling this page) -31 33 standards (CNS) A4 specifications (210X297 male f) in various paper sizes

Claims (1)

Employees of the Ministry of Economic Affairs, Smart Time and Industry Bureau, Consumer Consumption Tlurlvii 522478 C8 D8 6. Scope of Patent Application 1. A self-aligning method used to form a semiconductor memory array, one of the floating gate memory cells, in a semiconductor matrix. The body cell has a floating gate, a first terminal, a second terminal with a channel region therebetween, and a control gate. The method includes the following steps: a) forming a plurality of spaced isolations on the substrate; The isolation regions are substantially parallel to each other and extend in a first direction. There is an active region in each pair of adjacent isolation intervals, and each of the active regions includes a first layer of insulating material on the semiconductor substrate, and A first layer of conductive material on the first layer of insulating material; b) forming a plurality of spaced first trenches across the active area and the isolation area, the first trenches being substantially parallel to each other and substantially perpendicular Extending in a second direction of the first direction, each of the first trenches has a sidewall including a grid formed therein; c) filling a first conductive material into each of the first trenches To form a plurality of first squares of the conductive material, wherein for each of the first squares in each of the active areas: the first square includes one of the first squares formed below the contraction in the sidewall of the first trench. A lower part, the lower part is disposed adjacent to the first layer of conductive material and is insulated therefrom; and the first block includes an upper part formed above the contraction of the first trench side wall The upper part is disposed above the first layer of conductive material and is insulated from it; d) forming a plurality of first terminals in the base 1 1 to make each of the first terminals in each of the active areas Adjacent to these conductive materials, the first two, the second and the third, and the bow = 3 1 home! (CNS) A4 specification (210 X 297 mm) Ί · -------- t ---------. ≪ Please read the notes on the back before filling in this page) 32 522478 A8 B8 C8 D8 Scope of patent application Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs have cooperated with consumers to make Indian materials. The lower and upper parts of each of the first blocks are insulated from the first conductive material layer by the second insulating material layer. 6. The method according to item 1 of the scope of patent application, further comprising the steps of forming a plurality of spaced second trenches substantially parallel to each other and parallel to the first trenches; forming a first trench in the second trenches One of the two blocks is a conductive material for each of the second conductive material blocks: the second block includes a lower portion disposed adjacent to the first layer of conductive material and insulated from the second block; Above the first layer of conductive material and -_ in the block, and is electrically connected to it; and e) forming a plurality of second terminals in the base vessel, wherein each of the second terminals is connected to each of the active areas The first-terminals are separated. 2. The method according to the scope of the patent application, wherein the first squares of the conductive material are substantially rectangular. 3. The method according to item p of the patent application, which further comprises the following steps:-forming a layer of metal fossil on each of the first-conductive material blocks. 4. The method according to item 1 of the scope of patent application, which further comprises the following steps: Before forming the first conductive material blocks, a second layer of conductive material is formed in the first trenches. 5. The method according to item 丨 of the scope of patent application, which further includes the following steps: forming a second layer of absolute ones along the side walls of each of these first trenches Standard a (CNS) A4 specification (210 X 297 mm) -------------- ^ -------- I -------- line, please first (Please read the notes on the back and fill in this page) 33-522478 6. The upper part of the scope of patent application and its insulation. The method according to item 6 of the patent application scope further includes the following steps: forming a layer of metal fossil on each of the second conductive material blocks. 8. The method according to item 丨 of the patent application scope, wherein the formation of the first trenches includes the following steps: forming at least one layer of a first material above the first conductive material layer; selectively etching through the at least one A first material layer to form the upper portions of the first trenches; forming at least one layer of a second material along a lower surface of one of the first trenches; in each of the first trenches Sidewall spacers are formed on the sidewalls; in each of the first trenches, etching is performed between the sidewall spacers, and the at least one second material layer is etched to expose a portion of the first conductive material layer ; And etching the exposed portion of the first conductive material layer to form the lower portions of the first trench; the employees of the Intellectual Property Management Bureau of the Ministry of Economic Affairs and the consumer concession system in which the side walls are formed Between the upper and lower portions of the first canals. 9. The method according to item 6 of the patent application scope, further comprising the steps of: forming an insulating material sidewall spacer along one side wall of each of said second conductive material blocks; and forming a layer on each of said second terminals Silicon metallization, where each Pan IIS uses = 3 S family standard! (CNS) A4 size (210 X 297 mm) 522478 Make sure to read the notes on the back before filling in this page. K Consumer spending cooperation with the Intellectual Property Bureau of the Ministry of Economic Affairs-iilbn ^ 522478 A8 B8 C8 _ D8 VI. A layer of silicon metallization is formed on each of these second terminals between the scope of patent application So that the layer of metallized silicon is aligned with the second terminal by the side spacers of the corresponding pair; a layer of protective insulating material is formed above the 4 first conductive material block; a layer is formed above the dedicated active area Cover material; forming a plurality of contact openings through the covering material, wherein for each of the contact openings: the contact opening extends down to one of the metalized silicon layers and exposes it, the contact opening has A lower part of the side wall spacers of the corresponding pair, and the contact opening has an upper part wider than a pitch of the side wall spacers Pel of the corresponding pair; and a conductive material is filled in each of the Wait for the opening. 14. The method according to item 1 of the scope of patent application, wherein: each of said first trenches has an upper portion and a lower portion 'the upper portion has a larger one than the lower portion A width; the lower part of each of the first squares is formed in one of the lower parts of one of the first trenches; and the upper part of each of the first squares is formed Within one of the upper parts of one of the first trenches. 15 · —An array of electrically programmable and erasable memory devices, including: a substrate of a first conductivity type semiconductor material; (Please read the precautions on the back before filling this page) ----- --- Order · -------- · 36. A8B8C8D8 522478 6. The scope of the patent application is formed on the substrate, which are generally flat with each other and extend in a first direction. There are a plurality of separated isolation areas, an active area in each pair of adjacent isolation areas, and each of these active areas. The region includes a plurality of pairs of memory cell units extending in the first direction, and each of the memory cell unit groups includes: a first region separated in the matrix having a second conductivity type; and A pair of second regions, a channel region is formed in the substrate between the first region and the second sections, and a first insulating layer disposed above the substrate and including the channel regions is disposed on the first region. A pair of electrically conductive floating gates above the insulating layer and extending above a portion of one of the channel regions and a portion of the first region, and disposed above the first region in the substrate, And an electrically conductive source region that is electrically connected to it, the source region has a lower portion disposed adjacent to and insulated from the pair of floating gates, and ^ is disposed above the pair of floating gates and One that is insulated from it • upper part. '16. The device according to item 15 of the scope of patent application, wherein the source region has a width larger than that of the upper portion than the lower portion of the source region. 17. The device according to item 16 of the patent application, wherein the source region has a substantially T-shaped cross-section. 18. The device according to item 15 of the scope of patent application, in which each of the source regions extends across the second direction approximately perpendicular to the first direction —______ 不 尺 芰 = 3National Standard Jade (CNS) A4 Specifications (210x297 public love) n ϋ n 1 »· n I nlnn —in stupid ·· ϋ n ϋ n ϋ n I ^ eJ · nn ϋ m —m ϋ n I (Please read the notes on the back before filling this page ) The staff of the Intellectual Property Bureau of the Ministry of Economic Affairs has eliminated the issue of spitting 37 522478 A8B8C8D8 The consumption of employees of the Ministry of Economic Affairs of the Bureau of Intellectual Property and Time Consumption ££ Imprint Ⅵ. Active areas and quarantine areas such as the scope of patent application, and submit such memories One of the unit cell pairs in each such active region. 19. The device according to item 15 of the scope of the patent application, wherein each of the memory cell pairs further includes: disposed above each of the floating gates, adjacent to the floating gate, and having a charge allowing Fowler-Nordheim to pass through A second insulating layer having a thickness; and a pair of electrically conductive control gates each having a first portion and a second portion, the first control gate portion being disposed adjacent to the second insulation Layer and one of the floating gates, and the second control gate portion is disposed above a portion of the second insulating layer and a portion of the one floating gate. 20. The device according to item 19 of the scope of patent application, wherein each of the control gates extends across the active area and the isolation area in a second direction substantially perpendicular to the first direction, and intercepts the memory One of the unit cell pairs in each of these active regions. 21 · —An electrically programmable and erasable memory device, comprising a base body of a first conductivity type semiconducting material; first and second spacers in a base conductivity of a second conductivity type An open region with a channel region therebetween; a first insulating layer disposed above the substrate; a first insulating layer disposed above the first insulating layer and extending over a portion of the channel region and a portion of the first region Electrically conductive floating gate: and I ----- HI n II n mmtm · nnn · ϋ n IJ, · n 1 · ϋ nnn ί I --- I —--; * ^ ^ r Note on the back, please fill in this page again) 38 522478 A8 B8 C8 D8 VI. The scope of the patent application is located above the first area in the base and is electrically connected to an electrically conductive conduction source area 'the source area There is a lower portion disposed adjacent to and insulated from the floating gate, and an upper portion disposed above and insulated from the floating gate. 22. The device according to item 21 of the scope of patent application, wherein the source region has a width larger than that of the lower region of the source region. f 23. The device according to item 22 of the scope of patent application, wherein the source region has a substantially T-shaped cross-section. 24. The device according to item 21 of the scope of patent application, further comprising: a second insulating layer disposed above the floating gate electrode and adjacent to the floating gate electrode and having a thickness allowing a charge Fowler-Nordheim to pass through; and An electrically conductive control gate of a first part and a second part, the first control gate part being disposed adjacent to the second insulation > layer and the floating gate, and the second The control gate part is disposed above a part of the second insulation layer and a part of the floating gate. ---------------- (Please read the precautions on the back before filling out this page) ί ΤΤ Consumption of employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, India and India ¾ Meaning this country is 〇g Saitama (CNS) A4 specifications (210 X 297 public love)