TW561591B - A stack-gate flash memory cell structure and its contactless flash memory arrays - Google Patents

Abstract

The stack-gate flash memory cell structure of the present invention comprises a floating-gate structure with a thinner floating-gate layer being formed in a central portion by using a spacer-formation technique; an implanted region being formed in the central portion of a channel for adjusting threshold-voltage and forming a punch-through stop; and a highly conductive control-gate structure spaced with an integrate-dielectric layer being formed over the floating-gate structure. The contactless NOR-type array of the present invention comprises a plurality of common-source conductive bus lines and a plurality of planarized common-drain conductive islands being integrated with a plurality of metal bit-lines. The contactless parallel common-source/drain bit-line array comprises a plurality of common-source/drain conductive bit-lines and a plurality of metal word-lines being integrated with a plurality of planarized control-gate conductive islands.

Description

561591 V. Description of the invention (1) Background of the invention: (1) Scope of the invention The present invention relates to a non-volatile (n 0 n — v 0 1 a 11 i 1 e) semiconductor memory element and its semiconductor memory array, especially It is related to a kind of stacked gate flash memory cell structure and its contactless flash memory array. (2) Known techniques describe a stack-gate flash memory (f 1 ash) memory cell that is well known as a single transistor cell, where the gate length of the cell can be minimized using one of the technologies used Line width (minimum-feature-size) F to define. Therefore, this stacked gate flash memory cell is commonly used in today's high density memory systems. FIG. 1A shows a typical schematic structure diagram of a stack of gate memory cells. A gate-stack includes a control gate layer (CG) 1 04a and an intergate dielectric layer 1. 3a, a floating gate layer (FG) 102a, and a tunneling dielectric layer 101a are patterned and placed on a semiconductor substrate 100; a doubly e-diffused source structure includes A shallow highly doped source diffusion region 10 6 a is formed within a deeper lightly doped source diffusion region 105 a at a source edge of the gate stack; and a shallow highly doped source diffusion region 106a is formed on a drain of the gate stack. The dual-diffusion source structure is used to eliminate band-to-band tunneling during the scrubbing operation.

561591: V. Description of the Invention (2)-Effect and provide a large overlapping area for source-side scrubbing. The shallow south doped drain diffusion region 106a is mainly used to form a drain electric field to generate thermoelectric + to operate as a writer. The asymmetric source / drain diffusion structure shown in Figure-A can be used to form a NOR-type flash memory array. ^ FIG. 1B shows another typical schematic structure diagram of a stacked gate flash memory cell. A gate stack is also formed and formed on a semiconductor substrate 100, and has a highly doped source / drain. The diffusion regions i 05a / 105b are a symmetrical source / drain diffusion region structure formed on each side of the gate stack, respectively. The symmetric source / drain diffusion structure is mainly a NAND-type flash memory array. It can be clearly seen from Figures 1A and 1B that when the gate length of the gate stack is miniaturized, the gate is proportional to the square of the gate length. The puncture (punch -1 hr ugh) voltage of the memory cell will decrease rapidly. The reduction of the breakdown voltage becomes a major concern of Figure 1A, because a moderately high drain voltage can be written by the hot electron injection method. For the same reason, the depth of the junction between the source / drain diffusion region must also be shallower. The scrubbing area using source-side scrubbing or substrate scrubbing will be smaller, and the scrubbing mystery will be slower: In addition, a non-split array The readout speed will be slowed down due to the shallow common source; a high stray source / drain series resistance in the second scattered region. Therefore, one of the main objects of the present invention is to provide a stack memory gate with a high-efficiency resistance to the prohibited area structure. 2. Another object of the present invention is to provide one of the shallow source / drain diffusion regions with conductive pipelines or islands to improve the contact resistance and contact angle of a flash memory array.

Page 6 561591 V. Description of Invention (3) Completeness. A further object of the present invention is to provide a contactless structure of flash memory arrays with different configurations. When the ground structure is connected to the element, the cell is connected to the same gate and the floating structure is remembered to record the individual flash points and the fast regions; One of the gates and one pile of open areas in the open area are divergent. The source stack shows a stack of open arrays: Ming Yi contains a description of the hairpin package, the outline of which is less than the bright to the point of the formation of the cloth, and the first high-rise wall of the entire pair of knots off the gate side In this case, the pressure component in the float floats, and the boundary of the stack of the electric shape part is forbidden to form a barrier between the overlap and the stop. The intermediate part of the stack is used to pass through the layer of the electric formation. The channel-shaped structure is used to form a zebra layer. One layer is separated from the other. In the shallow section of the gate, there is a floating layer. A floating wall. A cloth pad structure. The gate is two, the wall is deep, the first to the more remote control is the opposite side, the side electric appliances are planted, two guides, or the complex area is non-flashing. Ranked and Yuan-Yi array cells: / Yi Li thin column source memo array common flash slot memory line quick recess flash type flat shallow flash point or row gate fast connection non-flat stack point no point stack inoculation and multiple planting There is nothing and nothing and the state of being listed in the formation of the Ming formation is the same as the memory. Heap. Forming memory of two fast array gates on a flashbook stack

561591 V. Description of the invention (4) Contains: a plurality of floating gate structures are alternately formed on the plurality of active areas and have an extension control gate conductive layer sandwiched by a gate dielectric layer formed on the plurality of floating gate structures and a plurality of The first protruding field oxide layer is used as a word line, and the plurality of ion-implanted regions of the first conductivity type are formed in a middle portion of the plurality of active regions to adjust a threshold voltage and form a forbidden region; The common source conductive pipeline is formed on the plurality of first flat beds between the first side wall dielectric pads, wherein each of the plurality of first flat beds is alternately formed by a common source of a second conductivity type. A diffusion region and a third protruding field oxide layer; a plurality of planarized common-drain conductive islands are formed on the second conductive-type multi-drain diffusion region between the other first sidewall dielectric pads, Wherein the other first side wall dielectric cushion layer is disposed on a part of the surface of the plurality of second flat beds and each of the plurality of second flat beds is alternately shared by a second conductive type. Diffusion zone and a A third protruding field oxide layer; and a plurality of metal bit lines are connected to the plurality of planarization and conductive conductive islands and are formed perpendicular to the plurality of gate stacks. A contactless parallel common source / drain bit line flash memory array of the present invention includes at least a plurality of gate stacks formed in a plurality of parallel shallow groove isolation regions and a plurality of active regions alternately formed in a first conductive type. A shallow groove isolation region structure on a semiconductor substrate, wherein each of the plurality of gate stacks includes at least: a plurality of floating gate structures are alternately formed on the plurality of active regions and have a plurality of planarization control conductive islands An inter-gate dielectric layer is formed on the plurality of floating gate structures, and a plurality of ion-implanted regions of the first conductivity type are formed in a middle portion of the plurality of active regions to serve as an adjustment of the threshold voltage and a breakdown prohibition. Area; complex common source / drain bit line

561591 V. Description of the invention (5) formed on a plurality of first / second flat beds between the first side wall dielectric pads, wherein each of the plurality of first / second flat beds is formed by a first A common source / drain diffusion region of a two-conductivity type and an alternating ground composition of a third protruding field oxide layer; and a plurality of metal word lines connected to the plurality of planarization control gate conductive islands and integrated with the plurality of common sources The / drain bit lines are formed perpendicular to each other. Brief description of drawing number: 3 0 0 semiconductor substrate 3 0 2b floating gate layer 3 0 3a first mask dielectric layer 3 0 4b first protruding field oxide layer 3 0 4d third protruding field oxide layer 3 0 6a Doped common source diffusion region 3 0 7a Moderately doped common drain region 3 0 8a First side wall dielectric pad 3 0 9b Common source conductive line 3 1 1 a Second side wall dielectric pad 301 b Penetrating dielectric layer 3 0 2 c floating gate structure 3 0 4 a planarized field oxide layer 3 0 4c second protruding field oxide layer 30 5a second mask dielectric layer 3 0 6b shallow highly doped common source Diffusion region 3 0 7b Shallow highly doped co-diffusion region 309a Planarize the second conductive layer 3 1 0 a Planarize the thick silicon dioxide layer 3 1 2 a Ion implanted region

313a inter-gate dielectric layer 314a planarization third conductive layer 3 1 4b control gate conductive layer 3 1 4c planarization control gate conductive island 315a planarization cover thick silicon dioxide layer 316a metal bit (word) element line 317a cover screen Electrical layer 3 1 8 a Side wall · Dielectric pad

Page 9561591 V. Description of the invention (6) Detailed description of the invention: Please refer to FIG. 2A to FIG. 2F, which discloses the manufacturing of the present invention-a kind of stacked gate flash memory cell structure and its contactless fast Process steps and a sectional view of a shallow groove isolation (ST I) structure of a flash memory array. FIG. 1 a shows that a penetrating dielectric layer 301 is formed on a semiconductor substrate 300 of a first conductivity type, a first conductive layer 302 is formed on the read dielectric layer 301, and then a first A mask dielectric layer 303 is on the first conductive layer 302. Next, the multiple mask photoresist pR1 is ^^. The first mask dielectric layer 30 3 is used to define a plurality of active regions (pRi; a plurality of parallel shallow groove isolation (STI) regions (^ 丨 of)), and the width and spacing of the resistance m can use the technology used "( F) to define. The penetrating dielectric layer 3 () 1 is a 4 wide gasification (mountain vice) thermal oxygen cut layer, and its thickness is 1 to 2 or ^ ^ ^ ^ 3 0 2 # # 1 〇 And use low-pressure chemical vapor deposition (LPCVD) method to pile up the material, non-say that the silicon layer is between 10 ° angstrom and 300 angstrom. The first-mask dielectric reed, 3. = Department of It is composed of silicon and stacked by LPCVD method, i 2 ^ 03 is nitrided between 2000 angstroms, and thickness is between 500 angstroms and Figure 2B shows the photoresistor pR located in the complex mask. Dielectric layer 303, the first conductive layer, and the first mask of the perforated layer are anisotropically dry-etched to remove the 'sade 1 electrical layer 301 sequentially anisotropically The ground name is engraved to form a shallow groove. The conductor substrate 300, the groove 4 and the shallow groove are on the semiconductor substrate 561591. V. Description of the invention (7) The depth of 300 is between 4000 angstroms and 1000 angstroms. Between the Angstroms. Figure IIC shows the multiple mask light PR 1 is removed, and then a planarized field oxide layer 3 0 4 a is used to fill in each void formed by the shallow groove. The planarized field oxide layer 304 a is composed of SiO 2 and scale glass (P_glass ) Or borophosphate glass (BP-glass) and using high-density plasma (HDP) CVD method or plasma enhanced (PE) CVD method to deposit, first deposit a thick silicon dioxide film 3 0 4 to fill The gap is then planarized by a chemical-mechanical polishing (CMP) method and the first mask dielectric layer 30 3a is used as a polishing stop. It is worth mentioning here that Prior to the planarized field oxide layer 3 0 4 a, a thermal oxidation process can be performed to form a thin thermal silicon dioxide layer on the semiconductor surface of the shallow groove to eliminate the defects generated by the shallow groove. Figure 2D shows that the planarized field oxide layer 304a is etched back using anisotropic dry etching or wet etching—a depth equal to the thickness of the first mask dielectric layer 303a. To form a first protruding field oxide layer 3 0 4 b. FIG. 2E shows the first mask The layer 303a is selectively removed by using high-temperature phosphoric acid or anisotropic dry etching to form an alternating layer formed by the first protruding field oxide layer 3 0 4 b and the first conductive layer 3 0 2 a. A shallow groove isolation structure with a flat surface composed of ground. It is worth mentioning here that the flat surface shown in FIG. 2E can use a silicon dioxide layer as a first mask dielectric layer 303 or not. This first mask dielectric layer 303 is needed to obtain it. FIG. 2F shows that a second mask dielectric layer 305 is formed in the shallow groove.

561591

V. Description of the invention (8) Above the isolation structure. The second mask dielectric layer 305 is composed of nitride nitride and is deposited by LPCVD method, and has a thickness between 300 angstroms and 300 angstroms. An issue marked by an F-F 'line along the active area in FIG. 2F is shown in FIG. 3A. Referring now to FIGS. 3A to 3I, the potential steps and cross-sectional views of manufacturing a stacked gate flash memory cell structure and a contactless flash memory array according to the present invention are disclosed. Figure 3A shows the formation of a plurality of mask photoresist PR 2 ^ The second mask dielectric layer 3 05 is defined to define a complex gate stack region (below PR2) and a complex common source / drain region (outside PR2) . The width and pitch of the multiple mask photoresist PR2 can be defined using a minimum line width (F) of the technology used. FIG. 3B shows that the second mask w electric layer 3 0 5 located outside the multiple mask photoresist pr2 is removed by non-isotropic dry-etching, and then the first protruding field oxide layer 304 is removed. b is etched back to a depth equal to the thickness of the first conductive layer 302a to form a second protruding field oxide layer 3 04c, and then the first conductive layer 3 0 2a is selectively removed by an anisotropic dry etching method, Then remove the multiple mask photoresist PR2. Figure 3B again shows that multiple mask photoresist PR3 (a) -1 is placed on the multiple common drain region and a part of the surface adjacent to the gate stack, and then crosses the penetrating dielectric layer in an automatic alignment manner. 3 0 1 a is implanted with dopants in the semiconductor substrate 300 in the active region to form a plurality of lightly doped common source diffusion regions of a second conductivity type in each of the plurality of common source regions. For a Bu semiconductor substrate 300, the dopant is based on phosphorus ions to form the complex lightly doped common source diffusion region 306a. Figure 3C shows that the multiple mask photoresist PR3 (a) -1 is removed, and then the multiple mask photoresist PR3 (b) -1 is formed in the multiple common source region and the adjacent gate stack region.

Page 12 561591

V. Description of the invention (9) A part of the surface μ,, Lei 'is then automatically aligned across the penetrating medium w I 1 a to implant impurities in the semiconductor substrate of the active region 3 0 0 A complex light or moderate (m 0derate 1 y) doped co-drainer is used internally to perform a well-known rapid thermal annealing (RTA) system. ^ ^ Activation ^ diffusion implanted impurity exchange . For a P-type semiconductor substrate, the dopant is a boron ion to form the complex light-doped or moderately-doped ρ co-diffusion region 3 0 7a. It is worth mentioning here that the multiple mask photoresistor 3, (b) -1 can be a solid reverse tone of the same mask of the multiple mask photoresistor PR3 (a) -1. It is worth emphasizing here that the complex photoresist PR3 (b)-1 can be omitted. If the common source region and the common drain region are simultaneously implanted with the $ 2 ^ conductive type dopant to form the second conductive type The shallow and highly doped common source and / or diffusion regions 306b / 307b are shown in FIG. FIG. 3D shows that the multiple mask photoresist pR3 (b is removed, and then the semiconductor substrate 3 0 0 is implanted with dopants in the active 2 across the penetrating dielectric layer 301 a in a self-aligned manner. The second conductive type is formed with a shallow and highly doped common source / non-diffused region 3 006b / 3 0 7b in the second / first conductive type with a lightly-doped common source / moderately doped common drain region. Within 306 a / 307 a. Figure IIID should not penetrate the dielectric layer. 3 0 1 a is removed by dilute hydrofluoric acid bubble immersion method or non-isotropic dry worming method, and the second protrusion The field oxide layer 3 0 4c is also etched by I to form a third protruding field oxide layer 3 04d; then a first side wall dielectric pad 3 0 a is formed in each of the gate stack regions. A side wall and a part of the surface of the first / second flat bed of each of the plurality of common source / drain regions, and then a planarized second conductive layer 3 0 9a is formed on the first side Over the first / second flat bed between 3.08a of side wall dielectric cushion

Page 13 V. Description of the invention (10) __. The first / second flat bed is composed of one thin layer, one shallow high doped layer, and one / two second protruding field oxide layers 3 0 4 d. The first side wall; 'electric pad layer area 3 ° 6V 30? B alternately composed LPCVD method to pile up, is first piled up 8a is composed of silicon dioxide and uses the structured surface and then etch back A film of sintered silicon dioxide is obtained at a depth of the formed junction. Weiping: U-Si film 3 08 thickness of silicon and using LprVn & Seventh Brother-conductive layer 309a is doped with polycrystalline electrical film 3 0 9 to fill the f = thick one second The gap is then CMP method will be used to empty the space between the stacked first side wall wall layer and the second cover screen 介 β-conductive film 30 9 to planarize and cover: '电 层 30 5_ 为— A smooth stop layer. Greater than; ΐ does not / planarize the second conductive layer 30 9a to etch back a depth of a few electrical layers to a depth of 3 cores, and then performs ion implantation to highly doped etched semi-^^; a metal oxide (Not shown) can be formed on the second conductive layer 3913 by a well-known Self-allgned SlUeidatiQn process, and the metallization layer is silicified to refractory metal. Materials such as cobalt silicide (coSi2) or titanium (TiSiJ); the metal petroxide layer can also be stacked with a & tungsten (WSl 2) layer, and then planarized and then etched back to form Phase =, a metal layer such as tungsten can be formed on the etched-back planarized second p layer 3 0 9 b. The method is to first deposit a tungsten layer, then add a soft layer f and then etch back. The composite second conductive layer includes a gold layer or a metal layer as a common source / drain conductive line and is also marked with M 9b.

561591 V. Description of the invention (11), two E (b) displays a plurality of mask photoresistors pR3 (a) -2 (not shown) formed on the surface of the complex common area and a part of the adjacent gate stack area Up, and then, the touch process is performed to etch the planarized first conductive layer located in each of the plurality of common source regions to form an etched-back planarized second conductive layer 3 0 9b ^ and then divide the complex number The mask photoresist pR3 (a) -2 was subjected to an ion implantation process to dope the planarized second conductive layer 3 0 9 a and the etched-back planarized second conductive layer 3 9 9 b. Similarly, a metal silicide layer (not shown) can also be formed on the planarized second conductive layer 309a and the planarized second conductive layer 301 by the well-known automatic alignment silicidation process) A layer of tungsten or metal tungsten is selectively formed on the etched-back planarized second conductive layer 309b. It is worth mentioning here that the multiple mask photoresist PR3 (a)-2 can be formed using the same mask used in the multiple mask photoresist PR3 (a) -1. FIG. 2F (a) shows that a planarized thick silicon dioxide layer 3 1 0a is formed on each of the common source / drain conductive lines 3 09b, and then is selectively selected using a high-temperature phosphoric acid or an anisotropic dry etching method. The second mask dielectric layer 3005a is removed from the ground, and then a second side wall dielectric cushion layer 3 丨 a is formed on each inner side wall of the first side wall dielectric layer 308a. It is placed on a part of the flat surface alternately formed by the first protruding field oxide layer 3 0 4b and the first conductive layer 30 2b. The planarized thick silicon dioxide layer 3 丨 〇a is composed of silicon dioxide, phosphor glass (P-glass), or borophospho glass (Bp_gUss) and is deposited using HDPCVD or PECVD. A thick dioxide is first deposited. A silicon film is used to fill the gap between the first side wall dielectric pads 308a, and then planarized by the CMP method, and the second mask dielectric layer 305a is used as a

561591 V. Description of the invention (12) Smooth the stop layer. The second side wall dielectric pad layer 3 1 1 a is composed of silicon nitride and is deposited by LPCVD. A second dielectric layer 31 1 is deposited on the formed structure and then etched back. The second dielectric layer 311 is formed in thickness. FIG. 3F (b) shows that a planarized thick silicon dioxide layer 3 1 0 a is formed on each of the common source conductive lines 3 0 9 b, and then is selectively selected using high-temperature phosphoric acid or anisotropic dry etching. The second mask dielectric layer 3 0 a is removed, and then a second side wall dielectric pad layer 3 1 1 a is formed in each of the first side wall dielectric pad layer 3 0 8 a Above the side wall and on a part of a flat surface composed alternately of the first protruding field oxide layer 304b and the first conductive layer 302b. FIG. 3G (a) shows that the first conductive layer 3 0 2 b located between the second side wall dielectric pad 3 1 1 a is etched back to form a thin floating gate layer in the middle portion. Then, dopants are implanted across the thinner floating gate layer in an automatic alignment manner to form an ion implantation region 3 1 2 a of the first conductivity type under each floating gate structure 3 2 c. The thickness of the thinner floating gate is between 200 angstroms and 500 angstroms. The ion implantation area 3 1 2 a includes at least one shallow ion implantation area as indicated by a dashed line as an adjustment of the threshold voltage and a deeper ion implantation area as indicated by a number X X X to form a resistance-prohibited area. Figure 3G (b) shows that a plurality of mask photoresistors PR4 (not shown) are formed on the common drain region and the dielectric pad layer 3 1 1 a adjacent to the second side wall, and then located on the second side The first conductive layer 3 0 2b between the wall dielectric pads 3 1 1 a is etched back to form a thin floating gate layer in the middle portion, and then dopants are implanted to form an ion implanted region 3 1 2 a as described in G (a) of Figure 3, and then remove the complex number

561591 V. Description of the invention (13) Mask photoresistor PR4. It is worth mentioning here that if a thin thermal polycrystalite oxide layer is formed on the planarized second conductive layer 309a in FIG. 3D, or as shown in FIG. Above the planarized second conductive layer 309a after the oxidized stone layer 310a, the plurality of mask photoresist PR4 may be omitted. It can be clearly seen from FIG. 3G (a) and FIG. 3G (b) that the width of the ion implantation region 3 1 2a can be borrowed from the cushion thickness of the second side wall dielectric cushion layer 3 丨 丨 a = To control, and the electric field distribution can also be controlled relatively. ^ Wide, a large tilt-angle ion implantation (not shown) can also be used to form an anti-forbidden zone and adjust at the same time. Sink the electric field. It is shown in FIG. 3H (a) that the second side wall dielectric cushion layer 3 丨 丨 a is removed, and then an inter gate dielectric is placed on the structure formed by 3n cows. Then a flattening day 3 T was formed on each of the == sluice stacks. The inter-gate dielectric "70% dielectric layer such as _dioxo_nitrogen_dioxy system-a complex :: a nitride stone _ dioxide dioxide (Noc) structure system between 80 Angstroms and 12 The thickness of emulsified silicon is doped with polycrystalline silicon. Λ μ A conductive layer 3 1 4a is formed by Θ flutes and stacked using LPCVD method. Department of Secret # ΪμΙ 二 膜 314 来Every ~ 2 of the gate stack area is filled with a CMP method to add ^^ J ^ void reuse layers. Surface and use the inter-gate dielectric layer 313 as ~ smoothing stop 314a ^ I (b) shows the flat two-colored flute shown in Figure III. H (a) -Dordi di 4a series | worm—a second conductive layer called ^ tk u, number / woodiness' and then a metal silicide Μ, Soil ㈤- 314b. These two are formed in the etched-back pingxihuan third conductive absorptive value. It is noted that the steps of an ionization layer can be the same

Page 17 561591 5. In the description of the invention (14), a high-dose dopant for implanting the second conductivity type is used in the planarized second conductive layer 309a and the etched-back planarized third conductive layer 314b. It is worth emphasizing that a planarized metal layer can be formed on the etched-back planarized third conductive layer 3 1 4b and then etched back to form a composite control gate conductive layer in each of the gate stack regions Above. FIG. 3 I (a) shows that a metal layer 3 1 6 is formed on the entire structure and is formed by aligning the mask layer with the active area through a mask step; and the metal layer 316 and the planarized third The conductive layer 31 4a is simultaneously etched to form a plurality of metal word lines 3 1 6a and a plurality of planarization control gate conductive islands 3 丨 4b are integrated to form a contactless parallel common source / drain bit line flash of the present invention. Memory array. The masking step may be a plurality of masking photoresistors or a plurality of hard masking dielectric layers 317a aligned on the plurality of active regions and a side wall dielectric layer 318a formed on the plurality of hard masking dielectric layers. Each side wall of the 317a eliminates misal ignmemt. It is worth mentioning here that 'the planarized third conductive layer 3 丨 4 a is silicidated with a high temperature resistant metal petroxide layer' and the metal layer is an aluminum or copper layer placed on a barrier-metal A layer such as a titanium nitride (TiN) or nitride button (TaN) layer. FIG. 2I (b) shows that a planarized silicon dioxide layer 315a is formed on each of the composite control gate conductive layers 314b, and a metal layer 3 1 6 is formed on the formed structure.丨 a mask step described in (a) to form the metal layer and the planarized second conductive layer 3 0 9a at the same time to form a plurality of metal bit lines 3 丨 6 a and the planarized second Conductive islands are integrated to form a contactless non-or flash

Page 18 561591 V. Description of the invention (15) Memory array. It is worth mentioning here that the inter-gate dielectric layer 3 1 3 placed on the planarized thick silicon dioxide layer 310a and the planarized second conductive layer 309a is removed by the CMP method and is located The thin thermal polycrystalline silicon oxide layer on each of the planarized second conductive layers 309a is also removed; the exposed planarized second conductive layer 3 0a is coated before the metal layer 3 16 is formed. Silicide to form a high temperature resistant metal silicide layer on top of it. Similarly, the metal layer includes at least one aluminum or copper layer formed on a barrier metal layer such as a titanium nitride (TiN) or nitride button (TaN) layer. FIG. 4 shows a top-view layout diagram of the contactless parallel common source / drain conductive bit line flash memory array described in FIG. 3 I (a), wherein a cross-sectional view along the AA ′ line is shown in FIG. Three I (a). It can be clearly seen from FIG. 4 that the complex common source conductive bit line (CSBL, s) and the complex common drain conductive bit line (CDBL's) are formed in parallel and parallel to the complex shallow groove isolation region (STI 1 ines) are perpendicular to each other; and the plurality of metal word lines (WL, s) are integrated with the plurality of planarization control gate conductive islands 3 1 4b and are connected to the plurality of common source / drain conductive bit lines (CSBL , S / CDBL, s) are perpendicular to each other. FIG. 5 shows a top-view layout diagram of the non-contact non-OR flash memory array described in FIG. 3 I (b), and a cross-sectional view taken along line A-A ′ is shown in FIG. 3 I (b) Show. According to FIG. 5, it can be clearly seen that the plurality of common source conductive lines (CSBL's) are alternately formed and are perpendicular to the plurality of parallel shallow groove isolation regions (STI 1 ines); and the plurality of metal bits The line (bl, s) and the planarized common drain conductive island 3 0c are simultaneously formed and aligned on the complex active area (AA's) and mutually interact with the complex common source conductive pipeline (CSBl, s). vertical. As can be clearly seen from Figures 4 and 5, the size system of a cell

Page 19 561591 V. Description of the invention (16) is equal to 4 F 2 as indicated by the dotted square. Based on this, the advantages and characteristics of a flash memory cell structure of a stack gate of the present invention and its non-contact flash memory array are summarized as follows: (a) A flash memory cell structure of a stack gate of the present invention provides A floating gate structure with a thin floating gate layer formed in the middle portion to form an intermediate portion of a channel that efficiently penetrates the forbidden area in a miniature stack gate flash memory cell. (b) A stacked gate flash memory cell structure of the present invention provides a floating gate structure with a large surface area to increase the ratio of micronized flash memory cells (c 0 p 1 i n g r a t i 0). (c) A flash memory cell structure of the stack gate of the present invention provides a cell size of 4F and can be miniaturized without causing a puncture effect and without contact problems on the shallow source / drain interface. (d) A contactless parallel common source / drain conductive bit line flash memory array of the present invention provides high conductive bit lines and metal word lines to improve the read speed of a high density flash memory array. (e) A non-contact non-or-type flash memory array of the present invention provides a high-conductivity common source pipeline, a high-conductivity word line, and a metal bit line to improve the readout speed of a high-density flash memory array.

Page 20 561591 V. Explanation of the invention (17) Although the present invention is illustrated and described with reference to the attached examples or connotations, it is only a statement rather than a limitation. Moreover, the present invention is not limited to the details listed, and those skilled in the art can also understand that changes of various shapes or details can be made without departing from the true spirit and scope of the present invention, but still belong to the present invention. The category of invention.

References US Patent 4, 698, 787 10/1987 Mukherjee 5, 654, 917 8/1997 Ogura et a 1. 5, 918, 141 6/1999 Merrill 6, 221, 012 B1 4/2001 Lee et a 1. 6, 221, 0 2 0 B1 4/2001 Tripsas et a 1 6,221,718 B1 4/2001 Hong 6,215,145 B1 4/2001 Noble 6, 2 77, 6 9 3 B1 8/2001 Chen

Page 561591 Brief description of the drawings Figures A and B show a schematic cross-sectional view of a stack gate flash memory cell in the prior art, of which Figure 1A shows a stack with an asymmetric source / drain diffusion structure A schematic cross-sectional view of a gate flash memory cell and FIG. 1B shows a schematic cross-section view of a stacked gate flash memory cell with a symmetrical source / diffusion structure. Figures 2A to 2F show the manufacturing steps and cross-sectional views of a shallow groove isolation structure for fabricating a stack gate flash memory cell structure and a contactless flash memory array of the present invention. FIGS. 3A to 3I show the manufacturing steps and cross-sectional views of a stacked gate flash memory cell structure and a contactless flash memory array according to the present invention. FIG. 3E (a) and FIG. 3F (a), FIG. 3G (a), FIG. 3H (a), and FIG. 3I (a) are connected to FIG. 3D to manufacture a contactless parallel common source / drain conductive bit line flash memory array of the present invention Process steps and cross-sectional views thereof; FIG. 3 E (b), FIG. 3 F (b), FIG. 3 G (b), FIG. 3 H (b), and FIG. 3 1 (b) are subsequent to FIG. 3D to manufacture the present invention Process steps and cross-sectional views of a non-contact non-or type flash memory array. Figure 4 discloses a top-view layout diagram of a contactless parallel common source / drain bit line flash memory array according to the present invention. FIG. 5 illustrates a top-view layout diagram of a contactless NOR-type flash memory array according to the present invention.

Claims (1)

561591 VI. Application Patent Scope 1. A stacked flash memory cell including at least: a semiconductor substrate of a first conductivity type; a cell region having an active region and two parallel shallow groove isolation (STI) A region is formed on the semiconductor substrate and is divided into two regions: a common source region, a gate stack region, and a common dip region. The gate stack region has a gate stack system located in the common source region. And the common drain region; a common source diffusion region of a second conductivity type is formed by automatically implanting dopants in the semiconductor substrate of the active region of the common source region; and a first The flat bed is composed of the common source diffusion region and an oxide layer adjacent to the third protruding field, and a first side wall dielectric cushion layer is formed on a side wall of the gate stack in the gate stack region. On a portion of the surface of the first flat bed; a common source conductive layer is formed on the first flat bed outside the first side wall dielectric pad layer and a planarized thick silicon dioxide layer Formed on the common source conductive layer and the A dielectric layer on the first side wall; a common-drain diffusion region formed by automatically implanting dopants into the semiconductor substrate of the active region of the common region; and a second flat bed Consisting of the common drain diffusion region and the adjacent third protruding field oxide layer and the first side wall dielectric cushion layer formed on the other side wall of the gate stack in the gate stack region Over a part of the surface of the second flat bed; a common drain layer is formed on the second flat bed outside the first side wall dielectric pad layer and the planarized thick silicon dioxide layer Formed Page 23 561591 VI. Patent application scope The conductive layer and the first side wall dielectric cushion layer; a floating gate structure is formed on a penetrating dielectric layer and a thin floating gate layer is located on the gate A middle portion of the active region of the stacking region, one of the first conductivity type ion implantation regions is formed in a middle portion of a channel and is placed under the thin floating gate layer and two first A protruding field oxide layer is respectively located in the two parallel shallow groove isolation regions within the gate stack region; an inter-gate dielectric layer is formed at least in the floating gate structure, the two gate gate regions in the gate stack region A first protruding field oxide layer, and on each inner side wall of the first side wall dielectric pad; and a metal word line is integrated and aligned with a planarized control gate conductive island Simultaneously forming in the active area, wherein the conductive island system of the planarization control gate is formed on the inter-gate dielectric layer. 2. The stacked gate flash memory cell as described in item 1 of the scope of the patent application, wherein the above-mentioned co-source diffusion region includes at least a shallow highly doped diffusion region formed in a lightly doped diffusion region. 3. The stacked gate flash memory cell as described in item 1 of the scope of the patent application, wherein the common drain region includes at least one shallowly doped diffusion region of the second conductivity type or one second conductivity type. The shallowly doped diffusion region is formed in a moderately doped diffusion region of the first conductivity type. 4. The stacked gate flash memory cell as described in item 1 of the scope of patent application, Page 24 561591 6. Scope of patent application The above-mentioned thin floating gate layer is defined by a pair of second side wall dielectric barrier layers formed on the inner side wall of the gate stack area. Fan Wei specially asked Shen Ru to plant the scintillator M in a small area for the Yuan Zuo cells, and the shoal piled up a stack of the contents of the package to the upper part of the area. It is formed one by one to plant the cloth deeper than the one and the same piezoelectricity. Fan Li, who is in the bounds of the boundary zone, please refer to the description of the control plane in the middle 6. The compound cells of the wafer are mixed with the memory, the memory is high, the flash is fast, the gate is included, and the stack is less stacked. The gate 11 is controlled or covered with island silicon. The crystal layer complex is doped with silicon, which is high in gold, high temperature, or high in silicon. 7. The stacked gate flash memory cell as described in the first patent application scope, wherein the above-mentioned co-source / drain conductive layer At least one highly doped polycrystalline silicon layer or one highly doped polycrystalline silicon layer is covered or silicided with a high temperature resistant metal silicide layer. 8. The stacked gate flash memory cell as described in item 1 of the scope of patent application, wherein the metal word line includes at least one aluminum or copper layer formed on one barrier metal layer. 9. A stacked gate flash memory cell, comprising at least: a semiconductor substrate of a first conductivity type; Page 25 561591 VI. The scope of the patent application is one recess and one recess from the source compartment: two or three of the flat area of the row area and the main area of the moving area are divided into two. The stacking area of the forming area is described in the above. The areas and areas in the above area are all in common. This area and the total area are all connected to each other. The ill · JL stack is stacked Hfl 0¾ 0Π ΘΠ one by one. The internal standard plate from the square shape to the base body self-guided borrows the expansion of the scattered areas of the original region ^ ,, 4 ^ «3. There are a total of one of the region-type source conductors of the one and the second one. The seed mixed with the implanted cloth forms an oxygen field that emerges from the third nearest neighbor and the area of the diffused source. The bed should be flat. The first stack of sluice beds should be flat and the first layer should be placed on the wall. The upper side of the side wall is stacked one by one on the side of the gate layer. The outer layer of the materialized area is the outer layer of the dielectric wall. The side of the dielectric wall is on the forming layer. A part of the table should be silicified on the forming layer; The thickness of the second layer is between the first bed on one side and the side of the wall, the first bed, the second bed, the first bed, and the first bed. The source should be mixed with the quality; the inner standard plate from the pattern is moved to the base. The self-guided extension of the half-zone and the scattered expansion zone did not move the stacking bed of the first field of the Jichang heap, and the third gate of the flat was nearly adjacent to the second, and the layer was electrically connected to the pad. The side wall of the pumping wall on the expanded wall is distributed on the side by a first bed, a flat bed, and another two stacks, and a stack of gates is formed. The first part should be flat to the surface of the conductivity, and the first part should be a flat part. There is a layered area with a middle and an upper one. The electric medium mainly penetrates the area that should be worn; The gated area is formed by the scattered floating gates at the expansion level, the co-floating gate, the floating species, and a relatively thin layer. Page 26 561591 6. The scope of the patent application is the first one, two, and a square lower system. The area of the plant gate cloth float floats away from the thin competition. The part of the department is one of the two, and the compartment grooves are shallow and flat. The two should be layered and physicalized. The gates should be floating. The stacking gate should be located in the forming layer. The fields are stacked one by one, and the area inside the dielectric layer is side by side, and the layers are materialized; the side of the field where the oxygen is out of the wall is one by one, one by one, and the layers are silicified oxygen. The second layer is covered with a layer, the upper layer of the upper layer is electrically insulated, and the interlayer cover is overlaid with the layer of the electric field guide stack gate. The gate is gated on a common surface of the conductive island of the volume island. The flat shape should be the same as the timeline, and the main one should be in quasi-oppositional diffusion U source expansion V: f 4 last 2 2 1 It is in the scattered area of the surrounding area, and the elementary cell area is scattered. Enlarging the description of stray flash mixed with fast high-gate shallow stacks is rare. Item to inner 9 ❿ If the compound of the green youth I i is applied, it is doped with medium or high element, or the layered cells are finely silicified. The crystal is remembered as a flash gold fast doped with high temperature and high resistance. Contains less silicon terminology of the encapsulation, or 9 layers of capped electrically conductive layer f eutectic, and a thin type electromechanical guide flash of the ancient interstellar cell, the second and third gates of the stack contain as few as The description of the expansion and expansion of the Communist Party of the People's Republic of China is described in the above. Diffuse diffused heteroconductors doped with shallow areas of the inner high doped with the second type of the first type or the conductive region is diffused and the doped ones are diffused with the first page 27561591 6. Application for patent scope 1 3. If applied The stacked gate flash memory cell described in item 9 of the patent scope, wherein the above-mentioned planarized common drain conductive island includes at least one highly doped polycrystalline silicon island or a highly doped polycrystalline silicon island covered or silicified with one High temperature resistant metal silicide layer. 14. The flash memory cell of stacked gates as described in item 9 of the scope of patent application, wherein the thinner floating gate layer is formed in the gate stack region by a pair of second side wall dielectric cushion layers. To define on the inside side wall. 15. The stacked gate flash memory cell as described in item 9 of the scope of the patent application, wherein the above-mentioned ion implantation area includes at least one shallow ion implantation area for the adjustment of the threshold voltage and a deeper ion implantation. Zone to form a forbidden zone. 16. The stacked gate flash memory cell as described in item 9 of the scope of the patent application, wherein the conductive gate control layer as a word line includes at least one highly doped polycrystalline silicon layer to cover or silicide with a high temperature resistance A metal silicide layer or a highly doped polycrystalline silicon layer is covered with a metal layer. 1 7. A contactless flash memory array, comprising at least: a semiconductor substrate of a first conductivity type; a shallow groove isolation structure having a plurality of active regions and a plurality of parallel shallow groove isolation regions alternately formed on the semiconductor substrate; On a semiconductor substrate; Page 28 561591 6. The scope of the patent application The complex gate stack area is formed between the common source area and the complex draw area, wherein the aforementioned complex gate stack area is formed on the shallow groove isolation structure and is connected with the The plurality of parallel shallow groove isolation regions are perpendicular to each other; each of the plurality of common source regions includes at least: a first flat bed consisting of a common source diffusion region of a second conductivity type having a double diffusion structure and a third protrusion The field oxide layer is composed alternately. A pair of first side wall dielectric pads are formed on each side wall adjacent to the gate stack and placed on a portion of the surface of the first flat bed. A common source conductive bit line is formed on the first flat bed between the pair of first side wall dielectric pads, and a planarized thick silicon dioxide layer is formed on the first side wall Above the common source conductive bit line between the dielectric rhenium layers; each of the plurality of common drain regions includes at least: a second flat bed intersected by a common drain diffusion region and the third protruding field oxide layer Variable ground composition, another pair of first side wall dielectrics A layer is formed on the other side wall adjacent to the gate stack and on a part of the surface of the second flat bed, and a common drain bit line is formed on the other pair of first side wall On the second flat bed between the electric pads, and the planarized thick silicon dioxide layer is formed on the common drain bit line between the other pair of first side wall dielectric pads ; Each of the plurality of gate stack areas includes at least: a floating gate structure disposed on a penetrating dielectric layer of each of the plurality of active regions and having a thinner floating gate layer in a middle portion, a A first protruding field oxide layer is located within each of the plurality of parallel shallow groove isolation regions. A first ion implantation region of the first conductivity type includes a shallow ion implantation region as a threshold voltage adjustment and a deeper one. Ion implants the area to form a barrier Page 29 561591 VI. The patent application scope stop zone is formed in a middle part of one channel in each of the plural active zones, and an inter-gate dielectric layer is formed at least in the plural floating gate structures. The plural first Protruding over the field oxide layer, and the conductive islands of the plurality of planarization control gates sandwich the dielectric layer formed on the plurality of floating gate structures: and a plurality of metal word lines and the conductive islands of the plurality of planarization control gates The connection and alignment are simultaneously formed on the plurality of active regions. 1 8. The contactless flash memory array as described in item 17 of the scope of the patent application, wherein the common-drain diffusion region includes at least one shallowly doped diffusion region of the second conductivity type or one second conduction region. A shallowly doped diffusion region of the type is formed in a moderately doped diffusion region of the first conductivity type. 1 9. A contactless flash memory array, comprising at least: a semiconductor substrate of a first conductivity type; a shallow groove isolation structure having a plurality of active regions and a plurality of parallel shallow groove isolation regions alternately formed on the semiconductor Above the substrate A plurality of gate stack regions are formed between a plurality of common source regions and a plurality of common drain regions, wherein the plurality of gate stack regions are formed on the shallow groove isolation structure and are parallel to the plurality of parallel shallow groove isolation regions. Vertical; each of the plurality of common source regions includes at least: a first flat bed consisting of a common source diffusion region of a second conductivity type having a double diffusion structure and a third protruding field oxide layer alternately A pair of first side wall dielectric pads are formed on each side wall adjacent to the gate stack and placed on Page 30 561591 6. Scope of patent application On a part of the surface of the first flat bed, a common source conductive pipeline is formed on the first flat bed between the pair of first side wall dielectric pads. And a planarized thick dioxide layer is formed on the common source conductive pipeline between the pair of first side wall dielectric cushion layers; Each of the plurality of common drain regions includes at least a second flat bed composed of a common drain diffusion region and the third protruding field oxide layer alternately formed, and another pair of first side wall dielectric cushion layers Formed on the other side wall adjacent to the gate stack and placed on a portion of the surface of the second flat bed, and a plurality of planarized common drain conductive islands formed at least on the other pair of first side walls Over the common-drain diffusion region between the dielectric pads; Each of the plurality of gate stack regions includes at least: a floating gate structure disposed on a penetrating dielectric layer of each of the plurality of active regions and having a thinner floating gate layer in a middle portion, a first A protruding field oxide layer is located within each of the plurality of parallel shallow groove isolation regions. An ion implantation region of the first conductivity type includes a shallow ion implantation region as a threshold voltage adjustment and a deeper ion. An area is planted to form a forbidden area formed at a middle portion of a channel in each of the plurality of active areas, and an inter-gate dielectric layer is formed at least on the plurality of floating gate structures and the plurality of first protruding fields. An oxide layer, an extension control gate conductive layer is formed as a word line on the inter-gate dielectric layer, and a planarized silicon dioxide layer is formed over the extension control gate conductive layer; and a plurality of The metal bit lines are connected to the plurality of planarization and collective conductive islands and are aligned on the plurality of active regions to be simultaneously formed. Page 31 561591 VI. Patent application scope 20. The non-contact flash memory array as described in item 19 of the patent application scope, wherein the above-mentioned common-diffusion diffusion region includes at least one shallow-doped doped second conductivity type. The hetero-diffusion region or a shallow highly doped diffusion region of the second conductivity type is formed within a moderately doped diffusion region of the first conductivity type. Page 32