TW541690B - Scalable multi-bit flash memory cell and its memory array - Google Patents

Abstract

A scalable multi-bit flash memory cell consists of three regions, first sidewall region, gate region and second sidewall region, wherein the gate region comprises two stacked gate transistors and a selecting transistor between them. The first/second sidewall region comprises a sidewall oxide pad layer formed at the gate region, and from top to bottom a planar thick oxide layer, a silicide conduction layer on the planarized bed between a pair of sidewall dielectric pad layers, and a common diffusion area. The stacked gate transistor comprises a sidewall pad layer, an extended control gate on the inter-gate dielectric layers and an integrated floating gate from top to bottom. The selecting transistor comprises a planar conduction island on the gate dielectric layer and connects a word line. The memory array is made by arranging the memory cell in a variable way.

Description

541690 V. Description of the invention (1) Background of the invention: (1) Scope of the invention The present invention relates to general flash memory cells and their memory cell arrays, especially to a miniaturizable multi-bit flash memory cell and its Related to memory cell array. (2) Description of learned skills

Basically, a flash memory element can be divided into two categories: a stacked gate type (37 7 8 ^ 2316) structure and a split gate type (31) 1 丨 1: 131; 6) structure. A stacked gate structure is well known as a cell of an transistor, where the gate length can be defined using the minimum line width of the technology used (mi n i m u m f e a t u r e s z z e F). However, a split gate structure includes a floating gate and a selective gate, which are well-known as a cell of a 5-cell transistor. Therefore, stacked gate structures are often used in high-density flash memory systems. The stacked gate structure can use a common source / drain diffusion region and a series connection to form a high-density NAND-type array. However, a non-harmonic array

Resistance relationship 'its data access speed is slower. Dancha, a non-harmonic type 歹 J series uses Fowler-Nordheim penetrating to write, g this writing speed is slower. The split-gate structure has a selective gate to avoid the problem of rubbing (〇ver-erasing), and generally forms a non-or type (ν (method two f :: electron injection (h〇t-electron in ject ion); 2 Obtained the South Speed Write & Based on this, the use of stacked idle and partitioned, individual advantages to form a flash memory cell became a major test

541690 V. Description of the invention (2) Development trend, of which a typical example disclosed in U.S. Patent No. 5,3 6,4,806 is shown in Figure 1. Referring to FIG. 1A, two of the selection gates 2 4 G are separated, and a top view is placed as a bit line system on each one, as shown in FIG. 1B. The stacked gate structure has two N + / N stacks. A display of the stack gate structure, where as a

2 0 G and 2 2 G use diffusion lines of 20 A and 2 2 A sides. Figure 1 A A polycrystalline silicon layer 28 is placed on top of N + / 2 0 C and 2 2 C. According to the needs of four mask photoresistive steps, 4F2, compared with the non-harmonic array that is available with stacked gate junctions, select the miscellaneous between the gate line (word line) and bit line word line) and the control gate line. Poor isolation; and adjacent bits, severely, bad word line separations present incorrect data. Therefore, a multibit that can be miniaturized according to the present invention is another object of the present invention to memorize a shallow one required for a cell array. A better density and speed required for a further object of the present invention. Other objects of the present invention and

Diffusion line 20A Figure 1A and Figure 1B choose 22A and make this cell ruler, and a non-harmonic type of each bit structure is equivalent. The structure of FIG. 1A still shows that the stray capacitance is too large; the selective capacitance is too large; the isolation between the adjacent word line element line and the adjacent word line will cause the third control gate line element of the selected cell gate to be at least Limited, however, with some disadvantages: The gate line is too weak. The readout purpose is to provide a cell size smaller than 4F 2 flash memory cells. It is to provide a high-density multi-bit flash memory. The slot isolation structure is to provide a multi-bit flash memory array • power product. The advantages will be more significant from the description below. ❿

Page 5 541690 V. Description of the invention Summary of the invention The memory array of the present invention can be divided into middle gate zoning. The gate area lies between two two-sided areas (3) It will not be revealed. The two areas of the hair pass through a one-to-one clear field: the first mask is in the gate area, and the transistor contains silicon oxide to form at least a part of the flat layer. The worm includes at least one side of the stack gate. Outside the second layer of the wall, a top-down compound layer, and each electric pad layer placed in a co-diffusion area and stacked gate transistors are integrated, and a thin penetrating dielectric field oxide dielectric layer is formed. Place on the inner side wall surface. And placed under the two gate areas, the sub-planting area forms one of the impeding layers on the plane, and a semiconducting system intervening with a flat stack is used to forbid the area to control the gate layer. The upper part of the layer is thickly oxygenated. Two surface-guiding gate-type electrical substrate adjustment pads can be adjusted. One micro-miniaturized seed can be micro-opposed on one side of the photoresist step and the other on the side of the gate. The multi-level reduction zone of the electric island system on the main drift surface of the inner stack is located on the main drift surface. The side wall for the partial selection is located on the plane of the lead-out field and is lower than the integrated floating gate. Snapshot multi-bit fast-gate region and Dijiao define two stacked gate-selected transistors and placed on one side to thicken the oxide layer. A gate between crystals forms at least one gate floating layer and a stack of stacked crystal strips, and a deep material layer including the interlayer gate layer floats between the stacking gates and lines in the same layer. Memory on both sides, so brake electric body. The second part is a flat-walled dioxygen layer, a flat element and its cell region, which can be scaled crystals and a silicon bed on a silicon bed. The two side walls are connected to each other, and include a boundary voltage, the bit line includes at least one electrical layer, and at least is enclosed by a protruded gate layer. A gate transistor and one of its semiconductors are formed and etched, of which, in the selection, a shallow implantation area is used to place the metal layer in the gate

Page 6 541690 V. Description of the invention The dielectric layer and the upper and side walls are layered and electrically conductive. The grooves of the present invention isolate the space between them, which protrude the field oxygen through the dielectric layer substrate and form a line area. (4) A flat A complex number which is hardly placed on the island 0 surface conductive island mask metal layer can be reduced by one more. A scaleable flash region is formed in a semiconductor. A complex compound layer is formed with a plurality between and between each. One side and one stack gate area on each side of an extended bulk drift layer and two parts of the surface side wall of the bed. One layer contains a layer placed on an etch flat to control the protrusion At least one extension surface of the floating gate layer. Part of the surface of the electric pad is flattened out to be parallel and semi-parallel. A plurality of gates are selected by placing the gate layer on the shallow groove number of the active conductor base, and the gate region of the shallow groove number is formed on the gate selection region and is formed between the gates and interposed between two stacked gate types including a mask dielectric layer and To form and etch the mother board of the metal bit fast memory fine substrate isolation region. Each of the flash memory cell arrays in the isolation zone has a plurality of gates that are perpendicular to each other, including two stacks, and at least one inter-gate dielectric layer. The complex contains a main floating layer placed on a surface of each of the floating gates separately from each of the floating gates located adjacent to the spur area, and the silicide is formed on the side wall and the side wall of the thick oxide layer. On the bed. A flat bed consists of alternating layers. A row of gate dielectric cells. Plural main areas include at least a few inclusive areas to form a straight line, while a few layers of thin out-of-field oxygen are deposited on the side wall layers of the two overlap areas, and at least the dielectric layer and the ground layer are intersected by the co-layer system. In between, its two side layers and the plane are arranged in a number of parallel shallow motion regions interposed between one by one through the semiconductor multiple bit stack gate region. Two dielectric pads, and a plurality of floating gates, a dielectric layer, a layer of a pair of at least one conductive out-of-plane diffusion region and a ground

Page 7 541690 V. Description of the invention (5) The area and its inner side wall, so that a plurality of planar conductive islands are above the gate of the stack gate section and the extension control strip contains at least one metal, and one A hard cover-side dielectric pad is formed on the plurality of planarized conductive islands. Element flash memory cells and color: conductive cell lines of micronizable cells; no isolation; and placed on the complex layer than the prior art and selective gates. The gate lines are layered on each other, and the dimensions of the memory array elements are placed on the gate curtain layer, including the metal layer. The contact problem is better than the planar guide layer of the plural main digital lines and the advantages and capacitances of the metal scaleable columns in two moments Good fine power product on the side of the electric island and multiple bits of special South cell flattened thick oxide layer on the surface of the semiconductor substrate of the stacked gate area. A complex number of each gate area The line system is placed vertically in the plurality of active areas, in which each dielectric layer of the plurality of digital lines and a plurality of mask dielectrics are formed and etched. The column of the present invention can provide a shallow diffusion region with lower bit line electricity; density · speed · Drawing number comparison explanation Φ 100 semiconductor substrate 102 first conductive layer 10 4a planarized field oxide layer 104c protruding field oxide layer 1 0 6 a first side wall dielectric pad layer 108 third conductive layer 1 1 0 a The doped co-diffusion region 112a planarizes the fourth conductive layer 101, the thin penetrating dielectric layer 103, the first mask dielectric layer 1 0b, the flat field oxide layer 105a, and the second conductive layer 107. The inter-gate dielectric Layer 109 second mask dielectric Layer 1 1 1 aSecond sidewall dielectric pad 1 1 3 bSilicide layer

Page 8 541690 V. Description of the invention (6) 114a planarized thick oxide layer 1 1 6 a ion implanted area 118 gate dielectric layer 1 2 0 a metal layer 1 2 2 a fourth side wall dielectric cushion layer 1 1 5a Third side wall dielectric pad layer 1 17a Highly doped co-diffusion region 1 1 9a Planarized conductive island 121a Third dielectric layer Detailed description of the invention: Referring now to FIG. 2A, the present invention is disclosed A sectional view of a miniaturized multi-bit flash memory cell. As shown in FIG. 2A, a miniaturizable multi-bit flash memory cell can be divided into three regions: a first side region, a gate region, and a second side region. The gate region is located in the first side region and the second side region. Between the side regions' includes two abundant stack gate transistors, which are respectively formed on the two side portions of the gate region, and a selection gate transistor is between the two stacked gate transistors; the first side region and The second side area is a bit line area. Each of the two stacked gate transistors includes at least one side wall dielectric cushion layer 115b, an extended control gate layer 108a, an inter-gate dielectric layer 107b, an integrated floating gate layer, and A thin penetrating dielectric layer 1 0 1 c is formed on a semiconductor substrate 100 of a first conductivity type. The first / second side region includes at least one side wall dioxide cushion layer 1 1 1 b formed on one side wall of the gate region and includes at least one planarized thick oxide layer 114b and Shi Xi from top to bottom. The compound layer 113b and the conductive layer 112b are placed on a flat bed. This flat bed consists of a highly conductive doped diffusion region 1 1 7a of the second conductivity type formed in the lightly doped diffusion region 1 1 0 a of the second conductivity type and an etched flat field oxide layer 1 0 4 c. . An integrated floating gate system consists of a main floating gate layer

Page 9 541690 V. Description of the invention (7)

Above the dielectric layer 10 C and two extended floating gates 105 C are placed on a portion of the surface adjacent to each of the protruding field oxide layers. A gate dielectric layer 1 1 8 is placed on a planarized thick oxide layer 1 1 4b, two stacked gate transistors and their inner side walls, and a semiconductor surface between the two stacked gate transistors on. A planarized conductive island 119a is placed on the gate dielectric layer 10 8 between two Fengdui gate transistors and passes through the word line 120a at the same time. It includes a mask dielectric layer 1 2 1 a and two A hard cover curtain layer composed of a dielectric barrier layer 1 2 2 a on the side wall is formed and etched. An ion implantation region 1 1 6 a is formed on the semiconductor surface below the selective gate region. One of the shallow ion implantation regions (shown in dotted lines) is used for threshold voltage adjustment, and one of the deep ion implantation regions (marked X) (Shown) is used to form an anti-pass zone.

FIG. 2B illustrates a top view of a miniaturizable multi-bit flash memory cell array according to the present invention, wherein a plurality of parallel shallow groove isolation (ST I) regions are formed on a semiconductor substrate 100 of a first conductivity type and have a plurality of The active area is located between them; the complex gate area, as indicated by xF, is perpendicular to the complex parallel shallow groove isolation area, and is formed by a mask photoresist step with the complex bit (BL) area in between; the complex digital line (WL ) Is located above the plural active area and perpendicular to the plural bit line area. Each of the plurality of parallel shallow groove isolation regions includes at least one protruding field oxide layer 104b formed on the semiconductor substrate 100, and the plurality of active regions includes at least one thin penetrating dielectric layer 101a disposed on the semiconductor substrate 100. Each of the plurality of bit line regions includes at least a pair of side wall dielectric pads 1 1 1 b formed on the opposite side wall adjacent to the gate region and a part of the surface of a flat bed at least from top to bottom. Contains a planarized thick oxide layer 114b, a petrochemical layer and a conductive layer placed on a pair of side wall dielectric cushion layers 1 1 1 b of 541690 5. Description of the invention (8)

On a flat bed. The second co-diffusion region of the second conductivity type is formed in the semiconductor substrate 100 of the multiple active region of the multiple bit line region, and each flat bed is alternately composed of the co-diffusion region and the etched-out flat oxide layer. 1 0 4 C. Each of the plurality of co-diffusion regions includes at least one highly doped diffusion region 1 1 7 a formed in the lightly doped diffusion region 1 1 0 a. Each of the plurality of gate regions includes at least two stacked gate regions located on each side of the gate region and placed on the semiconductor substrate 100 and a selective gate region is located between the two stacked gate regions. Each of the two stacked gate regions includes at least one side wall dielectric pad layer 1 15b, an extended control gate layer 108b formed on a gate dielectric layer 107b, and Pluralized floating gates. Each of the plurality of integrated floating gate layers includes at least one main floating gate layer 1 0 2 c placed on a thin penetrating dielectric layer 1 0 1 c and two extended floating gate layers 1 0 5 c placed separately A portion of the surface adjacent to a pair of protruding field oxide layers 10 4 b. A gate dielectric layer 1 1 8 is alternately placed on the planarized thick oxide layer 11 4b, two stacked gate regions and their inner walls, and a semiconductor surface located between the two stacked gate regions, where two There is an ion implantation region 1 1 6 in the semiconductor substrate 100 of each stack gate interval. At least one shallow ion implantation region is used for threshold voltage adjustment and a deep ion implantation region is used to form a breakdown prohibited region. Use. Each of the plurality of digital lines includes at least one metal layer disposed on the gate dielectric layer 1 1 8 and the plurality of planarized conductive islands 1 1 9a formed in the selection gate region, wherein a hard mask layer includes a mask dielectric The layer 121 a and its two side wall dielectric pads 1 2 2 a are used to simultaneously form and etch the metal layer and the planarized conductive island 1 1 9 a to form an integrated word line. The cross-sectional view in the AA ′ direction shown in FIG. 2B is shown in FIG. 2A and FIG. 4I (a) as shown in 541690. 5. Description of the invention (9); As shown in Fig. 4 1 (b); the cross-sectional view in the CC-C 'direction shown in Fig. 2B is shown in Fig. 4 I (c); and the cross-sectional view in the D-D' direction shown in Fig. 2 B is shown in Fig. Figure 4 shows 1 (d). The unit cell cell indicated by the dashed line in Fig. 2B is an area of one multi-bit flash memory cell cell of 2 (1 + X) F 2, where X represents a scaling factor that can be controlled in the range of 1S X < 3. For example, x = 2, the cell size of each bit is only 3 F 2, which is smaller than the minimum cell size of 4 F 2 of the advanced non-sum array or a multi-bit flash memory cell of the prior art.

According to the above description, the multi-bit flash memory cell of the present invention and its memory cell array exhibit the following advantages and features: (a) The multi-bit flash memory cell of the present invention can provide a micronizable cell The size and cell size of each bit can be less than 4 F 2. (b) The multi-bit flash memory cell of the present invention can provide a self-aligning integrated floating gate layer to greatly increase the coupling ratio of the floating gate, which is higher than the coupling of the floating gate of the multi-bit flash memory cell in the past. Larger ratio and no additional mask photoresist steps required. (c) The multi-bit flash memory cell array of the present invention can provide a planar conductive pipeline, which has a smaller bit line resistance, a smaller bit line capacitance, and a smaller bit line than conventional buried diffusion bit lines. Leakage current.

(d) The multi-bit flash memory cell array of the present invention can provide a shallow groove isolation structure between different word lines (or selection lines) of the multi-bit flash memory cell, so as to eliminate the previous technology. Read error data. (e) The multi-bit flash memory cell array of the present invention can provide smaller word line resistance and capacitance than the multi-bit flash memory cell array of the past.

Page 12 541690 V. Description of Invention (ίο) Referring now to FIG. 2C, the circuit diagram of the multi-bit flash memory array shown in FIG. 2B is disclosed. As shown in FIG. 2c, the complex bits ~ BL3) and the complex control gate lines (CG0 ~ CG7) are parallel to each other ', and 葙 (WL0 ~ WL3) and the complex bit lines are perpendicular to each other, and the complex multiple bits are fast Each column of complex memory cells (300 ~ 311) is connected to a word line.

If a multi-bit flash memory cell 305 is selected for writing, the first voltage is connected to BL1 and the second voltage is connected to Bl2; the first voltage is also connected to a bit line on the same side as BL1 (such as BL0) The second voltage is also connected to the bit line (such as BL3) on the same side as bl2; the third voltage is connected to the control lines CG3 and CG4; and the fourth voltage is connected to the word line WL1. If the first voltage is 0 volts, the second voltage is 3 to 5 volts, the third voltage is 10 to 12 volts, and the fourth voltage is slightly greater than the threshold voltage V τ of the selection gate transistor, it is close to the bit line BL2 The stacked gate transistor can be used for hot electron injection by a high lateral electric field across the gap between the selected gate transistor and the bit line BL 2 to perform a write operation and predetermined by a fourth voltage

The cycle time reaches the desired level. By the same principle, if the first voltage is 3 to 5 volts, the second voltage is 0 volts, the third voltage is 10 to 12 volts, and the fourth voltage is slightly greater than the threshold voltage V τ of the selection gate transistor, it is close to the bit. The stacked gate transistor of the element line BL 1 is written, and the required level is written according to the cycle time of the added fourth voltage. It can be clearly seen that each stacked transistor can write different levels based on the cycle time of the fourth voltage added on the selected word line, and the write current is the fourth voltage added on the selection gate. Voltage

Page 13 541690 V. Description of invention (π) to control. Therefore, the writing efficiency is very high and the writing power is lower than the conventional channel terminal (c h a η n e 1-e n d) hot electron injection method. For scrubbing, the first voltage is about 10 ~ 12 volts connected to BL 1, and the third voltage is equal to 0 volts connected to CG3. All stacked gate transistors below the control line CG3 can be controlled by this The electrons stored in the floating gate below the line penetrate to the bit line BL 1 to perform the scrubbing action. Similarly, if the second voltage is about 10 ~ 12 volts connected to BL2, and the third voltage is equal to 0 volts connected to CG4, all stacked gate transistors under the control line CG4 are scrubbed. Since the bit line is a common bit line adjacent to two rows of cell elements, if the first voltage is about 10 to 12 volts connected to the bit line, and the third voltage is equal to 0 volts connected to the two adjacent two bit lines. By controlling the gate line, all stacked gate transistors adjacent to the two rows of the bit line can be scrubbed simultaneously. In the same way, if all the bit lines are connected to a voltage of about 10 to 12 volts and all control gate lines are grounded, the multi-bit flash memory cells in all arrays can be scrubbed at the same time. . It is worth noting here that the problem of excessive scrubbing does not occur because the selected gate transistor is turned off without applying the gate voltage. For reading, if a multi-bit flash memory cell 305 needs to be read, the first voltage is equal to 0 volts connected to the bit line BL1 and all bit lines (eg, BL0) on the same side as BL1, and the second A voltage of about 1.0 to 1.5 volts is connected to bit line BL2 and all bit lines on the same side (eg, BL3), a third voltage equal to 5 volts is connected to word line WL1, and a fourth voltage is about 10 to 12 volts. When CG4 and the fourth voltage equal to 5 volts are connected to CG3, the level of the stacked gate transistor below CG3 in the multi-bit flash memory cell 3 0 5 can be read; if the fourth voltage is about 10 ~ 1 2 volts connected to CG3 and the fourth voltage equal to 5 volts connected to CG4, then multi-bit flash memory

Page 14 541690 V. Description of the invention (12) The level of another stacked gate transistor of cell element 305 can be read. For the same reason, the level of the stacked gate transistor under CG 4 can also be read out by adjusting the voltages applied to BL1 and BL 2. Among them, the fourth voltage is about 10 ~ 12 volts connected to CG3 and the fourth voltage is equal to 5 volts connected to CG4. According to the above operation description, the operating voltage of the multi-bit flash memory cell of the present invention is simple, and the writing speed, scrubbing and reading are faster than the conventional non-Hash type flash memory array. Therefore, the miniaturizable flash memory cell and the memory array of the present invention have a better density · speed · power product. Referring now to FIGS. 3A to 3I, the process steps and cross-sectional views of a shallow groove isolation structure of a multi-bit flash memory cell with an integrated floating gate and its memory array are disclosed. FIG. 3A shows that a thin penetrating dielectric layer 101 is formed on a semiconductor substrate 100, a first conductive layer 102 is formed on the thin penetrating dielectric layer 101, and a first mask dielectric layer is formed. 10 3 is placed on the first conductive layer 102, and the formed photoresist PR1 is placed on the first mask dielectric layer 103 to define a plurality of active regions (below PR 1) and a plurality of parallel shallow groove isolation regions (PR 1). The thin penetrating dielectric layer 101 is a thermal silicon dioxide layer or a nitrided thermal silicon dioxide layer having a thickness between about 60 angstroms and 150 angstroms. The first conductive layer 102 is a doped polycrystalline silicon layer or a doped amorphous silicon layer, the thickness of which is between 100 angstroms and 300 angstroms and is formed by low pressure chemical vapor deposition (LPCVD). ) Law formation. The first mask dielectric layer 103 is composed of silicon nitride, and its thickness is between 1000 angstroms and 500 angstroms and is formed by the LPCVD method. It is worth mentioning here that Figure 3A shows only a small part of the memory array. In fact, the complex shaped photoresist PR 1 is used to define the complex active area and the parallel parallel shallow groove isolation area. The width and pitch of the shaped photoresist PR 1 can be used

Page 15 541690 V. Description of the invention (13) '--- Take the small line width F to define it, as shown in Figure 3A. The first mask dielectric layer 103, the first conductive layer 102, and the thin concavity are shown. After being absent, they are all selectively etched to form grooves ... and the formed photoresist PR1 is removed. The depth of the shallow groove formed in the semiconducting semiconductor is between 300 Angstroms and 800 Angstroms. Ugly soil anti-oxidation: Ϊ I picture three fills the voids formed by the etching to fill the planarization field and the planarization field oxide layer 1 ° 4a using chemical vapor stacking method or southern density plasma chemical vapor deposition ⑽: : = Physical layer to fill the gap, and then use a chemical-mechanical-flattening first (c 隹, say: I: surface and use the first mask dielectric layer 103 "at first glance is the flattening stop layer first" 〇P). It is worth mentioning here that the surface of the shallow groove can be two holes: oxidation to eliminate the defects caused by the shallow groove touch: a thick oxide layer 104. 1 Wen Dan Dui, ^ shows the planarized field oxide layer 1G4a shown in Fig. 2 after passing back to the level equal to one and a half thickness of the first conductive layer,

;: Plant 1 2 planarization brother 2 conductive ㉟ 1 ° 5 tear back etched planarized field oxygen 2 and the void formed on the material layer 104b. Planarize the second H. First, a thick second conductive layer is stacked to fill the gap, and the second conductive layer is smoothed and the stop layer is flattened with the first mask dielectric layer ι03. The planarized second conductive hafnium 105a is composed of doped ::: amorphous silicon and is stacked using the LPCVD method. ', Θθ s, Figure 3E shows the planarized second conductive layer 1 〇 ^ the thickness of the first mask dielectric layer 103a, / after ^ by touching a side wall approximately equal to each side to form a- Side wall f curtain: electrical layer, electrical layer 10 6 a. First side wall

Page 16 541690 V. Description of the invention (14) The dielectric pad layer 1 6 a is firstly deposited a good covering dielectric layer 106 on the formed structure, and then anisotropically etches back the cover. Thickness of the dielectric layer. The first side wall dielectric pad 106a is composed of silicon nitride deposited by the LPCCVD method. It is worth noting here that the pad width of the first side wall dielectric pad layer 10 6 a can be controlled by the thickness of the stacked dielectric layer 106 having a good coverage. Fig. 3F shows that the first side wall dielectric pad layer 106a and the first mask dielectric layer 103a are both removed by adding hot phosphoric acid. Figure 3G shows that the inter-gate dielectric layer 107 is formed on the first conductive layer 102a, the extended second conductive layer 105b, and the protruding field oxide layer 104b. The inter-gate dielectric layer 107 is composed of a composite dielectric layer, such as a silicon dioxide-silicon nitride-silicon dioxide (ONO) structure or a silicon nitride-silicon dioxide structure, which is equivalent to silicon dioxide. The thickness is between 80 angstroms and 150 angstroms. FIG. 3A shows that the third conductive layer 108 is formed on the inter-gate dielectric layer 107. The third conductive layer 108 is composed of a composite conductive layer, such as a polycrystalline silicon compound (ρ ο 1 ycide) structure placed on top of a doped polycrystalline silicon layer. Its thickness is between 3 Angstroms and 6 Angstroms. The second mask dielectric layer 109 is placed on the third conductive layer 108, as shown in FIG. 3I. The second mask dielectric layer 109 is composed of silicon nitride deposited by the LPCVD method, and its thickness is between 100 angstroms and 500 angstroms. It is worth noting here that the third conductive layer 108 can be a doped polyspar layer or a structure in which a barrier metal layer is interposed between two doped polycrystalline silicon layers, and silicidation is added in subsequent processes. . It can be clearly seen from Figure III that the integrated floating gate layer includes a first conductive layer 10 2 a and two extended second conductive layers 1 0 5 c, which can greatly increase the floating

Page 17 541690 V. Description of the invention (15) The coupling ratio of the brake, and the surface formed is quite smooth, so as to facilitate micro-line etching. In addition, the extended second conductive layer is formed by using a side pad technology, and the enemy does not need an additional mask photoresist step. Therefore, the isolation area can be defined by the minimum line width F. A cross-sectional view in the direction A-A 'in FIG. 3I is shown in FIG. 4A. As shown in Fig. 4A, the formed photoresist PR2 is placed on the second mask dielectric layer 10 to define a plurality of gate regions (below PR2). The width of a gate area includes two stacked gate transistors and a selection gate transistor, which are denoted by xF, where X represents a value greater than or equal to one and is a scale factor. The area outside the gate area (outside PR2) is a co-diffusion area, which can be defined by the minimum line width F. FIG. 4B shows that the second mask dielectric layer 10, the third conductive layer 108, and the inter-gate dielectric layer 107 outside the gate region are selectively etched and automatically aligned to be removed; Then, a part of the first conductive layer 10 2a is selectively etched, and the second conductive layer 105c (shown in FIG. 3I) placed on the protruding field oxide layer 104b is also removed. Then, The protruding field oxide layer 10 4b is selectively etched back to a level approximately equal to the top of the thin penetrating dielectric layer 1 0 1 a, and then the remaining first conductive layer 102b is removed, and then the formed mask light is removed. Resistance PR2 is removed. An ion implantation is performed across the thin penetrating dielectric layer 110a in an automatic alignment manner, and a lightly doped diffusion region 110a is formed in the semiconductor substrate 100, as shown in FIG. 4B. For the p-type semiconductor substrate 100, the implanted dopant is phosphorus; for the n-type semiconductor substrate 100, the implanted dopant is boron. In the subsequent processes, all descriptions and explanations are mainly based on P-type substrates, and the status of η-type substrates can also be handled by well-known methods. FIG. 4C shows that the thin penetrating dielectric layer 1 0 1 a outside the gate region is removed, and

Page 18 541690 V. Description of the invention (16) The etched flat field oxide layer is also slightly etched by diluted hydrofluoric acid to form a plurality of flat beds, each of which is alternately lightly doped with X The scattered area 1 1 Oa and the flattened protruding field oxide layer 104 c are formed, and this structure is expanded and shown later. The second dielectric pad layer 1 1 1 a is formed on the sides of the gate region and partially flat on the bed. The second dielectric pad 11a is composed of silicon oxide deposited by LpcvD, and the width of the pad is between about 2000 angstroms and 2000 angstroms. — Figure 4D shows the planarized fourth conductive layer} 12a (not shown) placed on a flat bed between a younger and a dielectric pad, and returning money to the top of the first conductive second layer 1 0 2 b Level to form a conductive line J 丨 2 b, and then the lithium oxide layer 1 1 3b is placed on the conductive line 1 1 2b, and then the plane = thick oxygen: the material layer is placed on the first silicide layer 113b . The planarization of the fourth conductive layer is performed by stacking the gap between the thick fourth conductive layer 112 and the pair of second dielectric pad layers ia, and then planarizing the thick fourth conductive layer by the CMP method, and The second mask dielectric layer i9a is used as a smoothing stop layer. The fourth conductive layer 112 is a doped polycrystalline silicon group deposited by the LPCVD method: and a high-concentration phosphorus impurity is implanted after etchback to form the conductive pipeline Π 2b. The first stone compound layer 113b can be formed by using a conventional self-aligned stone compound technology or stacking and planarizing the thick first stone compound, i 3a, and returning the surname. The first—Xi Xihusheng 113b is composed of refractive metal silicide, such as tungsten silicide (wsi2) ^ melting point silicide. The planarization of the first thick oxide layer 4a is composed of CVD oxidation: or phosphorous glass (PSG), and the voids above the first thick oxide layer 114 and the first petrochemical layer 113b are first deposited, and then the CMP is used. The planarized first thick oxide layer 114 is planarized, and the second mask dielectric 109a is used as a smoothing stop layer. θ

Page 19 541690 V. Description of the invention (17) Figure 4E shows that the second mask dielectric layer 10 9a is removed by thermal phosphoric acid or anisotropic dry worm cutting and then the inner side of each gate area. Two third dielectric pad layers 115a are formed. The third dielectric pad 115a is composed of silicon nitride or silicon dioxide, and is deposited by the LPCVD method. It is worth mentioning here that the pad width of the third dielectric pad 115a is used to control the gate length of two stacked gate transistors formed in the gate region. Figure 4 shows that the third conductive layer 108a, the inter-gate dielectric layer 107a, and the first conductive layer 102b / extended second conductive layer 105c located on the third dielectric pad layer are all anisotropically etched. Then, ion implantation is performed across the thin penetrating dielectric layer 1 0 1 b in an automatic alignment manner, and an ion implantation region 116 a is formed in the semiconductor substrate 100, which includes a shallow ion implantation region (represented by a dotted line). (Shown) as the adjustment of the threshold voltage of the selection gate and a deep ion implantation zone (shown as X) as the forbidden zone. The shallow ion implantation area is formed by implanting boron fluoride (BF 2) impurities, and the deep ion implantation area is formed by implanting boron impurities. Figure 4G shows that the thin penetrating dielectric layer 1 0 1 b between two stacked gate transistors is removed by dipping hydrofluoric acid and then forming a gate dielectric layer 1 18 on the structure. The gate dielectric layer 1 1 8 is composed of silicon dioxide formed by high temperature oxidation (HTO) or a composite dielectric layer, such as silicon nitride-silicon dioxide or silicon dioxide-silicon nitride-silicon dioxide. The structure has an equivalent silicon dioxide thickness between 200 angstroms and 500 angstroms. Figure 4 shows that the fifth conductive layer 1 19 is stacked on the gate dielectric layer 1 18 to fill the gap between the two stacked gate transistors and is planarized by the CMP method. The fifth conductive layer 119 is composed of a doped polycrystalline silicon layer or a first metal layer disposed on the first barrier metal layer. If doped with a polycrystalline silicon layer as the fifth conductive layer

P.20 541690 V. Description of the invention (18) 119, 118-gate nitride dielectric layer _ silicon dioxide-stone dioxide (ONO) structure, @ 一 / 化 碎 structure or stone dioxide-for nitrogen Talking about ... Oxygen ... and the fifth conductive layer 1193 can be used for "9a"-to further increase the thickness of the cloth Vi /, while the planarization of the fifth conductive layer is μμ 田田 古 "卞 师 植 回 / 辰 度 的 杂质 impurities (Not shown) and automatically aligned with the Shixihua process to form a 7-fold refractive metal silicide layer, such as: titanium silicide (T i S i 2), cobalt silicide (cosi2), silicon button ( TaSi2), nickel silicide (NiSi2), molybdenum silicide 0S10, platinum silicide (PtSi 2) or tungsten silicide (wsi 2), etc. The sixth conductive layer 120 is formed on the gate dielectric layer 118 and the planarized fifth conductive layer u9a Above, it is shown in Figure 4. If the first metal layer is placed on the first barrier metal layer, the structure is. The fifth conductive layer 119, wherein the first metal layer is made of tungsten (w) or silicon. 2), and the first premature metal layer is made of refractive metal nitride = such as: titanium nitride (TiN) or nitride button (TaN), and the planar conductive layer 119 & CMP is planarized and a gate dielectric layer 118 $: f ^ ^ stop layer, and then a sixth conductive layer 1 2 0 is formed on the gate dielectric layer 1 1 8 Case = No. = ... ΪΓ " on the above two layers: The electrical layer I20 is formed by the second metal layer placed on the second barrier metal, which is entirely reed: f *. The second metal layer is composed of aluminum or steel, and the second barrier : The metal layer is composed of refracted metal nitrides, such as titanium oxide or gas. Figure I (a) shows that a plurality of hard masks are formed on the curtain layer to form a complex number line on a complex active area, and / N 9 120 is conductive. One layer of the layer 120 and the fifth conductive layer 丄 19 serves as an etching sixth soap curtain layer. The hard mask curtain layer system

Page 21 541690 V. Description of the invention (19) Including the third cover dielectric layer 121 a and the side wall dielectric layer 1 2 2 a (as shown in Figure 4I (b) to Figure 4I (d) (Shown), and is composed of nitrided stone or dioxide. Reference is now made to FIG. 4I (b) to FIG. 4I (d), in which various cross-sectional views shown in FIG. 4I (a) are shown. Figure IV (b) shows a cross-sectional view in the direction B-B 'indicated by Figure IV (a); Figure IV (c) shows a cross-section in the direction C-C' indicated by Figure IV (a); And FIG. 4 I (d) shows a cross-sectional view in the direction D-D ′ indicated in FIG. 4 I (a). As shown in FIG. 4I (b), the bit line includes a thinner planarized fourth conductive layer 1 1 2b covered with a first silicide layer 1 1 3b, which is placed on a flat bed, and the flat bed is alternated. The ground is composed of a highly doped (η +) diffusion region 1 1 7 a and an etched flat field oxide layer 1 0 4c. The complex digital line includes a shaped sixth conductive layer 1 2 0 a which is placed on top of the gate dielectric layer 11 8 on the planarized thick silicon dioxide layer 1 1 4b, and a hard mask layer includes a third mask The dielectric layer 121a and the dielectric layer 1 2 2a on the side walls on both sides are used as a mask layer of a word line engraved above the active area. Figure IV (c) shows a cross-sectional view in the direction C-C 'indicated by Figure IV (a) and is also a cross-sectional view along the direction of the extended control gate layer 108b of the stacked gate transistor. As shown in FIG. 4 I (c), an integrated floating gate layer includes a main floating gate layer 1 0 2 c formed in a thin penetrating dielectric layer 1 0 1 c and two extended floating gate layers 1 0 5 c They are respectively placed on a part of the surface adjacent to the two protruding field oxide layers 1 0 4 b; the inter-gate dielectric layer 10 7b is placed between the complex integrated floating gate layer and the protruding field oxide layer 1 0 4b The third conductive layer 108b is formed on the inter-gate dielectric layer 107b as an extension control gate layer; the second side wall dielectric cushion layer 11.5b is placed on the third conductive layer 108b To define the control gate length; gate dielectric layer

Page 22 541690 V. Description of the invention (20) 1 1 8 is formed on the second dielectric pad 11 5 b; the complex digital line includes a shaped sixth conductive layer 1 2 0 a is formed on the gate dielectric layer 1 18, and a hard cover curtain layer includes a third cover dielectric layer 1 2 1 a and a side wall dielectric cushion layer 1 2 2 a on both sides, and serves as a word line formed above the active area. The curtain. Figure IV (d) shows a cross-sectional view in the direction D-D 'indicated by Figure IV (a) and is also a cross-sectional view along the selected gate direction in the gate area. As shown in FIG. 4I (d), the gate dielectric layer 118 is placed on the surface of the complex protruding field oxide layer 104b and the semiconductor substrate 100 located in the complex active area; the complex digital lines and the complex planarization The fifth conductive layer 1 1 9 a is simultaneously formed and etched by using a plurality of hard mask layers as a mask. As can be clearly seen from the figure, the side wall dielectric cushion layer 1 2 2 a is used to eliminate the misalignment of the word line and its integrated selection gate relative to the active interval. Although the present invention is specifically referred to the attached example And connotations to illustrate and describe, but only represent statements and not limitations. Moreover, the present invention is not limited to the details listed, and those skilled in the art can also understand that changes of various shapes or details can be made without departing from the true spirit and scope of the present invention. 0 References US patents 5, 3 64, 8 0 6 1 1/1 9 94 Ma et al.

Page 23 541690 V. Description of the invention (21) 5, 654, 917 08/1997 Ogura et a 1. 5, 989, 960 11/1999 Fuka seeta 1. 6, 051, 860 04/2000 Odanaka eta 1 6,133,098 10 / 2000 Ogura et al. 6,248,633 B1 06/2001 Ogura eta 1. Other publications S. Aritome, Advanced Flash Memory Technology and · Trends for File Storage Application, "I EDM (2 0 0 0), pp · 763 ~ 766 · JD-Choi et al., 丨 丨 A 0.15 // m NAND Flash Technology with 0.1 // m 2 cell Size for 1G bit Flash Memory, M IEDM (2000), pp. 767-770.

Page 541690 Brief Description of Drawings Figures 1A and 1B show the structure of the prior art, of which Figure 1A shows a cross-sectional view of a multi-bit flash memory cell; Figure 1B shows a multi-bit flash Top view of memory cells. FIG. 2A to FIG. 2C show the structural diagrams of the present invention, wherein FIG. 2A shows a cross-sectional view of a miniaturizable multi-bit flash memory cell of the present invention; FIG. A top view of a bit flash memory cell array; and FIG. 2C illustrates a circuit diagram of a miniaturizable multi-bit flash memory cell array of the present invention. Figures 3A to 3I disclose the process steps and cross-sectional views of a shallow groove isolation structure with an integrated floating gate layer. FIGS. 4A to 4I show the process steps and cross-sectional views of a miniaturizable multi-bit flash memory cell and its memory array according to the present invention, and FIG. 4A (a) shows A marked in FIG. 2B -A 'direction cross-section; Figure IV 1 (b) reveals a cross-sectional view of the direction B-B' marked in Figure II B or Figure IV 1 (a); Figure IV (c) reveals Figure II B or Figure IV A cross-sectional view in the direction C-C 'indicated by I (a); and a cross-sectional view in the direction D-D' indicated in FIG. 2B or FIG.

Page 25

Claims (1)

541690 6. Scope of patent application 1. A miniaturizable multi-bit flash memory cell, comprising at least: a semiconductor substrate of the first conductivity type; a cell region including an active region and two shallow groove isolation regions Formed on the semiconductor substrate, the cell is divided into two regions. A gate region is formed between the first side region and the second side region. The gate region is defined by a mask photoresist step. Can be miniaturized; a co-diffusion region belonging to the second conductivity type is formed in the active region of the first side region and the second side region, and the gate region is used as an ion implantation mask; a flat bed is formed respectively The first side region and the second side region, wherein the flat bed # is composed of the co-diffusion region and an etch-level protruding field oxide layer disposed on the two shallow groove isolation regions; a side wall A silicon dioxide cushion layer is formed on each side wall of the gate region and on a part of the surface of the flat bed; a conductive layer is formed as a bit line on the side wall silicon dioxide cushion layer, respectively. Outside of On a flat bed; a planarized thick oxide layer is formed on the conductive layer and the side wall silicon dioxide cushion layer; two stacked gate transistors are formed on the side portions of the gate region and one A selective gate transistor is formed between the two stacked gate transistors, wherein each of the two stacked gate transistors includes at least one side wall cushion layer formed from the top to the bottom. An oxide stone cushion layer and a side wall created by the planarized thick oxide layer, an extended control gate layer is placed on an inter-gate dielectric layer, and an integrated floating gate layer is placed on the inter-gate dielectric Page 26 541690 6. The patent application scope is under the electric layer; the integrated floating gate layer includes at least one main floating gate layer formed on a thin penetrating dielectric layer and two extended floating gate layers respectively. A portion of the surface of the protruding field oxide layer on the two shallow groove isolation regions; a gate dielectric layer disposed on the semiconductor surface between the two stacked gate transistors, and the two stacked gates Transistor and its inner side wall, and the planarized thick oxide layer located on the first side area and the second side area; and a word line is formed above the active area and is perpendicular to the extension control The gate layer, wherein the zigzag line includes at least one hard cover curtain layer placed on a metal layer and a planarized conductive island on the gate dielectric layer between the two stacked gate transistors. 2. The multi-bit flash memory cell according to item 1 of the patent application scope, wherein the co-diffusion region is a lightly doped diffusion region. 3. The multi-bit flash memory cell according to item 1 of the scope of patent application, wherein the conductive layer is a highly doped polycrystalline silicon layer of the second conductivity type and is covered with a refractory metal (refractory- metal), and the highly doped polycrystalline silicon layer serves as an impurity diffusion source formed in the highly doped co-diffusion region in the co-diffusion region. ⑩ 4. The multi-bit flash memory cell as described in item 1 of the scope of patent application, wherein the extension control gate layer is a compound crystal compound (ρ ο 1 y c i d e-g a t e) layer 0 Page 27 541690 6. Application for patent scope 5. The multi-bit flash memory cell as described in item 1 of the scope of patent application, wherein the integrated floating gate is composed of doped polycrystalline silicon or It is composed of doped amorphous silicon. 6. The multi-bit flash memory cell as described in item 1 of the patent application scope, wherein the side wall dielectric cushion layer is made of silicon nitride, silicon oxynitride, silicon dioxide or low dielectric. Consisting of a constant dielectric material. 7. The multi-bit flash memory cell as described in item 1 of the scope of patent application, wherein the gate dielectric layer is a silicon dioxide layer or a silicon nitride-silicon dioxide or silicon dioxide. Multi-bit flash memory cell as described in item 1 of the patent application scope, wherein said planarized conductive island is made of doped polycrystalline silicon or The doped amorphous silicon is covered with a refractive metal silicide layer. 9. The multi-bit flash memory cell as described in item 1 of the scope of patent application, wherein the planar conductive island is formed by a planar metal island on < · barrier-metal Made up of layers. 10. The multi-bit flash memory cell according to item 1 of the scope of patent application, wherein the metal layer is a Ming layer, a copper layer, a Yan layer, or Page 28 541690 VI. Scope of patent application A Shixi chemical crane layer is composed of a barrier metal layer. 1 1. The multi-bit flash memory cell according to item 1 of the patent application scope, wherein the hard mask layer comprises at least one mask dielectric layer placed above the active area and two side walls The cushion layer is formed on a side wall of the mask dielectric layer and is composed of silicon nitride or silicon dioxide. 12. The multi-bit flash memory cell according to item 1 of the scope of patent application, wherein an ion implantation area is implanted on the surface of the semiconductor substrate between the two stacked gate transistors. The ion implantation area includes at least one shallow ion implantation area for adjusting the threshold voltage and a deep ion implantation area to form a punch-through stop area. 1 3. A miniaturized multi-bit flash memory cell array including at least one semiconductor substrate of the first conductivity type; a plurality of parallel shallow groove isolation (ST I) regions and a plurality of active regions are formed on the semiconductor substrate Wherein a protruding field oxide layer is provided on the plurality of parallel shallow groove isolation regions; A plurality of gate regions are alternately formed on the semiconductor substrate and perpendicular to the plurality of parallel shallow groove isolation regions, wherein each of the plurality of gate regions is formed between a pair of common bit line regions and is formed by one A mask photoresist step to define and thus can be miniaturized; a plurality of co-diffusion regions belonging to the second conductivity type are formed in the collinear line region 541690 6. In the semiconductor substrate of the plurality of active regions in the scope of patent application; a flat bed is formed in each of the collinear line regions, wherein the flat bed is alternately formed by the plurality of co-diffusion regions and etch Composed of a flat protruding field oxide layer; a side wall silicon dioxide pad layer is formed on the side wall of each of the plurality of gate regions and placed on a part of the surface of the flat bed; a conductive layer serves as a bit The element line is placed on the flat bed between each of the collocation line areas to the side wall silicon dioxide cushion layer; a planarized thick oxide layer is formed on a pair of the side wall silicon dioxide layer And on the conductive layer therebetween, two stacked gate regions are formed on the side of each of the plurality of gate regions, and a selective gate region is formed between the two stacked gate regions, wherein the two Each stack gate area includes at least one side wall dielectric layer from top to bottom, an extended control gate layer placed on top of the gate dielectric layer, and a plurality of integrated floating gate layers placed on the gate. Under the interlayer dielectric layer; Each of the floating gates includes at least one main floating gate layer on a thin penetrating dielectric layer and two extended floating gate layers on a portion of the surface adjacent to the two protruding field oxide layers, respectively; A gate dielectric layer is alternately formed on the plurality of semiconductor surfaces of the two stack gate regions, the two stack gate regions and their inner side walls, and the planarized thick oxide layer; and a complex number Lines are formed above the plurality of active areas and are perpendicular to the extended control gate layer, wherein each of the plurality of digital lines includes at least one hard cover curtain layer placed on a metal layer and a pair of the two stacks Gate interval Page 30 541690 VI. Patent Application Scope The gate dielectric layer has a plurality of planarized conductive islands. 14. The miniaturizable multi-bit flash memory cell array according to item 13 of the patent application scope, wherein the co-diffusion region includes at least one highly doped diffusion region formed in a lightly doped diffusion region Inside. 1 5. The miniaturizable multi-bit flash memory cell array according to item 13 of the patent application scope, wherein the conductive layer is covered by a highly doped polycrystalline silicon layer covered with a refractive metal silicide layer. composition. 16. The miniaturizable multi-bit flash memory cell array according to item 13 of the scope of patent application, wherein the planarized conductive island is composed of doped polycrystalline silicon and is covered with refractive metal silicide. Physical layer. Jiji = Mouth / Ί The surface of the flash surface is more than one unit, which is more than 3 of the flat items of the chemical surface that can be guided by the chemical system contraction island microelectronics. Cell. Fine 7 1 The Cryptococcus aureus surface of the Cretaceous islands should be composed of gold. Obstructing the barrier group, all tungsten is placed on or placed on the island of tungsten. It is a gold coin. It is written by a fast system and a bit line characterizes the contraction. Please apply, apply for .Imt special element such as cell • Fine 8 1It face-in the forming layer tungsten 1 or layered silicon 1 or. The layers are the same as those of the BL, or the layers are gold and aluminum. Page 31 541690 VI. Application scope 1 9. The miniaturizable multi-bit flash memory cell array described in item 13 of the scope of patent application, wherein the hard mask layer includes at least one mask The electrical layer and the dielectric pad layers on the side walls of the electrical layer and the side wall are composed of a dioxide stone or a nitride stone. 20. The miniaturizable multi-bit flash memory cell array according to item 17 or item 18 of the patent application scope, wherein the barrier metal layer is composed of a refracted metal nitride, such as: Titanium nitride (T i N) or nitride group (T a N). Page 32