TW200406884A - Method of forming a stacked-gate cell structure and its NAND-type flash memory array - Google Patents

Method of forming a stacked-gate cell structure and its NAND-type flash memory array Download PDF

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Publication number
TW200406884A
TW200406884A TW91132230A TW91132230A TW200406884A TW 200406884 A TW200406884 A TW 200406884A TW 91132230 A TW91132230 A TW 91132230A TW 91132230 A TW91132230 A TW 91132230A TW 200406884 A TW200406884 A TW 200406884A
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TW
Taiwan
Prior art keywords
formed over
select lines
paired
lines
stacked
Prior art date
Application number
TW91132230A
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TW569395B (en
Inventor
Ching-Yuan Wu
Original Assignee
Intelligent Sources Dev Corp
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Priority to TW91132230A priority Critical patent/TW569395B/en
Application granted granted Critical
Publication of TW569395B publication Critical patent/TW569395B/en
Publication of TW200406884A publication Critical patent/TW200406884A/en

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Abstract

A stacked-gate cell structure having a tapered floating-gate layer and a laterally graded source/drain diffusion profile is implemented to form NAND cell strings over a self -aligned STI structure having a high coupling ratio. The paired string select lines and the paired ground select lines being formed over one-side tapered floating-gate layers are simultaneously defined by a spacer formation technique and are therefore scalable. Each of common-source conductive bus lines is formed over a first flat bed between a pair of sidewall dielectric spacers being formed over sidewalls of the paired ground select lines. A plurality of planarized conductive islands are formed over common-drain diffusion regions between another pair of sidewall dielectric spacers being formed over sidewalls of the paired string select lines and are patterned simultaneously with a plurality of metal bit - lines by using a masking photoresist step.
TW91132230A 2002-10-30 2002-10-30 Method of forming a stacked-gate cell structure and its NAND-type flash memory array TW569395B (en)

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TW91132230A TW569395B (en) 2002-10-30 2002-10-30 Method of forming a stacked-gate cell structure and its NAND-type flash memory array

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Application Number Priority Date Filing Date Title
TW91132230A TW569395B (en) 2002-10-30 2002-10-30 Method of forming a stacked-gate cell structure and its NAND-type flash memory array

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TW569395B TW569395B (en) 2004-01-01
TW200406884A true TW200406884A (en) 2004-05-01

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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8405196B2 (en) 2007-03-05 2013-03-26 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
US8432045B2 (en) 2010-11-15 2013-04-30 Tessera, Inc. Conductive pads defined by embedded traces
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8704347B2 (en) 2006-11-22 2014-04-22 Tessera, Inc. Packaged semiconductor chips
US8735287B2 (en) 2007-07-31 2014-05-27 Invensas Corp. Semiconductor packaging process using through silicon vias
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US9070678B2 (en) 2006-11-22 2015-06-30 Tessera, Inc. Packaged semiconductor chips with array
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8704347B2 (en) 2006-11-22 2014-04-22 Tessera, Inc. Packaged semiconductor chips
US9548254B2 (en) 2006-11-22 2017-01-17 Tessera, Inc. Packaged semiconductor chips with array
US9070678B2 (en) 2006-11-22 2015-06-30 Tessera, Inc. Packaged semiconductor chips with array
US8405196B2 (en) 2007-03-05 2013-03-26 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
US8735205B2 (en) 2007-03-05 2014-05-27 Invensas Corporation Chips having rear contacts connected by through vias to front contacts
US8735287B2 (en) 2007-07-31 2014-05-27 Invensas Corp. Semiconductor packaging process using through silicon vias
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8809190B2 (en) 2010-09-17 2014-08-19 Tessera, Inc. Multi-function and shielded 3D interconnects
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US9355948B2 (en) 2010-09-17 2016-05-31 Tessera, Inc. Multi-function and shielded 3D interconnects
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8432045B2 (en) 2010-11-15 2013-04-30 Tessera, Inc. Conductive pads defined by embedded traces
US8772908B2 (en) 2010-11-15 2014-07-08 Tessera, Inc. Conductive pads defined by embedded traces
TWI401781B (en) * 2010-11-15 2013-07-11 Tessera Inc Conductive pads defined by embedded traces
US9368476B2 (en) 2010-12-02 2016-06-14 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US9099296B2 (en) 2010-12-02 2015-08-04 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages with plural active chips
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US9269692B2 (en) 2010-12-02 2016-02-23 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US9620437B2 (en) 2010-12-02 2017-04-11 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US8796828B2 (en) 2010-12-08 2014-08-05 Tessera, Inc. Compliant interconnects in wafers
US9224649B2 (en) 2010-12-08 2015-12-29 Tessera, Inc. Compliant interconnects in wafers

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Publication number Publication date
TW569395B (en) 2004-01-01

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