TW569395B - Method of forming a stacked-gate cell structure and its NAND-type flash memory array - Google Patents

Abstract

A stacked-gate cell structure having a tapered floating-gate layer and a laterally graded source/drain diffusion profile is implemented to form NAND cell strings over a self-aligned STI structure having a high coupling ratio. The paired string select lines and the paired ground select lines being formed over one-side tapered floating-gate layers are simultaneously defined by a spacer formation technique and are therefore scalable. Each of common-source conductive bus lines is formed over a first flat bed between a pair of sidewall dielectric spacers being formed over sidewalls of the paired ground select lines. A plurality of planarized conductive islands are formed over common-drain diffusion regions between another pair of sidewall dielectric spacers being formed over sidewalls of the paired string select lines and are patterned simultaneously with a plurality of metal bit-lines by using a masking photoresist step.

Description

569395 V. Description of the invention (1) Background of the invention: (1) The scope of the invention The present invention relates to a boat non-operating device and its memory array; non-volatile semiconductor memory cell gate cell structure and A 4 temple are It is related to a stacked _ manufacturing method. (2) of the NAND-type flash memory array (2), the conventional art describes the basic f / i: t: ^ structure system composition-a high-density fast Cells of flash memory arrays can benefit from structures ....-an overlapping area between individual camps or between the floating gate and the common source diffusion zone ~ Fowler ~ pen 彳 1; the heavy camp area between the conductor substrates Rich channel 埶 雷 子 4. (heim) Penetration mechanism to scrub. Generally, the writing work of the channel hot electron left-entry mechanism and the stack gate length are the same as & t The limitation of the effect is that it is not easy to add miniaturization. The above writes the mind; the structure uses the channel hot electron injection mechanism as -2 1: and forms a non-or-type (_-type) memory array. Write and scrub through Fuller-Nordheim penetrating between semiconductor substrates to obtain low power element junctions The structure " cross section is not as y; the system stack gate = the cell structure of the stack is in a writing '丨 Figure-A shows-edge stack U, 1U horse into a sad state; and Figure 1 B shows the stack

569395 V. Description of the invention (2) The gate cell structure is in a scrubbing state. It can be clearly seen from FIG. 1A and FIG. 1B that a gate stack from top to bottom includes at least one tungsten silicide layer 105, a doped polycrystalline silicon layer 104, and a gate ( (Inte gate) dielectric layer 103, a doped polycrystalline stone layer 102, and a penetrating oxide layer 101 are usually defined by a minimum line width (F) of the technology used and placed in the formation On a p-well 3 0 0 b within a η-well 3 0 a; and a symmetrical common source / drain n + diffusion region 106a / 106b is implanted with a high dose of doping in an auto-aligned manner It is within 100Ob of the p-well and uses the gate stack as an ion implanted mask. It can be seen from Fig. 1A that when the control gate 10 ￥ / 104 is applied with a high positive gate voltage (for example, + 18 volts), the source / drain n + diffusion region 10 6 a / 1 〇 6 b , The ρ well 10 0 b and the η well 100a are grounded, then the induction surface inversion layer and source / drain n + diffusion region 1 located below the penetration oxide layer 101 The electrons of 〇6a / 10b will penetrate the penetrating oxide layer 101 to the floating gate layer 102 to perform a write operation. It can be seen from Fig. 1B that when the gate brake 105/1104 is grounded, the 姘 100b and the _i〇〇a plus a still positive voltage (for example / ί nh /] μμΛ), and the source / Steam n + diffusion region af ^ it f ^ V ^ 102 ^ 1 ^ ^ operation. It can be clearly seen here that% 10: b is miniaturized by the idle length of the cell structure that performs one scrub: Figures: A and Figure-B. The stack closure will quickly shrink, while writing and washing The applied control gate voltage and the effective area write of j writing and scrubbing will also decrease. In addition, it is high, so a floating junction & plus the voltages of wells P and η is relatively necessary in order to reduce 彳. There is a high coupling ratio (coupling & Controlled voltage and scrubbing

Page 7 569395 V. Description of the invention (3) The voltage of well p and well η is added. A shallow groove isolation (ST I) structure with a non-automatically aligned floating gate layer and a high coupling ratio requires two rigorous (cr iti ca 1) curtain steps to fabricate a non-harmonic flash memory array. At least four rigorous masking steps are required to automatically align the shallow groove isolation structure. Therefore, a main object of the present invention is to provide a non-Japanese flash memory array when the stack gate length is reduced. A stack gate cell structure has an oblique floating gate structure to have a larger write and scrub. area. Another object of the present invention is to provide an auto-aligned floating gate structure having a large coupling ratio. A still further object of the present invention is to provide a method for manufacturing a contactless non-harmonic flash memory array with fewer rigorous masking steps and a smaller unit cell. Summary of the invention: The stacked gate cell element structure of the present invention has an oblique-angle floating gate layer for forming a non-contact non-harmonic flash memory array. The above-mentioned oblique-angle floating gate layer not only provides a large surface area on A penetrating dielectric layer is used for writing and scrubbing without increasing the control gate length and providing a beveled tip to increase the speed of scrubbing. The non-contact non-harmonic flash memory array of the present invention is manufactured on a shallow groove isolation structure having an automatic alignment floating gate structure, wherein the above-mentioned automatic alignment floating gate structure can provide a Higher coupling ratio and fewer rigorous masking steps to fabricate and a smooth surface to form an inter-gate dielectric layer to reduce sharp field emission

569395 V. Description of the invention (4) Radiation effect. The width of the string selection line and the ground selection line of the above-mentioned non-contact and non-type flash memory array is defined by a pad formation technology and can be made smaller than a minimum line width of the used technology. The conductive space of the selection gate transistor under each of the above-mentioned string selection line and ground selection line is manufactured to have a single-sided bevel structure, so that it can provide a longer channel length than the width of the string ground selection line. Each of the common source conductive pipelines of the present invention is formed on a first flat bed composed of a common source diffusion region and a third protruding field oxide layer alternately, so that a lower And a lower line capacitance relative to the semiconductor substrate. Each of the bit line contact points of the present invention is composed of a planarized common leakage conductive island and is simultaneously formed with a metal bit line, so it can easily provide a larger contact area under a miniature contact technology and A higher contact reliability. The contactless NAND flash memory array of the present invention can be manufactured with fewer rigorous mask photoresist steps than the prior art and has a smaller unit cell size. Detailed description of the invention: Please refer to FIG. 2A and FIG. 2B, wherein a stack gate cell structure of the present invention operates in a writing state as shown in FIG. 2A and operates in a scrubbing state as shown in FIG. 2B Show. The cell structure of the stack gate of the present invention includes at least one composite control gate 3 1 Oa / 3 0 9b, an inter-gate dielectric layer 3 08a, an oblique floating gate layer 3 0 2b, and a penetration from top to bottom. A dielectric layer 30 lb is formed on a p-well 3 0 0 b located within an n-well 3 0 a; and the source / drain diffusion region 3 1 2 a has a lateral gradient doping profile for automatic alignment of

Page 9 569395 V. Description of the invention (5) A high-dose dopant is implanted across the oblique portion of the oblique floating gate layer 3 0 2 b and the penetrating dielectric layer 3 0 1 b. The p well is within 3 0 0 b. Obviously, the stack gate cell structure of the present invention is larger than the prior art shown in FIG. 1A and FIG. 1B under the known control gate length, which can face the penetrating dielectric layer 3 0 1 b. A surface area. As shown in the writing state shown in FIG. 2A, the common source and drain diffusion region 31 2a and the semiconductor substrate (P well 30 0b and η well 3 0 0a) are grounded, and the composite control gate layer 31 0a / 3 0 9b Plus a high positive voltage vCG, the electrons can penetrate the penetrating dielectric layer to the oblique floating gate by the surface inversion layer generated by the common source / drain diffusion region 3 1 2 a and p well 3 0 0 b Within 302b, as indicated by the arrow. As shown in the scrubbing state shown in FIG. 2B, the composite control gate layer 3 丨 〇a / 309b is grounded, and the semiconductor substrate (p well 3) is floating. 0 0 b and η well 3 0 0 a) are applied with a positive high voltage v μ, then the electrons stored in the oblique floating gate 302 b can penetrate the penetrating dielectric layer 30 lb to the P well 3 0 0b And the common source / drain diffusion region 312a. It can be clearly seen here that the scrubbing area shown in FIG. 2B is larger than the prior art shown in FIG. 1B. In addition, the sharp angle of the oblique floating gate layer 3 2b can also enhance the penetrating current in the scrub state. In the subsequent display, an automatic alignment floating gate structure is formed in the width direction of the gate to increase the coupling ratio of the oblique floating gate layer 3 2 2b, and the applied control voltage V c in the write state and the scrub state The applied substrate voltage V SB can be further reduced. Referring now to FIGS. 3A to 3F, it is disclosed that a shallow groove isolation structure for fabricating a self-aligned floating gate structure with a high coupling ratio is fabricated to make a forward non-harmonic array. FIG. 2A shows that a penetrating dielectric layer 301 is formed on a first conductive layer.

Page 10 569395 V. Description of the invention (6) a semiconductor substrate 300; a first conductive layer 3 02 is formed on the penetrating dielectric layer 301; and a first cover intermediary The electric layer 303 is formed on the first conductive layer 302. The above-mentioned penetrating dielectric layer 301 is a thermal silicon dioxide layer or a nitrided thermal dioxide layer, and its thickness is between 60 angstroms and 120 angstroms. The above-mentioned first conductive layer 30 is composed of doped polysilicon or doped amorphous silicon and is stacked using the lpcvd method. Its thickness is between 1000 angstroms and 500 angstroms. The above-mentioned first mask dielectric layer 3 0 3 is composed of silicon nitride and is stacked by the lpcvd method, and its thickness is between 15 0 angstroms and 3 0 0 angstroms. ^ FIG. 3 shows that the plurality of shallow groove isolation regions (STI) and the plurality of active regions (AA) are patterned alternately by a mask photoresist step PR1 (not shown) on the semiconductor substrate 300. The plurality of shallow grooves are filled with the planarized field oxide layer 304a. The width of the shallow groove isolation region (STI) and the width of the active region can be defined using a minimum line width (F) of the technology used. The above-mentioned planarized field oxide layer 304a is composed of silicon dioxide, phosphorous glass (P-glass), and borophosphoglass (bp-giass), and uses lpcvd, high-density plasma (HDP) CVD, Or plasma enhanced (PE) cvD method for stacking, first deposit a thick silicon dioxide film 3 04 to fill each void of the deep groove, and then use the CMP method to deposit the thick silicon dioxide film 3 0. 4 is planarized and the shaped first mask dielectric layer 303a is used as a flat stop layer (poi-ng stop). The shallow groove is located at a depth of 300 from the semiconductor substrate to between 25 and 50 angstroms. FIG. 2C shows that the planarized field oxide layer 3 0 4 a is selectively backed up to approximately equal to the first conductive shape by non-isotropic dry etching or house-etching.

569395 V. Description of the invention (7) One and a half thicknesses of the electric layer 302a and using the formed first mask dielectric layer 3 0 3a as an etching mask to form a first protruding field oxide layer 3 0 4b. FIG. 3D shows that a planarized second conductive layer 3 0 5 a fills every gap between the formed first mask dielectric layer 3 0 3 a and is then etched back to the first conductive layer 3 0 2 a top surface of a is horizontal to form an etch-back second conductive layer 30 5b on each of the first protruding field oxide layer 304b; and a pair of first side wall dielectric spacers 3 〇6a is formed on the side wall of each of the plurality of shallow groove isolation regions adjacent to the first mask dielectric layer 303a formed. The above-mentioned planarized second conductive layer 305a is composed of doped polycrystalline silicon or doped amorphous silicon and is deposited by LPCVD method. A thick second conductive layer 305 is first deposited to fill the area. Each gap between the formed first mask dielectric layer 3 0 3a is planarized by the cmp method, and the formed first mask dielectric layer 3033 is planarized. Operation, a smooth stop layer. The above-mentioned first side wall dielectric cushion layer 3 0 6 a is composed of gasified stone and is stacked using LPCVD method. A first dielectric layer is deposited first, and the first dielectric layer is then etched back by layer ^ 06. A thickness of layer 3 0 6. It can be clearly seen here that the thickness of the pad of the first side wall dielectric pad 30 6a is equal to the thickness of the stacked first dielectric layer 3 06 and can therefore be controlled. FIG. 2E shows that the etched back second conductive layer 3 0 5b located between the pair of first side wall dielectric pads 3 0 6a in each of the plurality of shallow groove isolation regions is anisotropically added. Pre-removed to form an extended second conductive layer 3 0 5 c; then, in the forming, a mask dielectric layer 3 0 3a and the first side wall dielectric pad layer 3 6 a are removed by adding high-temperature phosphoric acid; Next, a pair of thin side wall conductive pads

Page 12 Five 3 0 7a System Guidance System Description of the Invention (8) Each of the electric layer 3005e6 ^ each of the shallow groove isolation regions is extended by a second doping process. The conductive pad layer 3 0 7a of the above-mentioned side wall is first piled up: 3 :: amorphous silicon and is stacked on top by the lpcvd method, and then the back-etched conductive layer 307 is clearly formed on a structured surface. It can be seen that the thickness of the conductive layer 307 of Ling and Zhiyan is 307. Here can be extended the first corner = the side wall conductive pad layer 307a is mainly used for circular diagrams]-the sharp corner formed by the first conductive layer 305c. The inter-gate dielectric layer 308 is formed on the inter-gate dielectric layer, as shown in FIG. ^ J1, and then-a first overlying conductive layer dielectric layer 308 system-on top of the dioxide. The thickness between the gates mentioned above is composed of the meso / (N0) structure and its equivalent SiO2 layer is 309a, which is doped with polycrystalline ^ ^ f and third conductive

堆积 I 2 is composed of non-day and night and uses LPCVD to conduct a third conductive sound ^ 9 between \ gate ^ angstrom and 3 0 0 angstrom, the 亀 layer 3 0 9 is first deposited on the inter-gate dielectric layer 308 Zilitian rMD, + or the traditional etch-back method will stack the third lead: the first covering conductive layer 310 described by the CMP method is planarized by the silicidation force. On- ^ «LPCVD ^ ^ ^ ^ ^ (W ^ ^ ^ 4_Angstrom. Here it can be clearly f to: the measuring Angstrom and the gate structure has an ancient eight μ should + auto-aligned floating dagger: J front technology One of the non-automatically aligned floating screens first stops, and the extended floating system requires a secondary angle system that uses the thin side.

Page 13 569395 V. Description of the invention (9) The side wall conductive pad layer 307a is rounded to eliminate the field emission effect and reduce the reliability problem of the gate dielectric layer 308. A cross-sectional view along each of the plurality of active regions, and an F-F 'line shown in Fig. 3F is shown in Fig. 4A. It is worth mentioning here that FIGS. 3A to 3F only disclose an example of an auto-aligned floating gate structure that forms a high coupling ratio. Several modified methods can also use a mask photoresist step to form an automatically aligned floating gate structure. The first example (not shown) is the planarized second conductive layer 305a shown in Figure 3D. Etching back a thickness of the formed first mask dielectric layer 303a to form an etched back second conductive layer 305b with a top surface higher than the formed first conductive layer 3 0 2a, and then performing FIG. 3E and FIG. 3 F process; the second example (not shown) is a pair of side wall conductive pads formed on the side wall of the etch-back gap of each of the plurality of shallow groove isolation areas shown in FIG. 3C. The etched back second conductive layer 3 0 5 b and the first side wall dielectric pad layer 3 6 6a are replaced instead of FIG. 3D, and then the first mask dielectric layer 3 0 3a is formed and removed. Then, the processes of FIG. 3E and FIG. 3F are performed. Please refer to FIG. 4A to FIG. 4B, which disclose the process steps and cross-sections of an automatically aligned floating gate structure formed after FIG. 3F to manufacture a contactless non-harmonic flash memory array of the present invention. Figure 2A and Figure 2B shows a stack gate cell structure with an oblique floating gate layer as a memory cell. FIG. 4A shows a second mask dielectric layer 3 1 1 formed on the first covering conductive layer 3 1 0 of a stacked gate structure shown in FIG. 3F. It is worth emphasizing here that the second mask dielectric layer 311 can be formed on another type of self-aligned floating gate structure with high coupling ratio or other types of the prior art.

Page 14 569395 V. Description of the invention (10) Non-automatic alignment on the floating gate structure. The above-mentioned second mask dielectric layer 3 i i is composed of silicon nitride and is deposited by the LPCVD method, and its thickness is between 50 angstroms and 100 angstroms. It is worth noting here that a thin silicon dioxide layer (not shown) can be formed on the first cover conductive layer 31 to improve the second mask dielectric layer 311 formed on the first cover conductive layer 310. Closeness. FIG. 4B shows that a plurality of interconnected source / drain regions (ISD) are alternately formed to form a plurality of gate stack shafts (GS), wherein each of the plurality of gate lock shafts (GS) described above includes at least A shaped second mask dielectric layer 3 11 a, a composite control gate layer 3 1 0 a / 3 0 9b as a word line (WL), a shaped gate dielectric layer 3 0 8 a, and a plurality of oblique Angular floating gates 3 0 2 b, 3 0 7 b, 3 0 5 d (3 0 7 b and 3 0 5 d as shown in Figure 5C), and then connect the source / drain diffusion zone 3 1 2 a A high-dose dopant of the second conductivity type is implanted in the semiconductor substrate of the plurality of active regions across the formed oblique floating gate structure and the penetrating dielectric layer 3 0 1 in an automatic alignment manner. 300 surface, followed by a first planarized oxide layer 313a is formed in each void of the plurality of connected source / drain regions (ISD). The above semiconductor substrate includes at least _ wells 3 0 0b formed in an η well 3 0 0a (not shown), as shown in FIGS. 2a and 2B. The inclined angles Θ of the above-mentioned inclined floating gate layers 302b, 307b, and 305d are between 90 degrees and 60 degrees. The dopant of each of the above-mentioned multiple connected source / diffusion diffusion regions 3 1 2 a is arsenic or phosphorus and the dose of its ion implantation is between 1 0 15 / cm 2 and 5 × 1 0 15 / cm 2. between. It can be clearly seen here that the dopant distribution of each of the above-mentioned plurality of connected source / drain diffusion regions 3 1 2a will be laterally graded, and the laterally ly graded

Page 15 569395 V. Description of the invention (π) The width of the gradient-connected source / diffusion diffusion zone 3 1 2a can be controlled by the energy of an ion implant. The above first planarized oxide layer 3 丨 3a is composed of stone dioxide, glass-filled, or shed glass, and is stacked using LPCVD, HDPCVD, or PECVD. First, a thick dioxide fragment 3 is deposited. 3 to fill each gap between the formed second mask dielectric layer 3 1 1 a and then use the CMP method to planarize the thick silicon dioxide layer 3 1 3 and form the first layer in 5 MH. 'The mask dielectric layer 311a serves as a flattening stop layer. It is worth mentioning here that before the first planarized oxide layer 313a is formed, a thermal oxidation process can be performed to form a thin silicon dioxide layer on the side wall of the gate stack, including the oblique angle. Floating gates 30 2b, 3 05d, and 3 07b. The width of the connection source / drain area (ISD) and the minimum line width (F) of the technology used in the brake stack shaft (GS) can be defined; and the string selection area in the illustration (SSR) and ground selection area (GSR) can be defined as X i X 2 F, where XX 2 is a scaleable coefficient and its value is between 2 and 4. The above-mentioned string selection area (SSR) includes at least two string selection gate areas (SSG) and a common leakage area (CDR) located between the two string selection gate areas (SSG). The above-mentioned ground selection gate area (GSR) includes at least two ground selection gate areas (GSG) and a common source area (cSR) located between the two ground selection gate areas (GSG). It is worth mentioning here that the string of flash memory cells located between the string selection area (SSR) and the ground selection area (GSR) can be 1, 6, 2, 6, 4 or more. Stacked gate cells. FIG. 4C shows that a non-criticai photoresist PR 3 is covered on each of the cell strings to serve as an etched mask to selectively and sequentially remove the selection regions located in the string ( SSR) and the ground

Page 16 569395 V. Description of the invention (12) The shaped second mask dielectric layer 311a of the f-selected (GSR) region, the shaped first covering conductive layer 310a, the planarized third conductive layer 309b, and the shaping The inter-gate dielectric layer 3 0 8 a, and then the first conductive type dopant is implanted in the string selection across the formed first conductive layer 30 2 b and the penetrating dielectric layer 301 a in an automatic alignment manner. Area (SSR) and the ground selection area (GSR) in the active area of the semiconductor substrate 300 to form an ion implantation area (not shown). Then the mask photoresist PR3 is removed. The above-mentioned ion implantation region may include a shallow ion implantation region as a threshold voltage adjustment of the selective gate transistor and a deep ion implantation region to form a punch-through stop region of the selective gate transistor. ). The above-mentioned implants are doped with boron or boron-fluoride impurities. FIG. 4D shows that an etch-back second covering conductive layer 314b is formed within each of the string selection region (SSR) and each of the ground selection region (GSR). Then a pair of first side walls The electrode layer 3 1 5 a is formed on a side wall adjacent to the first planarized oxide layer 313 a and is disposed on each of the string selection region (SSR) and each of the ground selection region (GSR). The remaining second covering conductive layer 314 b is over a part of the surface to define a pair of string selection lines (SSL) 3 14c within each of the string selection area (SSR) and a pair of ground selection lines ( GSL) 3 14c is within each of the ground selection regions (GSR). The above-mentioned etch-back second cover conductive layer 314b is composed of tungsten silicide (WSi 2) or crane (w) and is deposited by LPCVD method or sputtering method. A thick second cover conductive layer 314 is first deposited on the string. SSR and each gap of the ground selection region (GSR), and then use the CMP method to planarize the thick second overlay conductive layer 314 and use the formed second mask dielectric layer 3Ua

Page 17 569395 V. Description of the invention (13) ~ '' A flat stop layer is formed to form a planarized second cover conductive layer 314a, and the second planar cover conductive layer 314a is etched to be equal to the formed first conductive layer 310a. The top surface is horizontal. The above-mentioned second side wall dielectric 31a is composed of silicon nitride and is deposited by the lPCVD method. It is a second dielectric layer 315 which is deposited on the surface of a formed structure and then is deposited. A thickness of the dielectric layer 315. One picture four E shows that a non-rigorous mask photoresist step (pR4) is performed to form, and the mask photoresist PR4 is on each of the cell strings and adjacent to the second side pair = ^ electrically cushion layer 3 1 5a On a part of the surface, and then the etched back second conductive layer between the u-side wall dielectric pad layer 315a is removed first, and then the extended second conductive layer 30c is removed anisotropically And the thin layer, the wall conductive pad layer 307a and the top surface level of the first conductive layer 302b etched to form the first / first protruding field oxide layer 304b (see FIG. 3E), and then etch back the The first dog field oxide layer 3041} to the T 4 surface level of the penetrating dielectric layer "Ia" to form a second protruding field oxide layer 304c, and then the remaining formed first conductive layer is removed 3 〇2b; Then, a β sub-planting is performed with an auto-aligned fraction to form a plurality of lightly doped co-leakage diffusion regions 3 1 β & The pair of second in each of the string selection regions (SSR) The surface of the half-body substrate 300 between the sidewall spacers 315 & and each of the plurality of lightly doped common source diffusion regions 3 1 6a to 4 ground selection region (gsR) The surface of the semiconductor substrate 300 between the pair of second sidewall spacers 315a. The implanted dopant is j or arsenic, and the implanted dose is between 10 13 / cm 2. And 5x 1 0 14 / cm 2. As can be clearly seen from Figure 4E, the width of the string / ground selection line (SSL) 31 5a is determined by the second side wall dielectric pad 315a.

Page 18 569395 V. The description of the invention (14) cushion layer width, and the selection gate layer 302c, 305e, 307c is a single-sided oblique angle floating gate structure with a larger channel length and a narrower string / Ground selection line 31 4c (SSL / GSL). Figure 4F shows that the mask photoresist PR4 is removed, and then a pair of third side wall dielectric pads 3 1 7a are formed on the pair of second side wall dielectric pads 3 1 7a, the string / ground Each of the selection line 314c and the selection gate layer 3 0 2c, 3 0 5e, 3 0 7c is placed on the side wall of the common source / drain area (CSR) / (CDR), The dielectric layer 301 a and a portion of a flat surface alternately composed of the second protruding field oxide layer 304 c; and

A high dose of a dopant of the second conductivity type implanted on the surface of the semiconductor substrate 300 of the active region is implanted across the penetrating dielectric layer 3101 in an automatic alignment manner to form a high The doped common source / drain diffusion region 3 1 6 b is within each of the lightly doped source / non-diffusion region 3 1 6 a; then, using an anisotropic dry etching method or diluting the hydrofluoric acid The bubble immersion method removes the penetrating dielectric layer 30 la between the pair of third side wall ^ layers 31 7a and simultaneously etches the second = field oxide layer 304c to form a third protruding field oxide Layer 304d; the wall interposed between the planarized fourth conductive layers 31 8a is formed in the gap between the pair of third sides 3 times the structure pad layer 31 ^. The above-mentioned third side wall dielectric pad layer is composed of > ^ oxidized fragments and stacked using LPCVD method, which is firstly deposited by stacking two dielectric layers 317 on a formed structure surface. A thickness of the four-conducting second dielectric layer 317 is returned again. The above-mentioned planarization product is composed of doped polycrystalline silicon and used LPCVD method to stack a thick fourth conductive layer 318 to fill the third layer of cushion layer. Each gap between 3 1 7a is reused by the CMP method.

Page 19 569395 V. Description of the invention (15) The thick fourth conductive layer 318 is flattened and the formed second cover layer 3 1 1 a is used as a smoothing stop layer. The dopant implanted in the above-mentioned highly doped common source / diffusion diffusion region 3 1 6b is arsenic or phosphorus, and the implanted dose ranges from 1015 / cm2 to 5x1015 / cm2. between. It is worth mentioning here that the planarized fourth conductive layer 318a is placed in each of the common source regions (CSR) by the highly doped common source diffusion region 316b and the third protruding field oxide layer. Above the first flat bed composed of 3 0 4d alternately and placed on each of the co-drained regions (CDR), the highly doped co-drained diffusion region 31 6b and the third protruding field oxide layer 304d Alternately composed on a second flat bed. FIG. 4G shows that the planarized fourth conductive layer 3 1 8 a located in each of the common source / drain regions is selectively etched back to a predetermined thickness to form a fourth conductive layer 318 b, and then automatically A high-dose dopant of the second conductivity type is implanted in the aligning fourth conductive layer 3 18b in an aligned manner; then, a planarized third covering conductive layer 3 9a is formed in the pair of third Side wall dielectric cushion layer 3 1 7 a; then, using a non-rigid mask PR5 (not shown) to selectively etch back the planarized third located in the common source region (CSR) Cover the conductive layer 3 1 9 a to another predetermined depth to form a common source conductive pipeline 319b / 318b, wherein the mask photoresist PR5 is placed on the common leakage area (CDR); then the mask photoresist is removed pR5; Next, a second planarized cover oxide layer 32 0a is formed on each of the common source conductive lines 31 9b / 318b. The above-mentioned planarized third cover conductive layer 319 a is composed of tungsten silicide (WSi 2) or tungsten (W) and is deposited by LpCVD method or sputtering method. First, a thick third cover conductive layer is deposited. 3 丨 9 To fill the common source

Page 20 569395 V. Description of the invention (16) / Each void in the leakage area is then planarized by using the CMP method to deposit the thick third covering conductive layer 3 1 9 and forming the second mask dielectric layer in this way. 311 & acts as a smooth stop layer. The above-mentioned second planarized cover oxide layer 320a is composed of silicon dioxide, phosphor glass, or borophospho glass and is deposited by LPCVD method, HDPCVD method, or PECVD method. First, a thick oxide layer 320 is deposited to fill Each gap that fills the common source area is planarized by the CMP method, and the formed second mask dielectric layer 311a is used as a flattening stop layer. FIG. 4A shows that a metal layer 321 is formed on the structural surface formed by the one shown in FIG. 4G and is placed with the planarized third covering conductive layer 319a on the fourth conductive layer 318b at the same time through a mask. A photoresist (pR6) (not shown) is preformed to form a complex metal bit line 32 1 a (BL) and a planar co-foam conductive island 319c / 318 c integrated connection. The above-mentioned metal layer 3 2 1 is composed of at least one aluminum (A1) or copper (Cu) layer placed on a barrier metal. The above mask photoresist step pR6 includes at least a plurality of third mask dielectric layers 322a formed by the multiple mask photoresist PR6 aligned on the multiple active area (AA) and a fourth side wall dielectric. The ytterbium layer 323a is formed on each side wall of the plurality of third mask dielectric layers 3 2 2 a to reduce misalignment, as shown in FIG. 5b to FIG. 5E. From FIG. 3A to FIG. 3F and FIG. 4A to FIG. 4η, the contactless non-harmonic flash memory array of the present invention requires only three rigorous mask photoresist steps to be manufactured, compared with at least six in the prior art. Rigorous mask photoresist steps. It is worth mentioning here that before the metal layer 321 is not stacked, the formed second cover dielectric layer 3 1 1 a and the second side wall dielectric cushion layer 3 1 5 a can be added with high temperature phosphoric acid.

Page 21 569395 V. Description of the invention (17) Selectively remove and then back-fill planarize the third covering oxide layer (not shown) to reduce the capacitance between the bit line 3 2 1 a and the word line and string selection line. . Please refer to FIG. 5A, which discloses a brief top view of a non-contact non-NAND flash memory array of the present invention. A cross-sectional view indicated by an AA line is shown in FIG. 4; B-B, a cross-sectional view of the line is shown in Fig. 5B; a cross-sectional view along a line CC-C 'is shown in Fig. 5C; a cross-sectional view along a line D-D' is shown In Figure 5d; and a cross-sectional view along an Ε-Ε 'line is shown in Figure 5ε. Figure 5A shows that the active region (AA) and the shallow groove isolation region (sti) are alternated. The ground is formed; the complex digital line (WL) is perpendicular to the active area (AA), wherein the parent of the complex digital line (WL) mentioned above includes "a composite control gate layer 310a / 3 0 9b formed in The plurality of automatic alignments are above the floating gates 302b, 30 5d, and 3 0 7 b, as shown in FIG. 5D, and each of the plurality of automatic alignments is located at each of the floating gates 3 0 2b, 3 5 5d, and 3 0 7b. A beveled floating gate structure is indicated by the dotted line; a pair of string selection lines (SSL) 314c and a pair of ground selection lines (GSL) 3 1 4 c For each side of the cell string, the above-mentioned pair of pairs / ground selection lines 3 1 4 c at least include a plurality of single-sided oblique floating chambers 302c, 305e, and 307c as shown in Figure 5C; The conductive island 3 1 9 c / 3 1 8 c is formed between a pair of third side wall dielectric plutonium layers 3 1 7 a and is placed at least on the common metallocene diffusion region 316b / 31 6a. The bit lines 321a are simultaneously formed. 'Each of the above-mentioned plural metal bit lines (BL) 321a is formed by a third mask dielectric layer 322—above the active area (AA) and a fourth side edge. A wall dielectric layer 323a is formed on the third mask dielectric

Page 22 569395 V. Description of the invention (18) Each side wall of the layer 322a is formed, as shown in Fig. 5b; and a common source conductive pipeline 3 1 9b / 3 1 8b is formed in the third pair Above a first flat bed between the side wall dielectric pads 317a, wherein the above first flat bed is alternately oxidized by a common source diffusion region 3 丨 6b / 3 丨 6a and a third protruding field The alternating layer composition of the physical layer 3 0 4 d is shown in Fig. 5. Figure 5B shows a cross-sectional view along the plane of the common leakage conductive island 3 丨 9c / 3 1 8c as shown by a line B-B in Figure 5A, in which the metal bit line 3 2 1 a Each of them is integrated with the planarized common leakage conductive island 3 1 9 c / 3 1 8 c and is aligned above the active area (AA) and a first through a third mask dielectric layer 323 a. Four side wall dielectric pads 323a are formed on each side wall of the third mask dielectric layer 323a to reduce misalignment; the planarized common leakage conductive island 3 1 9c / 3 1 8c is formed at least on Having a highly doped co-drained diffusion region 3 1 6b formed on a co-drained diffusion region 3 1 6 b / 3 1 6 a formed within a lightly doped co-drained diffusion region 3 1 6a; and a first The two flat beds alternately consist of a highly doped co-drained diffusion region 3 1 6 b and a third protruding field oxide layer 304d. FIG. 5C shows a cross-section view along a string selection line (SSL) 3 1 4 c as indicated by a BB ′ line in FIG. 5A, in which the above-mentioned _selection line (SSl) 3 14c is placed by An automatically aligned floating gate layer 3 2c, 3 5e, 3 07 and a first protruding field oxide layer 3 0 4b alternately on a surface; a second side wall dielectric pad The layer 3 1 5a is formed on the string selection line 3 14c to define the width of the string selection line (SSL) 3 14c; the metal bit line 3 2 1 a is formed on the second sidewall dielectric layer. 315 a and formed by the above-mentioned mask photoresist step (PR6); and the _select gate 302c

Page 23 569395 V. Description of the invention (19) Each system is formed on a penetrating dielectric layer 3 0 1 b adjacent to the first protruding field oxide layer 3 04 b. It can be clearly seen here that the string selection line 3 1 4c is connected to the metal-oxide half-field-effect transistor gate integration, which is different from the connection to the flash memory element in the prior art. FIG. 5D shows a cross-section view along a word line (WL) as shown in FIG. 5A, one of the D-D, lines, in which an automatically aligned floating gate structure with a high coupling ratio is formed as shown in FIG. Above the shallow groove isolation structure shown by 3F; a formed second mask dielectric layer 3 1 1 a is formed on the composite control gate layer 310 a / 3 0 9b; and the metal bit line 32 The la series is formed on the forming second mask dielectric layer 311a and is formed by the mask photoresist step (PR6) described above. FIG. 5E shows a cross-section view along an E-E 'line shown in FIG. 5A along a common source conductive pipeline 3 1 9b / 3 1 8b, where the above-mentioned common source conductive pipeline 3 1 9b / 3 1 8b is formed on a first flat bed consisting of a third protruding field oxide layer 3 04d and a common source diffusion region 316b / 31 6a, and the common source diffusion region 3 1 6 b / 3 1 6 a includes at least one highly doped common source diffusion region 3 1 6b formed in a lightly doped common source diffusion region 3 1 6a; a second planarized cover oxide layer 32 0a is formed in the The common source conductive pipeline 3 1 9 b / 3 1 8 b; similarly, the metal bit line is formed on the second planarized cover oxide layer 320 a and passes through the above-mentioned mask photoresist step ( PR6). It can be clearly seen here that the common conductive pipeline 3 1 9b / 3 1 8b has a lower pipeline resistance than the buried diffusion line of the prior art and a lower pipeline capacitance of 300 compared to the semiconductor substrate.

Page 569395

Page 25 569395 Brief Description of the Drawings Figures A and B show a schematic diagram of a traditional stacked gate flash memory cell structure and its writing and scrubbing in a NAND flash memory array, of which Figure 1 A shows a writing state and FIG. 1B shows a scrubbing state. FIG. 2A and FIG. 2B show a non-and-type flash memory array of a stack gate flash memory cell structure of the present invention and its writing and A brief diagram of scrubbing, wherein FIG. 2A shows a writing state and FIG. 2B shows a scrubbing state. FIG. 3A to FIG. 3F show the manufacturing steps and cross-sectional views of a shallow groove isolation structure with an automatic alignment floating gate structure for manufacturing a non-harmonic flash memory array of the present invention. FIG. 4A to FIG. 4B show the process steps and cross-sectional views of the NAND flash memory array of the present invention following FIG. 3F. FIGS. 5A to 5E disclose a brief top layout diagram and a sectional view of the present invention, wherein FIG. 5A reveals a brief top view of FIG. 4A; FIG. 5B reveals a line B along FIG. 5A -A cross-sectional view of the line Β '; Figure 5C reveals a cross-section view along a line C-C' shown in Figure 5A; Figure 5D illustrates a line D-D 'shown in Figure 5A A cross-sectional view of FIG. 5; and FIG. 5E discloses a cross-sectional view along an E-E 'line shown in FIG. 5A. Comparative illustration of drawing numbers: 300 semiconductor substrate 301b penetrates dielectric layer 302b beveled first conductive layer 302c unilateral beveled first conductive layer

Page 26 569395 Brief description of the diagram 3 0 3a First mask dielectric layer 3 0 4a Planar field oxide layer 3 0 4b First protruding field oxide layer 3 0 4c Second protruding field oxide layer 3 04d Three protruding field oxide layer 3 0 5a planarized second conductive layer 305b etched back planarized second conductive layer 305c extended second conductive layer 3 0 6 a first side wall dielectric pad layer 3 0 7 a thin side Wall conductive pad layer 3 0 8 a forming inter-gate dielectric layer 3 0 9 a planarization third conductive layer 309 b forming planarization third conductive layer 310 a forming first covering conductive layer 311 second covering dielectric layer 311 a forming first Second cover dielectric layer 3 1 2 a Connection common source / drain diffusion area 3 1 3 a First planarized cover oxide layer 314b Etching back second cover conductive layer 314c String / ground selection line 3 1 5a Second side Wall dielectric pad 3 1 6a lightly doped common source / drain diffusion region 3 1 6b highly doped common source / drain diffusion region 3 1 7a third side wall dielectric pad layer 318a planarization fourth conductive layer 318b back Etch planarization fourth conductive layer 318c etch back planarization fourth conductive island 319a planarization third covering conductive layer 319b etch back third covering conductive layer 319c planarization third covering conductive 320a 321a covering second planarized metal bit line 322a forming the third oxide layer a dielectric layer mask fourth side wall 323a of the dielectric underlayer

Page 27

Claims (1)

569395 VI. Scope of patent application 1. A stacked gate cell structure of a non-flash memory array, including at least: a semiconductor substrate of a first conductivity type having an active region formed in two shallow grooves to isolate ( STI) region; a gate stack is formed on the semiconductor substrate, wherein the above gate stack includes at least a composite control gate layer formed on an inter-gate dielectric layer, and the inter-gate dielectric layer is formed on An oblique-angle floating gate layer and a portion of the surface of the two first protruding field oxide layers of the two shallow groove isolation regions, the oblique-angle floating gate layer having a main portion formed on the active layer A penetrating dielectric layer and two extending portions of the region are respectively formed on the surfaces of the other portions of the two first protruding field oxide layers in the two shallow groove isolation regions; and A laterally-gradient-connected source / drain-diffusion region of the second conductivity type uses the gate stack as an ion implantation mask to implant a high dose of the semiconductor substrate doped in the active region in an automatic alignment manner. 2. The surface of the patent application to form a range of item 1 of cell structure and the gate stack, wherein said semiconductor substrate are of a well formed in a P well of the η. 3. The stacked gate cell structure described in item 1 of the scope of the patent application, wherein the above composite control gate layer includes at least one Shi Xihua town (WS i 2) or iron (W) layer formed in a doped complex On top of crystalline or doped amorphous silicon. Page 28 569395 6. Application scope of patent 4. The stacked gate cell structure as described in item 1 of the scope of patent application, wherein the inter-gate dielectric layer is a silicon dioxide-silicon nitride-silicon dioxide ( 〇 N 0) structure or a silicon nitride-silicon dioxide (NO) structure and its equivalent silicon dioxide thickness is between 60 angstroms and 200 angstroms, and the penetrating dielectric layer is a thermal The silicon dioxide layer or a thermally nitrided silicon dioxide layer has a thickness between 60 angstroms and 120 angstroms. 5. The stacked gate cell structure according to item 1 of the scope of the patent application, wherein the above-mentioned oblique-angle floating gate layer is composed of doped polycrystalline silicon or doped amorphous silicon and uses anisotropic dry etching. To form an oblique angle between 0 and 60 degrees. 6. The stacked gate cell structure described in item 1 of the scope of the patent application, wherein the two extensions of the above-mentioned oblique-angle floating gate layer are formed by two first gates formed on the side wall of the active area. An etch-back second conductive layer on one side wall dielectric pad layer disposed on the two first protruding field oxide layers is defined or conductive by two side wall walls formed on the side wall of the active region A cushion layer is formed and a thin side wall conductive cushion layer is formed on the side walls of the two extensions to reduce the sharp-angle field emission effect. 7. A non-contact non-harmonic flash memory array, at least comprising: a semiconductor substrate of a first conductivity type having a plurality of active regions and a plurality of shallow groove isolation regions alternately formed; a plurality of cell cell string regions alternately A ground is formed on the semiconductor substrate, and Page 29 569395 VI. Each of the above-mentioned plural cell string areas in the scope of the patent application is located between a string selection area and a ground selection area and contains at least a plurality of brake stack shafts and a plurality of connection source / discharge area alternating grounds. Forming; each of the plurality of gate stack shafts includes at least one formed second cover dielectric layer formed on a composite control gate layer, the composite control gate layer formed on a gate dielectric layer, the gate An inter-dielectric layer is formed on the first oblique field oxide layer between the plurality of oblique-angle floating gates and the adjacent oblique-angle floating gates, and the plurality of oblique-angle floating gates are formed in the penetration of the plurality of active regions Above the dielectric layer and on a portion of the surface of the first protruding field oxide layer in the plurality of shallow groove isolation regions, wherein each of the above-mentioned plurality of oblique-angle floating gate layers includes at least one major portion formed Above the penetrating dielectric layer and two extension portions are respectively formed on a portion of the surface adjacent to the two first protruding field oxide layers; each of the plurality of connected source / drain regions includes at least one Second lead Electrically-connected multiple source / diffusion diffusion regions are automatically aligned across the penetrating dielectric layer and the oblique portion of the oblique floating gate by implanting a high dose of dopants in the complex active region. A surface of the semiconductor substrate is formed between the laterally gradient impurity distribution of each of the plurality of connected source / drain diffusion regions and a first planarized silicon dioxide layer is formed between the adjacent second mask dielectric layers; the ground The selection area includes at least a pair of ground selection gate areas, which are defined by a pair of second side wall dielectric pads, and a common source area is formed between the pair of ground selection gate areas. Each includes at least one ground selection line formed on the plurality of unilateral oblique angle floating gates and the first protruding field oxide layer between adjacent unilateral oblique angle floating gates and Page 30 569395 6. Scope of patent application The plurality of unilateral oblique angle floating gate layers are formed on the penetrating dielectric layer in the plurality of active regions and the first protruding field oxidation in the plurality of shallow groove isolation regions. A part of the surface of the material layer; the common source region includes at least a plurality of lightly doped common source diffusion regions of the second conductivity type formed on the surface of the semiconductor substrate of the plurality of active regions, and a pair of third sidewall spacers; An electrical pad is formed on the side walls of the pair of ground selection gates and is placed on a portion of a flat surface composed of the penetrating dielectric layer and a second protruding field oxide layer. A common source conductive line is formed on a first flat bed between the pair of third side wall dielectric pads, and a second planarized silicon dioxide layer is formed on the common source conductive line. On each of them, the above-mentioned first flat bed is formed by a highly doped common source diffusion region within each of the plurality of lightly doped common source diffusion regions and an alternating third field oxide layer Ground composition; the string selection area is at least A pair of string selection gates is defined by the pair of second side wall dielectric pads and a common leakage region is located between the pair of string selection gates, where the above string selection gates include at least one string selection Lines are formed on a plurality of unilateral oblique-angle floating gates and the first protruding field oxide layer between adjacent unilateral oblique-angle floating gates and the plurality of unilateral oblique-angle floating gates are formed on the plurality of active Above the penetrating dielectric layer and on a portion of the surface of the first protruding field oxide layer in the plurality of shallow groove isolation regions; the common leakage region includes at least the second conductivity type A doped co-bleed diffusion region is formed on the surface of the semiconductor substrate of the plurality of active regions, the pair of third side wall dielectric pads are formed on the side walls of the pair of string selective gate layers, and Page 31 569395 6. The scope of the patent application is placed on a part of a flat surface composed of the penetrating dielectric layer and the second protruding field oxide layer alternately, and a plurality of planarization and common leakage conduction An island is formed at least on the plurality of highly doped co-drained diffusion regions between the pair of third side wall dielectric pads, wherein each of the above-mentioned plurality of highly doped co-drained diffusion regions is formed on the plurality of lightly doped co-drained diffusion regions. Within each of the hetero-common leakage diffusion regions; and the plurality of metal bit lines are connected to the planarized common-leak conductive islands and are formed by a mask photoresist step, wherein the above-mentioned mask photoresist step At least a plurality of third mask dielectric layers are aligned on the plurality of active regions to form a fourth side wall dielectric cushion layer formed on each side wall of the plurality of third mask dielectric layers. . 8. The non-contact non-harmonic flash memory array as described in item 7 of the scope of patent application, wherein the composite control gate layer as a word line includes at least one tungsten silicide (WS i 2) or tungsten (W) layer Formed on a doped polycrystalline silicon or doped amorphous silicon layer. 9. The contactless non-harmonic flash memory array as described in item 7 of the scope of the patent application, wherein the above-mentioned oblique-angle floating gate layer is composed of doped polycrystalline silicon or doped amorphous silicon and uses non-equivalence A dry-etching method is used to form an oblique angle between 0 and 60 degrees. 10. The non-contact non-harmonic flash memory array as described in item 7 of the scope of the patent application, wherein the extension of the above-mentioned oblique floating gate is formed by Page 32 569395 VI. Scope of patent application The first side wall dielectric layer on the side wall of the active area is defined or is formed by the side wall conductive pad formed on the side wall of the active area. The thin side wall conductive cushion layer is formed on the side walls of the two extending portions to round the sharp corners formed. 1 1. The non-contact non-harmonic flash memory array as described in item 7 of the scope of the patent application, wherein the above-mentioned string / ground selection line includes at least one tungsten silicide or tungsten layer and the single-sided oblique floating gate layer is composed of The doped polycrystalline silicon or the doped amorphous silicon is formed by using an anisotropic dry etching method to form an oblique angle between 0 and 60 degrees. 1 2. The non-contact non-harmonic flash memory array as described in item 7 of the scope of patent application, wherein the common source conductive pipeline includes at least one tungsten silicide (WS i 2) or tungsten (W) layer formed in one 13 of the highly-doped polycrystalline silicon or highly-doped amorphous silicon layer. The contactless non-harmonic flash memory array described in item 7 of the scope of patent application, wherein the above-mentioned planarized common-leakage conductive islands include at least A tungsten silicide or tungsten island is formed on a highly doped polycrystalline silicon or highly doped amorphous silicon island, and the metal bit line includes at least a copper (Cu) or aluminum (A 1) layer formed on a barrier metal (Barrier-metal) layer. 1 4. A method for manufacturing a non-contact non-NAND flash memory array, the method at least includes: Page 33 569395 6. The scope of the patent application is to prepare a semiconductor substrate of a first conductivity type; forming a first multi-layered mask structure on the semiconductor substrate, wherein the above-mentioned first multi-layered mask structure is from top to bottom The bottom includes at least a first mask dielectric layer, a first conductive layer, and a penetrating dielectric layer; the first multi-layer mask structure is formed to form a plurality of shallow grooves, wherein the plurality of shallow grooves described above Each is filled with a planarized field oxide layer to form a plurality of shallow groove isolation regions; and the planarized field oxide layer located in each of the plurality of shallow groove isolation regions is selectively etched back to approximately greater than the first A depth of a conductive layer to form a first protruding field oxide layer; forming a pair of each extending the second conductive layer over the first protruding field oxide layer in each of the plurality of shallow groove isolation regions; Forming a first cover dielectric layer on one side portion and forming a thin side wall conductive cushion layer on each of the plurality of shallow groove isolation regions to form a pair of side wall extending the second conductive layer Above A self-aligned floating gate structure is formed; an inter-gate dielectric layer, a planar third conductive layer, a first cover conductive layer, and a second cover dielectric layer are sequentially formed on the self-aligned floating gate. Over the structure to form a second multi-layered veil structure; forming the second multi-layered veil structure to define a plurality of connected source / drain regions located within each of the cell string regions and sequentially removing the second The mask dielectric layer, the first covering conductive layer, the planarized third conductive layer, the inter-gate dielectric layer, and the anisotropically etched auto-aligned floating gate structure to form an oblique-angle floating gate structure Multiple brake stack shafts; Page 34 569395 VI. The scope of the patent application is automatically aligned across the angled portion of the angled floating gate structure between the adjacent stack stack axes and the penetrating dielectric layer. A dose of dopant is formed on the surface of the semiconductor substrate of the plurality of active regions to form a second conductive source / drain diffusion region of a second conductivity type; a first planarized silicon dioxide layer is formed to fill the plurality of interconnects Each gap in the source / drain region; selectively and sequentially removing the formed second mask dielectric layer, the first covered conductive layer, and the planarized layer in each of the string selection region and each of the ground selection region Forming a third conductive layer and forming an inter-gate dielectric layer; forming a planarized second covering conductive layer to fill in the gaps formed by each of the string selection regions and each of the ground selection regions and selectively return Etch the planarized second cover conductive layer to a thickness approximately equal to a thickness of the formed second cover dielectric layer to form an etch-back second cover conductive layer; form a pair of second side wall dielectric pads in the string selection Each of the districts and An adjacent first planarized overlying silicon dioxide layer side wall of each of the ground selection areas is placed on a portion of the surface of the etched back second overlying conductive layer to define a pair of string selection gates. Area within each of the string selection area and a pair of ground selection gate areas within each of the ground selection area; selectively and sequentially removing within each of the string selection area and the ground selection The etched back second conductive layer, the self-aligned floating gate layer, and the first protruding field oxide layer between the pair of second side and side wall dielectric pads within each of the regions to form A flat surface composed of a second protruding field oxide layer and the penetrating dielectric layer alternately; across the pair of second sidewall spacers in an auto-aligned manner Page 35 569395 6. The penetrating dielectric layer is implanted with dopants between the scope of the patent application to form the plurality of lightly doped co-bleeding diffusion regions of the second conductivity type within each of the string selection regions. The surface of the semiconductor substrate of the plurality of active regions and the surface of the semiconductor substrate of the plurality of active regions of the plurality of lightly doped common source diffusion regions of the second conductivity type within each of the ground selection regions form a pair of third Side wall dielectric pads are on the side walls of the pair of string selection gates and the pair of ground selection gates and are placed on a portion of the flat surface. The diffusion pads are diffused to a common source dielectric. The heterocomplex wall is lightly doped with doped margins; the side impurity is high and the internal doping is the first one of the opposite amount. A cross-planted expansion type is mixed with the source layer and a common electric high internal impurity is introduced through a light moving through a number from the type of the complex to the upper conductive region. In the second part of the dispersal area, the electric tank at the metamorphosis formation flat bed exchange penetrates a flat layer to pass through the flat bed. The first level of oxygen is formed into a field and the first layer is formed by a layer of protrusions. The three electric objects and one wall of the upper medial layer of oxygen are on one side of the field, and one of the three regions on the inner side is lateral. Every second second expansion pair is the first. The source should be selected when the mixed ecliptic etched area is selected to be high. The same should be selected and the string should be placed on the side of the bed. The interstitial layer and the three-sided area can be selected from the expansion and erosion, and the heterogeneity of the heterogeneity can be selected; the layer and layer are formed by the electric gap and the ground; the air conduction becomes the first four intersecting groups. The morphology of each # bed level of the system is flattened in the shape of a dioxin, and a layer of oxygen is used to form a cushion in the first field, which is suddenly mediated into three walls and four walls. Third page 36 569395 VI. Patent application scope Each gap between the side wall dielectric pads and selectively etch back the planarized third covering conductive layer in each of the ground selection areas to approximately equal to A top surface of the first covering conductive layer is horizontally formed to form an etch-back third covering conductive layer on the etched-back fourth conductive layer as a common source conductive pipeline; forming a second planarized covering silicon dioxide layer to fill Each gap between the pair of third side wall dielectric pads located in each of the ground selection regions; and forming a metal layer on a formed structure surface and simultaneously forming the metal layer and the The planarized third covering conductive layer is disposed on the etched-back fourth conductive layer to form a plurality of metal bit lines and the planarized common leakage conductive island integrated connection. 15. The method according to item 14 of the scope of patent application, wherein the pair of extended floating gate layers is formed in each of the plurality of shallow groove isolation regions by a pair of first side wall dielectric pads. An etch-back second conductive layer is defined above the first protruding field oxide layer and the pair of first side wall dielectric pads is removed simultaneously with the formed first mask dielectric layer. 16. The method according to item 14 of the scope of patent application, wherein the above-mentioned extended floating gate layer is a pair of side wall second conductive pads formed on each of the plurality of shallow groove isolation areas. The side wall of the planarized field oxide layer is disposed on a part of the surface of the first protruding field oxide layer. 17. The method according to item 14 of the scope of patent application, wherein the above-mentioned pair of strings Page 37 The silicon body that is etched by tungsten etching and chemical conversion is described by the integration of the upper layer and the middle layer, and its cover is covered by silicon. 1 Broken wire, crystal, tube, tube, compound, electric fan, miscellaneous materials, source W, W, C, please request a layer of tungsten, or apply for the same as the guide 2 • 1 • Quad S series 8 W 1 C junction 569395 6. Each of the patent application scope / grounding selection area contains at least one tungsten silicide (WS i 2) or tungsten (W) layer as a string / grounding selection line and a plurality of unilateral oblique angle floating gates are placed in the string / Ground selection line. 19. The method as described in item 14 of the scope of patent application, wherein the above-mentioned planarized common-leakage conductive island includes at least one planarized third covering conductive layer composed of tungsten silicide (WS i 2) or tungsten (W) The island is placed on the etched back fourth conductive island composed of highly doped polycrystalline silicon or highly doped amorphous silicon. 2 0. The method as described in item 14 of the scope of patent application, wherein the mask photoresist step is used to form the plurality of metal bit lines including at least a plurality of third mask dielectric layers aligned with the plurality of active regions. A fourth side wall dielectric underlayer is formed on each side wall of the plurality of third mask dielectric layers. Page 38