TW591764B - Scalable split-gate flash cell structure and its contactless divided diffusion bit-line arrays - Google Patents

Abstract

A scalable split-gate flash cell structure comprises a scalable split-gate region being formed between a common-source region and a scalable common-drain region. The scalable split-gate region comprises a scalable control-gate conductive island having its first portion formed above a scalable floating-gate island with an integrate dielectric layer being formed on its top surface and a poly-oxide layer being formed over its inner sidewall and its second portion formed on a gate dielectric layer with an implant region being formed in a surface portion of a semiconductor substrate. The common-source/scalable common-drain region comprises a common-source/drain diffusion region with or without being divided into a pair of buried source/drain diffusion regions by an etched-back first/second planarized field-oxide layer. Based on the source/drain diffusion structure, three different contactless divided diffusion bit-line arrays are disclosed.

Description

591764 V. Description of the invention (1) (1) The technical field to which the invention belongs The present invention relates to a SP 1 it-gate flash memory structure and its flash memory array, and particularly to a micro flash memory The cell structure is related to the contactless array (divided) diffusion bit line array. (2) In the prior art, a stacked-gate flash memory cell is a cell of an electric crystal and can be based on basic logic work or type (NOR-type), non-type (NAND-type) or and type Array. The above-mentioned non-flash type flash memory array is cascaded by cascading the stacked gate flash memory cells through a common source. Therefore, the number of cells in a string can be made between 5 F 2 and its cell size. However, when the number of cells in a string is increased, the series resistance will increase greatly, which will cause the read speed to decrease. The above-mentioned non-or flash memory array can be formed by bit line contact (c ntac /) 'is made up of parallel flash memory cells. Generally, due to the relationship, the unit cell of the NAND flash memory array is 6F 2, but its read speed is faster than that of the NAND flash memory array. The above-mentioned non-or flash memory array can add the stacked gate cells in parallel and formed in the buried source / diffusion bit except for the bit line contact of each cell. However, the buried mound line system Through a non-selective transistor, a contact connection, two memory cell shrinking and opening type;), separation and separation type (elementary system is recognized to form an AND-type / diffusion region according to a word between When 4 F 2 is increased, the size of the contact between the diffusion line and the fast bit line of the stack gate is larger than that of many fast flash memory thin lines to drain the diffusion bit data lines, and 591764 V. Description of the invention ( 2) The buried source bit line is connected to a common ground diffusion line through a contact point. It can be clearly seen here that the cell size of the NAND flash memory array can be made faster than the NAND flash memory array. The flash memory array is small; in addition, as the number of stacked flash memory cells increases, the read speed of the buried source / diffusion bit line array is much faster than that of the non-flash memory array. Common buried source / diffusion potentials mentioned above A typical example of an array is shown in Fig. 1. A plurality of stacked gate flash cells (10 to 25) are formed between adjacent buried common source / drain diffusion bit lines (BL's). The digital line (WL's) is perpendicular to the buried source / diffusion bit line (BL's). Each of the above-mentioned stack gate flash memory cells (10 to 25) It is written by the channel hot electron injection method (CHEI) and the electrons stored in a floating gate can be penetrated by the Fowler-Nordheim penetration method to the buried layer common source diffusion site Line or a semiconductor substrate for scrubbing. It can be clearly seen here that if the stack gate flash memory cell is further miniaturized, the stack located between the buried layer common source / diffusion bit line There are still some problems to be overcome in the gate flash memory cell: the puncture effect will be a major concern of component miniaturization; when the source / drain junction depth is increased to the micronization, the buried layer co-source / drain diffusion potential The chip resistance of the element wire will be greatly increased; the write efficiency of the channel hot electron injection method is low and a high-density flash The write time of the memory array will become longer; and the over-erase problem of a high-density flash memory array will cause a longer verification time. Therefore, a main object of the present invention is to provide a miniaturizable Minute

Page 7 591764 V. Description of the invention (3) Gate flash memory cell structure and its non-contact discrete diffusion bit line array to eliminate or reduce the above-mentioned miniaturized stacked gate flash memory cell and its fast Problems facing flash memory arrays. (3) Summary of the Invention The present invention discloses a miniaturizable open-type flash memory cell structure and a contactless discrete diffusion bit line array. The above-mentioned micronizable split-type flash memory cell structure is formed on a semiconductor substrate of a first conductivity type and includes at least one micronizable split-type region formed in a common source region and a micronizable common drain region. between. The above-mentioned micronizable gate area is defined by a fourth side wall dielectric cushion layer, which includes at least one micronizable control gate conductive island having a first portion formed above a micronizable floating gate island and The second part is formed on a part of the surface of a gate dielectric layer. The above-mentioned miniaturizable floating gate island is defined by a third side wall dielectric cushion layer and has a gate dielectric. An electrical layer is formed on the top surface thereof, a polycrystalline silicon oxide layer is formed on the inner side wall, and an ion implantation region includes at least one shallow ion implantation region for the adjustment of the threshold voltage and a deep ion A region is planted to form a surface portion of the semiconductor substrate that is formed below a portion of the surface of the gate dielectric layer and penetrates the forbidden region. The above-mentioned common source region includes at least a second conductivity type, a common source diffusion region formed on a surface portion of the semiconductor substrate, and a pair of etched back side wall dielectric pads formed on adjacent micronizable elements. The gate region is on the side wall and is disposed on a part of the surface of the penetrating dielectric layer. Miniaturizable

591764 V. Description of the invention (4) The common sinking area includes at least a common sinking diffusion area of the second conductivity type and a pair of etched back second side wall dielectric pads formed on the sides of adjacent miniaturizable tripping areas. Bet on top. A metal word line is integrated with the conductive island of the micronizable control gate. The metal word line, the conductive island of the micronizable control gate, the inter-gate dielectric layer, and the micronizable floating gate island system are simultaneously connected. Formed by a mask photoresist step. A cell isolation region includes at least an isolation ion implantation region or a shallow groove isolation (ST I) region of the first conductive plastic formed outside the metal word line and located in the common source region and the micronizable Each side surface portion of the semiconductor substrate between the common areas. The above-mentioned common source / and the micronizable common drain region further includes a common source / non-conductive layer formed between the pair of remaining first / second side wall dielectric pads and placed in the common source / drain. A highly doped common source / drain diffusion region of the second conductivity type within the diffusion region and an etched back first / second planarized oxide layer are formed on the pair of etched back first / second sides The semiconductor between the wall dielectric pads and placed on the common source / drain conductive layer or further comprising at least one shallow groove formed between the pair of etched back first / second side wall dielectric monolayers A surface portion of the substrate and an etched back first / second planarized field oxide layer are formed between the pair of etched back first / second side wall dielectric pads. According to the common source / drain diffusion structure, the present invention composes three different contactless separated diffusion bit line arrays. A first type of contactless discrete diffusion bit and line array includes at least a plurality of even-pair buried layer non-diffused bit lines and a plurality of common source conductive pipelines formed in parallel and perpendicular to the plurality of metal word lines. A second type of non-contact separated diffusion bit line includes at least a plurality of common-drain conductive tubes, lines, and a complex pair of buried layer source diffusion bit lines formed in parallel with a plurality of metals.

591764 V. Description of the invention (5) The word lines are perpendicular to each other. A third type of contactless separated diffusion bit line array includes at least a complex even-pair buried layer source diffusion bit line and a complex even-pair buried layer drain bit line formed in parallel and perpendicular to the plural metal word lines . (4) Embodiments of the invention Please refer to FIG. 2A to FIG. 2L, which show the manufacture of the first type of micronizable and switchable flash memory cell structure and the non-contact separated diffusion bit line array of the present invention. Process steps and cross-sectional views. FIG. 2A shows that a penetrating dielectric layer 301 is formed on a semiconductor substrate 3 0 of a first conductivity type; a first conducting layer 3 0 2 is formed on the penetrating dielectric layer 3 0 1 An inter-gate dielectric layer 3 03 is formed on the first conductive layer 3 02; and a mask dielectric layer 3 0 4 is formed on the inter-layer dielectric layer 3 03. The above-mentioned penetrating dielectric layer 301 is a thermal dioxide layer or a nitrided thermal silicon dioxide layer and its thickness is between 80 angstroms and 120 angstroms. The above-mentioned first conductive layer 30 is composed of doped polycrystalline silicon or doped amorphous silicon and is deposited using a low pressure chemical vapor deposition (LPCVD) method. Its thickness is between 100 angstroms and 100 angstroms. Between 3 0 0 0 Angstroms. The above gates = two, three, and three are a layer of stone dioxide-nitride stone-stone dioxide (NONO) layer and / or the thickness of the effective oxide is between 1 Angstrom and 150 Angstroms. The above 3 0 3 can be a thermal polycrystalline silicon oxide (poly-oxide) angstrom emulsified thermal polycrystalline silicon oxide layer and its thickness is between 150 angstroms and LPCVD method. The electrical layer 304 is a silicon nitride layer and its thickness is between 2 gqq Angstrom and Angstrom. Countless Common Source Regions (CSR)

Page 10 591764 V. Description of the invention (6) Resistive (PR1) step (not shown) to form; then, the mask dielectric layer 30 located within each of the plurality of common source regions (CSR) The inter-gate dielectric layer 3 03 and the first conductive layer 3 02 are sequentially removed by using an anisotropic dry etching method. Then, a common source diffusion region 3 05a of a second conductivity type is used. A dopant is implanted across the penetrating dielectric layer 301 in a self-aligned manner within a surface portion of the semiconductor substrate 300 within each of the plurality of common source regions (CSRs). . The common source diffusion region 305a includes at least one highly doped (source-doped) common source diffusion region or a highly doped common source diffusion region formed in a lightly doped (1 ight ly-doped) common source diffusion region. within. It can be clearly seen from Fig. 2 β that a virtual gate region (VGR) is formed between the common source region (CSR) and includes at least a pair of micronizable gates (SSGR) and a micronizable common sink. Regions (SCDRs) are formed between the pair of miniaturizable tripping regions (SSGR). FIG. 2C shows a pair of first side wall dielectric spacers 3 0 6 a formed on the side walls of the adjacent virtual gate area (VGR) and placed in the plurality of common source areas (CSR). On each part of the surface of the penetrating dielectric layer 301. The pair of first side wall dielectric pads 3 0 6 is composed of silicon dioxide and is deposited by LPCVD method. A silicon dioxide layer 3 6 is first deposited on the surface of the structure shown in FIG. 2B. A thickness of 306 of the deposited silicon dioxide layer is etched back. FIG. 1D shows that the penetrating dielectric layer 3 between the pair of first side wall dielectric pads 3 0 6 a located within each of the plurality of common source regions (CSR) uses non-net Add to the dry # engraving method or a dilute hydrofluoric acid bubble immersion method; then, an etch-back second conductive layer 3 0 7b is formed on the pair of first 591764 V. Description of the invention (7) Above the common source diffusion region 30 5a between the dielectric pad layers 30 6a; then, the etchback second conductive layer 3 07b is implanted with a high dose of dopants in an auto-aligned manner. As a dopant diffusion source, a highly doped common source diffusion region 3 05 b of the second conductivity type is formed within the common source diffusion region 3 05 a. The above-mentioned etch-back second conductive layer 3 07b is composed of doped polycrystalline silicon and is deposited by LPCVD method. A thick second conductive layer 3 07 is first deposited to fill the pair of first sides. The gap between the wall dielectric layer 306a 'is planarized by chemical-mechanical smoothing (CMP) method, and the mask "electrical layer 304a is used as a smoothing stop layer, Next, the planarized second conductive layer 3007 is made to have a thickness between 300 angstroms and 15 angstroms. Fig. 2E shows an etched back first conductive layer 3007d formed in the etched back. On top of the second conductive layer 307b, a first planarized oxide layer 3 0 8 a is formed between the pair of first side wall dielectric pads 3 0 6 & Layer 307d. The above-mentioned etch-back first covering conductive layer 307d includes at least tungsten (w) or silicide crane (WSi 2) and is deposited by LPCVD method or sputtering method. The etch-back second conductive layer is used. 3 〇 7 b to form the same process steps. It is worth noting here that the etch-back first conductive layer 3 7 7d together with the etch-back second conductive layer Layer 3 07b constitutes a common source conductive pipeline 3 0 7 (1/3 0 713) to greatly reduce the common source bit line resistance from the buried layer common source diffusion bit line 3051 and 3503. The junction depth of the common source bit line 305b // 3058 can be further miniaturized. The first planarized oxide layer 308 & is made of silicon dioxide and phosphor glass (?-213 ^) Or borophosphoglass (porous-glass) and using LPCVD method, high-density plasma (hdP) CVD or

Page 12 591764 V. Description of the invention (8) Plasma-reinforced (PE) CVD method for stacking, first deposits an oxide layer 308 between the pair of first side wall dielectric pads 30 6a Then, the stacked oxide layer 308 is planarized by the CMP method, and the forming mask dielectric layer 304a is used as a smoothing stop layer. FIG. 2F shows that the shaped mask dielectric layer 3 0 4 a located within each of the plurality of virtual gate regions (VGR) is added and removed by using hot phosphoric acid or an isotropic dry # etch method; then, a The third side wall dielectric cushion layer 3 09a is formed on the outer side wall of the first side wall dielectric cushion layer 3 within the adjacent common source region (CSR) and is placed on the A pair of floating gate regions (FGR) are defined above the side portions of the shaped inter-gate dielectric layer 3 0 3 a within each of a plurality of virtual gate regions (VGR); then, located on the third side of the pair The formed inter-gate dielectric layer 3 03 a and the formed first conductive layer 3 02 a between the wall dielectric pad 3 0 9 a are sequentially removed by using an anisotropic dry-etching method; Then, an ion implantation process is performed in an auto-alignment manner, and a dopant is implanted across the shaped penetrating dielectric layer 30la into the pair of first gates within each of the plurality of virtual gate regions (VGR). A surface portion of the semiconductor substrate 300 between the three side wall dielectric pads 3 0 9a forms an ion implantation region 3 1 0a of the first conductivity type. The pair of third side wall dielectric pads 3 09a is composed of silicon nitride and is deposited by LPCVD method. First, a nitride nitride layer 3 09 is deposited, and then the deposited silicon nitride layer 309 is etched back. A thickness. The above-mentioned ion implantation area 3 1 0a includes at least a shallow ion implantation area as indicated by a dashed line as an adjustment of the boundary voltage and a deep ion implantation area as indicated by a number XXX to form a puncture prohibition area (punch -through stop). Figure 2G shows the locations within each of the plurality of virtual gate areas (VGR).

Page 13 591764 V. Description of the invention (9) The f transparent dielectric layer 30 1 a between the pair of third side wall dielectric pads 3 0 9a is a dilute hydrofluoric acid bubble immersion method or the like. A dry etching method is used to remove it; then, a thermal oxidation process is performed to simultaneously grow a polycrystalline oxide layer 3 1 1 a on each inner side wall of the floating gate layer 3 0 2b and a A gate dielectric layer 3 1 1 W stands on the semiconductor substrate 300 between the pair of third side wall dielectric pads 3 09a within each of the plurality of virtual gate regions (v (j R)). Fig. 2 shows that the pair of third side wall dielectric pads 3 009 are removed by adding hot phosphoric acid; then, an etch-back planarized conductive layer 3 1 2 b is formed in the plurality of virtual gate regions (VGR). On each of the formed inter-gate dielectric layer 3 0 3 b, the polycrystalline oxide layer 3 1 1 a, and the gate dielectric layer 3 1 1 b; then, a pair of fourth sides The side wall dielectric cushion layer 313a is formed on the outer side wall of the first side wall dielectric cushion layer 3 of the adjacent common source region (CSR) on the outer side wall and placed on the violation #planar conductive layer 3 1 2 b The side surface part defines a pair of miniaturizable trip areas (SSGR) and a variable interval between the pair of miniaturizable trip areas (SSGR) within each of the plurality of virtual gate areas (VGR). Micronized common drain region (SCDR). The above-mentioned etch-back planarized conductive layer 312_ is composed of doped = Shi Xi and is stacked using LPCVD & firstly, a thick doped polycrystalline silicon layer 31 2 is filled. Each gap of the plurality of virtual gate regions (VGR) is flattened, and the thick silicon layer 312 stacked by CMP etchback technology is planarized to form a planarized conductive layer. ^ Back: The planarized conductive layer The layer 312a to a predetermined thickness ▲ The side wall dielectric pad 313a is composed of silicon nitride and is stacked in four, and a silicon nitride layer 3 1 3 is deposited first and then returned to etch. Deposited silicon nitride

Page 14 591764 V. Description of the Invention (ίο) A thickness of the layer. From Figure 2F and Figure 2 二, it can be clearly seen that each of the scalable gate openings (SSGR) includes at least one floating gate (FGR) and a selective gate (SGR). FIG. 2I shows that the etch-back planarized conductive layer 3 1 2 b is located between the pair of fourth side wall dielectric pads 3 1 3 a within each of the plurality of virtual gate regions (VGR). Non-isotropic dry etching method is used to add and remove to form a pair of micronizable control gate conductive layers 3 1 2 c; then, an ion implantation process is performed in an auto-aligned manner to pass the dopants across the The gate dielectric layer 311b implants a surface portion of the semiconductor substrate 300 that is doped within each of the plurality of virtual gate regions (VGR) to form a common-drain diffusion region 314a of the second conductivity type. . The above-mentioned common-diffusion diffusion region 31 4a includes at least one highly-doped common-drain diffusion region or a highly-doped common-drain diffusion region formed in a lightly-doped common diffusion region. Figure 2J shows that a pair of second side wall dielectric pads 3 丨 5a are formed on the side walls of the adjacent miniaturizable branching area (SSGR) and placed on the miniaturizable common drain area (SCDR ) Within each of them and located on the side surface of the gate dielectric layer 3 11 b between the pair of fourth side wall dielectric pads 3 1 3a; then, located in the miniaturizable common-sink area (SCDR) the gate dielectric layer 3 1 1 b between the pair of second side wall dielectric pads 3 1 5 a is added and removed by anisotropic dry etching; A shallow groove is formed on a surface portion of the semiconductor substrate 3000 between the pair of second sidewall spacers 315a to form each of the SCDRs. A pair of buried layers within one do not diffuse the bit lines 3 1 4 c; then, a second planarized field oxide layer 3 1 7a fills each of the micronizable common area (SCDR)

Page 15 591764 V. Above the shallow groove in the description of the invention (11). The pair of second side wall dielectric pads 3 丨 5a are composed of silicon dioxide and are stacked by LPCVD method. First, a silicon dioxide layer 3 1 5 is deposited and then the stacked silicon dioxide layer 3 is etched back. A thickness of 1 to 5. The above-mentioned second planarized field oxide layer 317 a is composed of silica, phosphor glass, or borophospho glass and is deposited by LPCVD method, HDPCVD method, or PECVD method. An oxide layer is first deposited 3 1 7 To fill the gaps within each of the SCDRs and then use CMP to planarize the stacked oxide layers 3 1 7 and use the pair of fourth side wall dielectric pads Layer 3 1 3 a acts as a smoothing stop layer. FIG. 2K shows the pair of first side wall dielectric pads 3 0 6 a and the first planarized oxide layer 3 0 8 a located in each of the plurality of common source regions (CSR) and the The pair of second side wall dielectric pads 3 1 5a and the second planarized field oxide layer 3 1 7a within each of the scalable common drain regions (SCDRs) are made by anisotropic dry etching Or wet etching firstly etch back to a top surface level of the micronizable control gate conductive layer 3 1 2c; then, the pair of fourth side walls located within each of the plurality of virtual gate regions (VGR) The dielectric pad layer 3 1 3a is removed by hot phosphoric acid or anisotropic dry etching. Next, a metal layer 3 1 8 is formed on the surface of the structure. The above metal layer 318 includes at least one tungsten (?), Copper ((11) or aluminum (eight 1) layer placed on a barrier metal layer such as a titanium nitride (TiN) or tantalum nitride (TaN). ) And the micronizable control gate conductive layer 312c can be added with silicide (Si 1icided) to form a high temperature resistant metal silicide layer such as titanium silicide (TiSi 2) or cobalt silicide before the metal layer 3 1 8 is formed. (CoSi 2)

Page 16 591764 V. Description of the invention (12) Figure 2L shows that the above-mentioned metal layer 3 1 8 is preformed by a second mask photoresist (PR 2) step (not shown) to form a plurality Metal word line (WL) 3 1 8a; then, the micronizable control gate conductive layer 3 1 2c, the inter-gate dielectric layer 3 03b, the polycrystalline silicon oxide layer 31 la, and the micronizable floating gate layer 3 0 2b is simultaneously formed and sequentially removed by the second mask photoresist (pR2) step to form a scaleable control gate conductive island 3 1 2 d and a scaleable floating gate island 3 0 2 c; Next, an ion implantation process is performed in an auto-alignment manner to form the plurality of isolated ion implantation regions 31 9a (not shown) of the first conductivity type between the plurality of metal word lines (WL) 3 18a and A surface portion of the semiconductor substrate 300 between the common source region (CSR) and the miniaturizable common drain region (SCDR). It is worth noting that the above-mentioned isolated ion implantation area 3 1 9 a can be easily replaced with a shallow groove isolation (ST I) area. Referring now to FIGS. 3A to 3C, it is disclosed that the first type of miniaturizable split-type flash memory cell structure for manufacturing the present invention has a composite control gate conductive layer and a first type of contactless discrete diffusion. The bit line array is followed by the process steps and cross-sectional views of Figure 2J. FIG. 3A shows the pair of first side step dielectric pads 306 a and the first planarized oxide layer 308 a located within each of the plurality of common source regions (CSRs) and the plurality of scaleable common layer The pair of second side wall dielectric pads 3 1 5 a and the second planarized field oxide layer 3 1 7 a within each of the drain regions (SCDRs) are back and forth using non-isotropic dry-etching To remove the curved portion of the first / second side wall dielectric cushion layer 3 0 6 a / 3 1 5 a; then, the pair located within each of the plurality of virtual gate regions (VGR) The fourth side wall interlayer 3 1 3 a is removed by using hot phosphoric acid or an anisotropic dry money engraving method.

Page 17 591764 V. Description of the invention (13) Fig. 3B shows a planar covering conductive layer 3 2 0 a which fills the gaps in each of the plurality of micronizable trip zones (SSGR); then, A metal layer 3 1 8 is formed on the surface of the structure. The above-mentioned planarized conductive layer 320a is composed of tungsten silicide (WSi 2) or tungsten (W) and is deposited by the L P C V D method or the coin plating method. The above-mentioned metal layer 3 1 8 is formed by the same process steps as described in FIG. 2K. FIG. 3C shows that the metal layer 3 1 8 is formed by using a second mask photoresist (PR2) step (not shown) to form a plurality of metal word lines (WL) 3 18a; then, the planarization cover is conductive. Layer 3 2 0 a, the micronizable control gate conductive layer 312c, the inter-gate dielectric layer 3 0 3b, the polycrystalline silicon oxide layer 31 a1, and the micronizable floating gate layer 3 0 2b The second mask photoresist step (not shown) is sequentially removed to form a micronizable composite control gate conductive island 3 2 0b / 31 2d and a micronizable floating gate island 3 0 2c; then, an automatic alignment An ion implantation process is performed in a standard way, implanting dopants between the plurality of metal word lines (WL) 3 18a and between the common source region (CSR) and the micronizable common drain region (SCDR). A plurality of isolated ion implantation regions 319a (not shown) of the first conductivity type are formed on the surface portion of the semiconductor substrate 300 in between. Comparing Fig. 2L and Fig. 3C, it can be clearly seen that the stray capacitance between the metal sub-line (WL) 318a and the common source conductive line 307 d / 3 0 7 b is smaller in Fig. 3C. Please refer to FIG. 4, which shows a hybrid top-view layout diagram of the miniaturizable open-type flash memory cell structure and the first contactless discrete diffusion bit line array of the present invention. As shown in Figure 4, the complex common source conductive pipeline 30 7d / 3 0 7b and the complex even-pair buried-drain diffusion line (BL2) 3 14c

Page 18 591764 V. Description of the Invention (14)

It is formed alternately and perpendicular to the plurality of metal word lines (WL) 3 18a. Each of the plurality of metal word lines (WL) 3 18a described above and the micronizable control gate conductive island 31 2d or the micronizable composite control gate conductive island 320b / located between the micronizable split gate area (SSGR) 31 2d integration link, as indicated by the dashed line with an x. Each of the above common source conductive lines 3 7d / 3 0 7b is formed in a highly doped common source diffusion region between each of a pair of etched back side wall dielectric pads 306b (306c) Each of the buried layers without diffusion bit lines (BL2) 3 1 5c above 3 0 5 b is etched back by a pair of etch backs between the second side wall dielectric pads 315b (315c) The second planarized field oxide layer 3171) (317 (:) is etched to separate; then, each of the plurality of isolated ion implantation regions 3198 is formed on the plurality of metal word lines (WL) 3 as indicated by XXX. 3 1 8 a. The surface portion of the semiconductor substrate 3 0 outside the complex common source region (CSR) and the complex shrinkable common region (§ c DR). Please refer to FIGS. 5A to 5F Among them, the present invention shows that the miniaturizable open-type flash memory cell structure of the present invention has a micro-controllable gate conductive island 3 1 2 d and various first contactless discrete diffusion bit line arrays. Sectional view. A cross-sectional view along the line A-A shown in Figure 4 is shown in Figure 2L. Figure 5A shows the figure 2l marked in Figure 4 A cross-sectional view taken along a line D-D, in which a common source conductive line 3 07d / 307b is a highly doped common source diffusion region 3 formed within a common source diffusion region 3 0 5 a. 〇5 b; an etched back first planarized oxide layer 308b is formed on the common source conductive line 307 (1/3 0 713) and a plurality of metal word lines (several) 318 & alternating A ground is formed on the etched back first planarized oxide layer 308b.

Page 19 591764 V. Description of the invention (15) Figure 5B shows a cross-sectional view of Figure 2L marked along Figure 4 along a line C-C ', one of which etches back the first side wall dielectric cushion layer 3 0 6b is formed on a penetrating dielectric layer 3 0 1 b and is formed on a common source diffusion region 3 5 5a. A plurality of metal word lines (WL) 3 18a are alternately formed on the etch back section. One side wall dielectric cushion layer 3 0 6b. FIG. 5C shows a cross-sectional view of FIG. 4L along a D-D ′ line, where the metal word lines 3 1 8a, which are located within each of the floating gate areas (FGR), The micronizable control gate conductive island 3 1 2d, the inter-gate dielectric layer 3 0 3 c, and the micronizable floating gate island 3 0 2 c are simultaneously formed by a second mask photoresist (PR2) step. And an isolated ion implantation region 3 1 9a implants a dopant on a surface portion of the semiconductor substrate 300 in a self-aligned manner across the penetrating dielectric layer 3 0 1 b. FIG. 5D shows a cross-sectional view of FIG. 4L along the line EE ′, wherein the metal word line (WL) 3 18a is located within each of the selection gate regions (SGR). Together with the micronizable control gate conductive island 31 2d, it is simultaneously formed by the second mask photoresist (PR2) step; an ion implantation region 3 1 0 b contains at least one shallow ion implantation region as indicated by a dashed line. It is marked as the adjustment of the threshold voltage and a deep ion implantation area is marked as χ χ χ to form a barrier dielectric layer formed within each of the selective gate regions (SGR). A surface portion of the semiconductor substrate 300 under 311d; and an isolated ion implantation region 3 1 9 a as described in FIG. 5C is formed between adjacent metal word lines (WL) 318 a A surface portion of a semiconductor board 300. Figure 5E shows one of the two lines marked L in Figure 4 along a line F—F.

Page 20 591764 V. Description of the invention (16) Diffusion bit line 314c is formed in the second section of this etch-back, one of which etches back the second side wall dielectric pad 3 1 5 b on a gate dielectric The layer 3 1 1 d is formed on a buried layer drain and the plurality of metal word lines (WL) 3 1 8 a is on the alternating terrain side wall dielectric pad 31 5b. The material layer 31 7b is formed on each surface; a second cross-sectional view along the line G_G 'shown in FIG. One and a plurality of metal word lines (WL) 318 a of the semiconductor substrate 300 formed by oxygen in a shallow groove are alternately formed on the chemical field oxide layer 3 1 7 b. The invention is a planarized oxide layer material layer 3 0 8 c of each of the B-B 'lines of the micro-condensable control gate conductive island bit line array. Now refer to FIG. 6A to FIG. 6F, which shows The localized split-type flash memory cell structure has different complex cross-sections of a complex 3 2 0b / 31 2b and its first contactless detached diffusion species. FIG. 6A shows a cross-sectional view of FIG. 3C marked in FIG. 4, wherein the remaining first 3 0 8b in FIG. 5A is formed by a thicker etched back first planarized oxide. FIG. 6B A cross-sectional view along line C-C, shown in FIG. 3C shown in FIG. 4 is shown, in which the remaining first side wall dielectric cushion layer 306b in FIG. 5B is formed by a thicker Replaced by the first side wall dielectric layer 306c. Figure 6C shows a cross-sectional view along Figure D-C along a line D-D, shown in Figure 4C. The scaleable control gate conductive island 31 2d is covered with a planarized conductive island 3 2 0b.

Page 21 591764 V. Description of the invention (17) Fig. 6D shows a cross-sectional view taken along the line EE of Fig. 3c marked in Fig. 4, among which the conductive island of the micronizable control gate in Fig. 5D 312 d is covered with a planarized conductive island 32b. FIG. 6E shows a cross-sectional view taken along a line f-F ′ as shown in FIG. 4, wherein the etched back side dielectric spacer 315 b in FIG. 5E is formed by a thicker Instead, the second side wall dielectric pad 3? 5c is etched. FIG. 6F shows a cross-sectional view taken along a line GG, shown in FIG. 4, wherein the etched back second planarized field oxide layer 317b in FIG. 5F is formed by a thicker etched back second plane The chemical field oxide layer 3 1 7 c is replaced. FIG. 7 shows a schematic representation of a hybrid schematic circuit of the scalable micro-flash memory cell structure of the present invention and its first type of contactless discrete diffusion bit line array, in which a plurality of common source conductive pipelines (BL 1) 30 7d / 3 0 7b and plural pairs of buried diffusion bit lines (BL2) 3 14c are formed in parallel and alternately; complex can be miniaturized gated flash memory cell (2 (Π ~ 2 2 5) is formed between the adjacent common source conductive pipeline (BL 1) 3 0 7d / 3 0 7b and the buried drain diffusion bit line (BL2) 314c and the plural metal word line (WL) 318a is common with the plural The source conductive pipeline (BL1) 3 0 7d / 3 0 7b and the complex even-pair buried-drain-diffusion bit line (BL2) 314c are perpendicular to each other and each of the plurality of metal word lines (WL) 3 1 8a is associated with each column Within the micronizable control gate conductive island 312 (1 or the micronizable composite control gate conductive island 3 2 01) // 312 (1 integrated connection. Now refer to FIG. 8A to FIG. 8I, where The invention discloses a miniaturized open-type flash memory cell structure of the present invention and the continuation of the first contactless discrete diffusion bit line array. The two process steps C and a sectional view thereof

Page 22 591764 V. Description of the invention (18) 〇

FIG. 8A shows that the penetrating dielectric layer 3 0 1 between the pair of first side wall dielectric pads 3 0 6 a located within each of the plurality of common source regions (CSR) uses non-equivalence The semiconductor substrate 300 is removed by a dry etching method, and the semiconductor substrate 300 located between the pair of first side wall dielectric pads 3 06a is formed by using an anisotropic dry etching method to form the plurality of common source regions ( A shallow groove within each of the CSR); then, a planarized field oxide layer 3 08d fills the pair of first side walls within each of the plurality of common source regions (CSR) A gap between the dielectric pads 30 6a. It is worth noting here that before the first planarized field oxide layer 3 08d is formed, a thermal oxidation process may be performed to form a liner-oxide layer on a surface of the shallow groove. Defects generated on a shallow groove surface of the semiconductor substrate 300 are eliminated. The first planarized field oxide layer 3 0 8 d can be completed by using the same process steps for forming the first planarized oxide layer 308 a. It can be clearly seen here that each of the common source diffusion regions 3 05 a in FIG. 2C is separated into a pair of buried source diffusion bit lines 3 05 c. Fig. 8B, Fig. 8C, Fig. 8D and Fig. 8E can be easily obtained according to the same process steps described in Fig. 2F to Fig. 2I.

FIG. 8F shows that a pair of second side wall dielectric pads 3 1 5a are formed on the pair of fourth side wall dielectric pads 3 1 3a on the sides of the pair of micronizable control gate layers 3 12c. Over the wall and on the side surface portion of the gate dielectric layer 3 11k placed within each of the SMD; then 'located on the SMD SCDR) within each of the pair of second side bet dielectric layers 3 1 5 a, the gate dielectric layer 3 11 b is by non-isotropic dry type #

591764 V. Description of the invention (19) Engraving or dilute hydrofluoric acid, buffered hydrofluoric acid #engraving method to remove; then, a common draw conductive line 3 1 6d / 3 1 6b is formed in the can Each of the miniaturized common-drain regions (SCDRs) is located on a highly doped common-drain diffusion region 314 b within the common-drain diffusion region 314 a and is described by FIG. 2 d and FIG. 2 e The same process steps for forming the common source conductive line 3 7d / 3 0 7b are formed; then, a second planarized oxide layer 3 7d is formed in each of the micronizable common drain regions (SCDRs). Above the pair of second side wall dielectric pads 3 1 5 a above the common-drain conductive pipeline 3 1 6 d / 3 1 6 b. According to the same process steps described in FIGS. 2K to 2L, FIGS. 8g to 8I can be easily obtained. Similarly, according to the same process steps described in FIGS. 3A to 3C, FIGS. 9A to 9C can be easily obtained. FIG. 10 shows the structure of the miniaturizable open-type flash memory cell and the second type of non-contact discrete diffusion bit line array according to the present invention. A cross-sectional view is shown in FIGS. 8I and 9C. As shown in FIG. 10, the complex common drain pipeline (BL2) 316d / 3 16b is formed alternately; a pair of buried source diffusion bit lines (BL) located within each of the complex common source regions (CSR) 1) 30 5c is an etched back first planarized field oxide layer by using the pair of etched back side wall dielectric pads 3 0 6b (3 0 6 c) as shown in FIG. 8I and FIG. 9C 3 08e (30 8 f) to separate; then, the plural metal word line (WL) 318a is perpendicular to the plural common drain line (BL2) 316d / 31 6b, wherein the plural metal word line (WL) 3 18a Each of them is integrally connected to the conductive island 3 1 2d of the micronizable control gate or the conductive island 32 0b / 31 2d of the micronizable composite control gate;

591764 V. Description of the invention (20) The ion implantation region 31 9a is formed between the common source region (CSR) and the micronizable common sinking region (SCDR) and between adjacent metal word lines (WL) 318a between. Figure 11 A to Figure 11 F shows Figure 8 marked in Figure 10! The various cross-sectional views 'of which FIG. 11A shows a cross-sectional view along a line B_B, marked in FIG. 10; FIG. 11B shows a cross-sectional view along a c_C' line marked in FIG. 10; Fig. 11c shows a cross-sectional view along a DD 'line shown in Fig. 10; Fig. 11d shows a cross-sectional view along an EE line shown in Fig. 10; Fig. 11e shows Fig. 10 A cross-sectional view along a F-F 'line is shown; and FIG. 11p shows a cross-sectional view along a G-G' line shown in FIG. FIG. 11A shows that an etch-back first planarized field oxide layer 3 008 6 is formed on the semiconductor substrate 300 and a plurality of metal word lines (WL) 3 1 8a are alternately formed on the semiconductor substrate 3 0 8. Etch the first planarized field oxide layer 3 0 8e. FIG. 11B shows that an etch-back first side wall dielectric pad layer 306b is formed on a penetrating dielectric layer 3 0 1 b and is formed on a buried layer source diffusion bit line 3 0 5c. A plurality of metal word lines (WL) 3 18a are alternately formed on the etched back sidewall dielectric layer 3 0 6b. FIG. 11C shows each of the plurality of metal word lines (WL) 318a within the floating gate area (FGR), the conductive island 31 2d of the micronizable control gate, and the dielectric layer 3 between gates. 0 3c and the micronizable floating gate island 3 0 2c are formed simultaneously by a second mask photoresist (PR2) step; and an isolated ion implantation region 31 9a crosses the A 30 lb penetrating dielectric layer implants a surface portion of the semiconductor substrate 300 between the adjacent metal word lines (WL) 3 18a.

Page 25 591764 V. Description of the invention (21) FIG. 11D shows each of the plurality of metal word lines (WL) 3 1 8 a located within each of the selection gate regions (SGR) and the micronizable The control gate conductive island 3 1 2 d is formed at the same time by the first mask photoresist (PR2) step, wherein the scaleable control gate conductive island 3 located within each of the selection gate regions (SGR) 1 2 d is formed on the gate dielectric layer 3 11 d; an ion implanted region 3 1 0 b includes at least a shallow ion implanted region as indicated by a dashed line for adjustment of the threshold voltage and a deep ion implanted region The implanted area is marked with χ χ χ to form a surface portion of the semiconductor substrate 300 that is formed under the mother of the plurality of metal word lines (wL) 3 1 8 a. And an isolated ion implantation region 3 1 9 a is formed on a surface portion of the semiconductor substrate 3 0 0 of an adjacent metal word line (ψ [) 3 1 8a. Figure 11E shows an etch-back second side wall dielectric cushion layer 3 丨 5b on top of the far gate dielectric layer 3 1 1 d and is formed in the micronizable common area ($ [j) r A plurality of metal word lines (WL) 318a are formed on each of the common drain regions 31 4a within each of the above), and are formed on the remaining second side wall dielectric layer 315b. FIG. 11F shows a non-conducting pipeline 3 1 6 d / 3 1 6 b formed on each of the second planarized oxide layer 3 丨 7e is formed within each of the micronizable common area (SCDR). On; the common conductive line is formed on a highly doped common diffusion region 3 1 4 b within the common diffusion region 3 1 4 a; and a plurality of metal word lines (WL) 3 18a intersect Variantly formed over the etched-back second planarized oxide layer 3176 within each of the micronizable common area (SCDR). Figures 12A to 12F show various types of Figure 9c marked in Figure 10.

Page 26, 591764 V. Description of the invention (22) The same cross-sectional view, in which FIG. 12A shows a cross-sectional view along a line B-B indicated in FIG. 10, in which the remaining first planarization field is oxidized The physical layer 3 0 8 e is replaced by a thicker etch-back planarized field oxide layer 3 8 8 f; FIG. 12B shows a cross-sectional view of a line “C-C '” shown in FIG. 10 Among them, the first side wall dielectric cushion layer 306 b shown in FIG. 11B is replaced by a thicker first side wall dielectric cushion layer 306 c; FIG. 12C shows A cross-sectional view taken along a line D-D, shown in FIG. 10, in which the conductive island 3 1 2 of the micronizable control gate shown in FIG. 11C is the conductive island 3 1 of the micronizable control gate 2 d is replaced by a planarized conductive island 3 2 0 b; Figure 12D shows a cross-section view along an e_ £, line marked in Figure 10, where the miniaturizable shown in Figure HD The control gate conductive island 3 1 2d is composed of the scalable control gate conductive island 3 1 2d covered with a planarized conductive island 3 2 0 b; Figure 12E A cross-sectional view along an F-F 'line indicated in Fig. 10, wherein the etched back side dielectric spacer 3 1 5 b shown in Fig. 11E is formed by a thicker back The second side wall dielectric pad 3 1 5 c is replaced; and FIG. 12F shows a cross-sectional view along a line G--G ′, as shown in FIG. The etch-back second planarized oxide layer 3 1 7 e is replaced by a thicker etch-back second planarized oxide layer 3 1 7 f. FIG. A hybrid schematic circuit representation of the flash memory cell structure and its second type of non-contact separated diffusion bit line array, in which the complex common drain pipeline (BL2) 31 6d / 31 6b and the complex even paired buried layer source diffusion The bit line (BL 1) 3 0 5c is formed in parallel; the plurality can be miniaturized and opened the flash memory cell (3 0 1 to 3 2 5).

Page 27 591764 V. Description of the invention (23) Between each of the plurality of common drain pipelines (BL 2) 316 d / 316b and its adjacent buried layer source diffusion bit line (BL 丨) 3 〇5 c ; And a plurality of metal word lines ("10303188 and the plurality of common conductive lines (to 2) 316 (1/31613 are perpendicular to each other ') wherein each of the above-mentioned plurality of metal word lines (WL) 3 18a and each A row of the conductive islands of the scaleable control gate or the conductive islands of the scaleable composite control gate 320b / 312d are integrated. Now refer to FIG. 14A to FIG. 14C and FIG. One kind of miniaturizable open-type flash memory cell structure and the continuation of the second type of non-contact discrete diffusion bit line array are shown in Figure 8E, which is a simplified process step and a cross-sectional view thereof. Figure 14A shows a pair of The second side wall dielectric cushion layer 3 丨 5a is formed on the side wall of the adjacent miniaturizable branching area (SSGR) and is placed in each of the miniaturizable common drain areas (SCDR). Over 31 lb of the side surface portion of the gate dielectric layer; located within each of the miniaturizable common drain regions (SCDRs) The gate dielectric layer 3 1 1 b between the pair of second side wall dielectric pads 3 1 5 a is added and removed by using a non-isotropic dry-cut method; The semiconductor substrate between the wall dielectric pads 3 1 5a is etched using an anisotropic dry-etching method to form a shallow groove within each of the micronizable common drain regions (SCDRs); then A second planarized field oxide layer 3 1 7 a fills the pair of second side wall dielectric pads 3 1 5a located within each of the scalable common drain regions (scd R). The above-mentioned second side wall dielectric pad layer 3 1 5a is composed of silicon dioxide and is deposited using the LPCVD method to form the first side wall dielectric pad layer 3 0a. It is formed by the same process steps. The second planarized field oxide layer 3 丨 7a described above is made of dioxygen.

Page 28 591764 V. Description of the invention (24) It is composed of siliconized, phosphorous glass or borophosphoric glass and is deposited using LPCVD method, HDPCVD method or PECVD method to form the first planarized field oxide layer 3 0 8d The same process steps to form. It can be clearly seen here that the parent and the diffusion region 3 1 4 a are separated by the first planarized field oxide sound 3 1 7 a into a pair of buried layer drain bit lines 3 1 4c . 9 FIG. 14B shows the first side wall dielectric cushion layer 306a and the second side wall dielectric cushion layer 3 1 above a top surface level of the planarization control gate conductive layer 3 1 2 c. 5 a, the first planarized field oxide layer 3 0 8 a, the second planarized field oxide layer 3 1 7 a, and the fourth side wall dielectric hafnium layer 3 1 3 a are sequentially removed Form a flat structure surface, as shown in Figure 2L or Figure 3C. FIG. 14C shows that a metal layer 3 1 8 is formed on the surface of the flat structure and is formed by a second mask photoresist (PR2) step (not shown) to form a plurality of metal word lines (WL). 3 1 8a; the planarization control interlayer conductive layer 3 1 2 c, the inter-gate dielectric layer 3 0 3 b, the micronizable floating gate layer 3 〇 2 b, and the polycrystalline silicon oxide layer 3 1 1 a The non-isotropic dry etching method is used to sequentially add and remove; then, an ion implantation process is performed in an auto-alignment manner to form the common source region (CSR) and the micronizable common drain region (SCDR). ) And an isolated ion implantation region 319a between adjacent metal word lines (WL) 3 1 8 a. For the detailed process mentioned above, please refer to the description in FIG. 2L or FIG. 3C. Figure 15 shows the first side wall dielectric pad 3 0 6 a, the second side wall dielectric pad 315 a, the first planarization field oxide layer 308 d, and the second planarization field oxide Layer 3 1 7d is etched back using non-isotropic dry etching to remove the bending of the first / second side wall dielectric cushion layer 3 0 6 a / 3 1 5 a

Page 29, 591764 V. Part (25) of the description of the invention; Then, the fourth side wall dielectric pad 3 1 3 a is removed by non-isotropic dry etching or wet etching with hot phosphoric acid; Next, a planarized clad conductive layer 320 a fills every gap left by the removed fourth side wall dielectric pad layer 3 1 3a; then, a metal layer 3 丨 8 is formed on the formed Above the structure surface, a second mask photoresist (PR2) step (not shown) is used to form to form a plurality of metal word lines (WL) 3 18a; then, in the micronizable opening zone (SSGR) ) Between each of the adjacent metal word lines (WL) 3 18a within the planarized overlay conductive layer 3 2 0a, the planarized control gate conductive layer 312c, the inter-gate dielectric layer 3 0 3b, the The micronizable floating gate layer 3 0 2 b and the polycrystalline stone oxide layer 3 11 a are sequentially removed; finally, an ion implantation process is performed in an automatic alignment manner, and the doped fabric Implanted between the common source region (CSR) and the micronizable common concealed region (scDR) and between adjacent metal word lines 3 1 8a A surface portion of the semiconductor substrate 3 to form a billion billion ion implantation isolation region 319a (not shown). For the detailed process steps mentioned above, please refer to the description of FIGS. 3A to 3C. It can be clearly seen from FIG. 14C and FIG. 15 that the common source diffusion region 3 0 5 a and the common diffusion region 314 a are respectively stimulated by a first planarization field oxide layer 3 0 8 e / 3 0 8 f and an etched back second planarization field oxide layer 317b / 3 17c to separate into a pair of buried source diffusion bit lines 3 05c and a pair of buried layers> and diffusion bit line 3 1 4 c; therefore, each of the above-mentioned plurality of micronizable open-type flash memory cells can be scrubbed separately. Please refer to FIG. 16 ′, which is a mixed brief top-view layout diagram of the miniaturizable and openable flash β-calyx cell structure of the present invention and its second type of contactless discrete diffusion bit line array . As shown in Figure 16, the complex even pair

Page 30 591764 V. Description of the invention (26) Buried source diffusion bit line (BL 1) 30 5c and complex even-buried layer drain diffusion bit line (BL2) 3 14c are formed in parallel and are parallel to the complex metal word line (WL) 3 18a is perpendicular to each other, wherein each of the plurality of metal word lines (WL) 3 18a is covered with the micronizable control gate conductive island 3 1 2d or the micronizable control gate conductive island 31 2d The planarization covers an integrated connection of the conductive island 32 0b; and an isolated ion implantation region 3 1 9 a is formed between the common source region (cs R) and the miniaturizable common congestion region (SCDR) and is located at Adjacent metal word lines (ψ l) between 3 1 8 a 0 Figure 10-surface diagram, which is shown in Figure 10 B-B 'line of a C-C' Along the marked diagram shown in Figure 10 shows the map system A detailed drawing, one along the eleventh part of the eleventh and the description of the eleventh in Fig. Ten of which seven A through seventeen F show a brief cross-section of the fourteenth c in the sixteenth A cross-sectional view of an A-A 'line is shown in Fig. 4C; Fig. 17A shows a cross-sectional view along a line marked in Fig. 16; Fig. 10 B shows a cross-sectional view along the line indicated in FIG. 16; FIG. 17C shows a cross-sectional view along the line DD 'shown in FIG. 16; FIG. 17D shows FIG. 12 ^ an E-E A cross-sectional view of the 'line; Figure XVII ^^' s Figure X = a cross-sectional view along an F-F 'line; and a cross-sectional view along a GG, line indicated in Figure XVIIF. Here, the values are as shown in Fig. 17A to Fig. 17D and Fig. 11a to Fig. 11d. Therefore, the detailed descriptions of FIGS. 17A to 17D can be described in Tables A to 11D. Similarly, FIG. 17E and FIG. 17 > FIG. Therefore, FIG. 17 and FIG. 17 can be explained with reference to FIGS. 5E and 5F, respectively. Figures 8A through 18F show a brief section of Figure 15 in Figure 16 and a section along A-A in Figure 16 is shown.

591764 V. Description of the invention (27) '~-In FIG. 15; FIG. 18A shows a cross-sectional view along the line B_B, shown in FIG. 16; FIG. 18B shows FIG. A cross-sectional view along a line c-C 'marked in FIG. 18; FIG. 18c shows a cross-sectional view along line DD' marked in FIG. 16; FIG. 18D shows a mark in FIG. ; A cross-sectional view along an E-E 'line; FIG. 18e shows a cross-sectional view along a line FF, shown in FIG. 16; and FIG. 18F shows a line indicated by ^ 16 A sectional view along a G-G 'line. Figures 18a to 18 are the same as Figures 11A to 11D. Therefore, the detailed description of FIG. 18a to FIG. 18D can be referred to the explanation of FIG. 12a to FIG. 12], respectively). Similarly, Figures 18E and 18F are the same as Figures 6E and 6F, respectively. Therefore, the detailed descriptions of FIG. 18E and FIG. 18F can be referred to the explanations of FIG. 6E and FIG. 6F, respectively. FIG. 19 shows a schematic representation of a hybrid schematic circuit of the micronizable split-gate flash memory cell structure and the third type of contactless discrete diffusion bit line array of the present invention, in which multiple pairs of buried layer sources The diffusion bit line (B L1) 3 0 5c and the multiple even-pair buried layer diffusion bit line (BL2) 314c are formed in parallel and perpendicular to the complex metal word line (WL) 318 a; the above complex metal word Each of the lines (WL) 3 18a is connected to the conductive island 31 2d or the conductive island 3 1 2 d covered with the planarized conductive island 3 2 0 b. ; And a plurality of scalable micro flash memory cells (40, 425) are formed between the buried source diffusion bit line (BL1) 305c and the buried layer drain diffusion line (BL2) 31 4c. . It can be clearly seen from FIG. 14C and FIG. 15 that the common source diffusion region 3 0 5a and the common drain diffusion region 3 1 4a are respectively planarized by an etchback first.

P.32 Based on the isomorphic structure of the cell, the cell can be memorized, flashed down, and fast-typed, which can be gated for micro-surgery, and can be used for this process. Bright wall 20 hairline 4 This side is> from small (a warp or 591764 v. Invention description (28) field oxide layer 3 0 8 e / 3 0 8 f and a back # second planarization field oxide layer 317b / 317c to separate into a pair of buried source diffusion bit lines (BL 1) 30 5c and a pair of buried layer drain diffusion bit lines (BL2) 31 4c; and the plurality of miniaturizable gated flash memory cells (4 (Π ~ 42 5) each can have high flexibility for writing and scrubbing. It is worth emphasizing here that the various ion-free isolated ion cloths of the present invention have different contactless separated diffusion bit line arrays. The implanted region 3 1 9 a can be easily replaced by forming a shallow groove isolation (STI) region, and the semiconductor substrate 300 can be a diffusion well of the first conductivity type formed in the second conductivity type. Based on this, the features and advantages of the miniaturizable open-type flash memory cell structure of the present invention and the contactless discrete diffusion bit line array can be summarized as follows: fb) The present invention The micro-scale open-type flash memory cell structure is provided, and the water-solidity can be micro-scaled. The island uses the middle channel hot electron injection method (MCHEI to zoom into the writing efficiency and reduce the writing power. The miniaturized open-type flash memory cell structure of the invention and its point-and-diffusion diffusion bit line The array can be

Page 33 591764 V. Description of the invention (29) The formula requires fewer mask photoresist steps to manufacture than the prior art. (d) The micronizable split-gate flash memory cell structure and the contactless discrete diffusion bit line array of the present invention provide the metal layer of each of the plurality of metal word lines and the micronizable control gate Conductive islands or the conductive composite islands of the reducible composite control gates are integrated to reduce the word line resistance significantly. Provide low-rise and high-rise array lines to the yuan line, bit tube, and scattered sources. Expansion and common resistance & B0 Πν \ From the conductor points, the high-level points are connected to a common type with a single source, and every time the deep area of the deep is exposed, the source is expanded and the source is shrunk e. C The micro (f) The second type of contactless separation of the present invention is identified by a high-conductance mine Δg AA of each of the common-diffusion diffusion regions at the time when the depth of the dip junction is reduced. Common drain bit line resistance. Decrease (g) The third type of the contactless separation type of the present invention each of the common source / sink diffusion regions is provided to the line array to increase the flexibility of cell operation. The present invention refers to the attached example, but it is only a representative statement and not a limitation. In addition, the details shown and described in this text can also make clear to those skilled in the art that they are not limited to the listed or detailed changes without departing from the true meaning of the present invention, 'f different shapes are made' but also It belongs to the scope of the present invention. 1 1 and Fan_ can be made under

591764 Brief Description of Drawings Figure 1 shows a buried common source / drain diffusion bit line array of the prior art. FIGS. 2A to 2E are easy to show that a miniaturizable open-type flash memory cell structure of the present invention has a micro-controllable conductive gate conductive island and a first type of contactless discrete diffusion bit line array. . FIG. 3A to FIG. 3C show that a miniaturized split-type flash memory cell structure for manufacturing the present invention has a micronizable composite control gate conductive island and a first type of contactless discrete diffusion bit line array. It follows the process steps and cross-sectional views of Figure 2J.

FIG. 4 illustrates a hybrid schematic top-view layout diagram of the miniaturizable split-type flash memory cell structure and the first type of contactless discrete diffusion bit line array of the present invention.

FIGS. 5A to 5F show various cross-sectional views of FIG. 4A indicated in FIG. 4A, wherein FIG. 5A shows a cross-sectional view along a line B-B ′ indicated in FIG. 4; FIG. 5B shows A cross-sectional view along a CC line indicated in FIG. 4; FIG. 5C shows a cross-sectional view along a D-D 'line indicated in FIG. 4; FIG. A cross-section view along an E-E 'line; FIG. 5E shows a cross-section view along a F-F' line indicated in FIG. 4; and FIG. 5F shows a G-G line along FIG. A section view of the line. FIGS. 6A to 6F show various cross-sectional views of FIG. 3C indicated in FIG. 4A, where FIG. 6A shows a cross-sectional view along a line BB ′ indicated in FIG. 4; FIG. 6B shows A cross-section view taken along a line CC-C 'shown in FIG. 4; FIG. 6C shows a cross-section view taken along a D-D' line shown in FIG.

Page 35 591764 Brief description of the drawings A section view A section view A section view Figure 6D display figure Figure 6E display figure and Figure 6F a sectional view. Reveal the structure of the invention in Figure 7 and its schematic circuit diagram. Eight flash memories of the second type without steps. Figure 9 Flash memory and its second process steps. Figure X. Structure and its brief layout. A D-D 'line of the line E-E' line of the first type of non-contact point representative diagram. A to FIG. 8I show the cross-sectional views of the cell structure with contact-separated diffusion. A to Fig. 9C reveal that the cell structure has a contactless separation type and its sectional view. The second type of contactless sub-map of the present invention is disclosed. Four marked along an E-E 'line. Four marked along an F-F' line. Figure 4 marked along a G-G 'line. Miniaturized trip flash. A hybrid of a memory cell cell with a diffused bit line array is made of a micronizable split gate type, a micronizable control gate conductive island and its bit line array are connected. The process of FIG. 2C makes one of the present invention. Continuation of a micronizable split gate type diffused bit line array of conductive islands in a controllable composite control gate Figure 8F The various diagrams shown in Figure 8I do not show a section along the line B-B 'shown in Figure X. Figure B shows a section along the C-line along Figure X. Figure 11 shows a section along the line marked in Figure X. Η--D shows the figure along the figure 一 --E shows the figure along the figure A through 11A, of which figure 11A is a cross-sectional view; A sectional view;

P.36 591764 The drawing simply illustrates a cross-sectional view of an F-F 'line; and FIG. 11F shows a cross-sectional view along a G-G' line marked in FIG. Figs. 12A to 12F show various cross-sectional views of Fig. 9C indicated in Fig. 10, wherein Fig. 12A shows a cross-sectional view along a BB 'line indicated in Fig. 10; Fig. 10 2B shows a cross-sectional view along a CC ′ line indicated in FIG. 10; FIG. 12C shows a cross-sectional view along a D-D ′ line indicated in FIG. 10; FIG. 12D shows FIG. 10 A cross-sectional view along an E-E 'line as shown; FIG. 12E shows a cross-sectional view along an FF' line as shown in FIG. 10; and FIG. 12F shows a cross-section along the line as shown in FIG. A sectional view taken along a line G-G '. FIG. 13 shows a representative schematic diagram of a hybrid schematic circuit of the miniaturizable open-type flash memory cell structure of the present invention and its second type of contactless discrete diffusion bit line array. FIGS. 14A to 14C show that a miniaturized split-gate flash memory cell structure for manufacturing the present invention has a micronizable control gate conductive island and a third type of non-contact discrete diffusion bit line. The process of the array is continued with FIG. 8E and its sectional view. Figure 15 reveals one of the structures of a miniaturizable split-gate flash memory cell structure with a micronizable composite control gate conductive island and its third type of contactless discrete diffusion bit line along the length of a channel. Sectional view. FIG. 16 is a representative schematic diagram of a hybrid schematic circuit of the miniaturizable open-type flash memory cell structure of the present invention and its third type of contactless discrete diffusion bit line array. Figures 17A to 17F disclose each of Figure 14C marked in Figure 16.

Page 591764 The diagram briefly illustrates the different cross-sectional views. Figure 17A in Gan Shi M @ ^ shows along the line marked in Figure 16 — with a c command map; Figure 17 6 shows the line marked in Figure 16. along

> A cross-sectional view of the ice plus one; FIG. 17C shows a cross-sectional view of the β-two machine label _ / D 'line shown in FIG. 16; FIG. A cross-sectional view of line E_E '; FIG. 17E shows a cross-section of a line FF + 丄 & 丄 in FIG. 10; and a cross-section along line G_G, line 2 of FIG. Eighteen A through 18F reveal the figure ten marked in figure sixteen Μ &# different cross-sectional views, picture book, a # s-eil various RRs solidifying five, soul # ^ 十 ^ A ”,, The member does not show a cross-sectional view along a BB line as shown in FIG. 16; or: A Γ-Γ, green from, 1 is only a cross-sectional view along the C line; Figure 18c Fig. 18 shows a cross section ffi; Fig. 18D shows a cross section of an E_E 'line in Fig. 18D; A cross-section view along the line "" indicated by sixteen and sixteen; eighth F. Fig. Nineteen reveals the miniaturizable open-type element structure of the present invention and its first section. three Contactless discrete diffusion bit, =: and a brief circuit representative diagram. A mixed representative drawing number of Hiroshi ’s description: 300 semiconductor substrate 301 penetrates the dielectric layer 301a / 301b is formed and penetrates the dielectric layer 302 first The conductive layer 3 0 2a is formed into a first conductive layer 302b to reduce the size of the floating gate layer.

38 591764 Brief description of the drawing 3 0 2 c Miniaturized floating gate island 3 0 3 a / 3 0 3 b / 3 0 3 c Forming gate 3 04 Mask dielectric layer 3 0 5 a Common source diffusion area 3 0 5 c buried source diffusion bit line 306 b / 306c etch back the first side wall 3 0 7d / 3 0 7b common source conductive pipeline 3 0 8b etch back the first planarization oxide 3 08d first planarization field The oxide layer 3 08e / 3 08 f etch back the first planarization 309a, the third side wall dielectric cushion layer 3 11 b / 3 11 d, the gate dielectric layer 312a, the planarization, and the second conductive layer 3 1 2 c. Control gate conductive layer 313a, fourth side wall dielectric pad 314b, highly doped common-drain diffusion region 315a, second side wall dielectric pad 3 1 5 b / 3 1 5 c, back side wall 316d / 316b common drain conductive line 317b / 317c etch back second planarization 31 7d second planarization oxide layer 317e / 317f back to second planarization 318 metal layer 319a isolation ion implantation area 30 3 inter-gate dielectric layer dielectric Layer 30 4a forming mask dielectric layer 3 0 5 b highly doped common source diffusion region 3 0 6 a first side wall dielectric pad layer dielectric hafnium layer 308 a first planarized oxide layer layer field oxide layer 310a / 310b ion implantation area 3 1 1 a / 3 1 1 c polycrystalline stone oxide layer 312b back to #planarize the second conductive layer 3 1 2 d can be controlled to control the gate conductive island 3 1 4 a common diffusion region 3 1 4 c buried layer drain diffusion line Dielectric pad layer 3 1 7 a second planarized field oxide layer field oxide layer oxide layer 318 a metal word line 32 0 a planarized cover conductive layer

591764 Schematic illustration of 3 2 0b planar cover conductive island

mm Page 40

Claims (1)

591764 VI. Scope of patent application 1. A miniaturizable open-type flash memory cell structure including at least: a semiconductor substrate of a first conductivity type; a miniaturizable open-circuit area is formed on the semiconductor substrate, The above-mentioned micronizable trip zone is located between a common source zone and a minimizable common sink zone; the mininizable trip zone contains at least one micronizable control gate conductive island with its first part formed Above a miniaturizable floating gate island and its second part is formed on a part of the surface of a gate dielectric layer, wherein the aforementioned miniaturizable floating gate island has an inter-gate dielectric layer formed on it Above the top surface and a polycrystalline silicon oxide layer formed on its inner side wall is formed on a portion of the surface that penetrates the dielectric layer; the common source region is illuminated by a first mask Resistance step to define a common source diffusion region containing at least one second conductivity type, and implanting a dopant on a surface portion of the semiconductor substrate by an automatic alignment method; the micronizable common drain region A common-drain diffusion region containing the second conductivity type is implanted with a dopant on a surface portion of the semiconductor substrate by an automatic alignment method; a metal word line with the common source region and the micronizable The common draw area is vertical to each other and is integrated with the conductive island of the micronizable control gate, wherein the metal word line, the conductive island of the micronizable control gate, the inter-gate dielectric layer, and the micronizable floating gate The island system is simultaneously formed by a second mask photoresist step; and a semiconductor substrate is formed outside the metal word line and between the semiconductor substrate and the common source region and the micronizable common drain region. Every table Page 41 591764 Six, the scope of patent application. 2. The miniaturizable open-type flash memory cell structure described in item 1 of the scope of the patent application, wherein the common source region further includes at least a pair of etch-back first side wall dielectric cushion layers formed on the phase A common source conductive layer is formed on the pair of etched back first side wall dielectrics on a side wall between adjacent miniaturizable trip zones and on a portion of the surface of the penetrating dielectric layer Between the underlayers and placed on a highly doped common source diffusion region formed within the common source diffusion region and an etched back first planarized oxide layer is formed on the pair of etched back side walls Between the electric pad layers and placed on the common source conductive layer, the micronizable common area further includes at least a pair of back #second side wall dielectric layers formed in the adjacent micronizable opening gates. An etch-back second planarization field oxide layer is formed on the side wall and on a part of the surface of the gate dielectric layer, and is formed between the pair of etch-back second side wall dielectric pads and It is placed on a shallow groove in the semiconductor substrate to separate the common-drain diffusion region into a pair of buried-drain diffusion regions. 3. The miniaturizable open-type flash memory cell structure described in item 1 of the scope of patent application, wherein the common source region further includes at least a pair of etched back first side wall dielectric cushion layers formed on the phase A shallow groove is formed on the side wall adjacent to the miniaturizable trip zone and on a part of the surface of the penetrating dielectric layer, and a shallow groove is formed in the pair of etched back first side wall dielectric cushion layers. A surface portion of the semiconductor substrate and an etched back first planarized field oxide layer are formed between the pair of etched back side wall dielectric pads to separate the common source diffusion region 591764 VI. The scope of the patent application is a pair of buried layer source diffusion regions, and the miniaturizable common drain region includes at least a pair of etched back second side wall dielectric pads formed on the side walls of adjacent miniaturizable trip zones. Above and placed on a part of the surface of the gated electrical layer, a common drain conductive layer is formed between the pair of etched second side wall dielectric pads and is positioned in the common drain diffusion area Within the second conductivity type, a highly doped common-drain diffusion region and an etch-back second planarizing oxide layer are formed between the pair of etch-back second sidewall spacer dielectric pads and disposed Over the highly doped common-drain diffusion region. 4. The miniaturizable open-type flash memory cell structure described in item 1 of the scope of the patent application, wherein the above-mentioned co-source / differentiable co-drain region further includes at least a pair of etch-back first / second sides A side wall dielectric cushion layer is formed on the side wall of the adjacent miniaturizable trip zone and is placed on a part of the surface of the penetrating dielectric layer / the gate dielectric layer, and a shallow groove is formed. A surface portion of the semiconductor substrate between the pair of first and second side wall dielectric pads and an etched back first / second planarized field oxide layer are formed in the pair of etched back layers. A common source / drain diffusion region is separated between one / second side wall dielectric pads to form a pair of buried source / drain diffusion regions. 5. The miniaturizable open-type flash memory cell structure described in item 1 of the scope of the patent application, wherein the above-mentioned miniaturizable floating gate island is formed on a side wall of the common source area by A third side wall dielectric pad layer is defined to include at least one doped polycrystalline silicon or doped amorphous silicon island and the scaleable control gate conductive island is formed by a side wall formed in the common source region. On one Page 43 591764 VI. Scope of patent application A fourth sidewall spacer is defined to contain at least one doped polycrystalline silicon island or one doped polycrystalline silicon island covered with a tungsten (W) island or a tungsten silicide (WSi2) island. 6. The miniaturizable open-type flash memory cell structure described in item 1 of the scope of patent application, wherein the co-source / drain diffusion region includes at least one highly doped diffusion region or a highly doped diffusion region. Within a lightly doped diffusion region. 7. The miniaturizable open-type flash memory cell structure described in item 1 of the scope of patent application, wherein the metal word line includes at least one metal layer formed on a barrier metal layer and the metal layer includes at least Aluminum (A1), copper (Cu) or crane (W). 8. The miniaturizable open-type flash memory cell structure described in item 1 of the scope of patent application, wherein an ion implantation region of the first conductivity type described above includes at least one shallow ion implantation region as a threshold voltage Adjustment and a deep ion implantation region to form an anti-forbidden region formed on a surface portion of the semiconductor substrate under the gate dielectric layer located within the miniaturizable switching region. 9. The miniaturizable open-type flash memory cell structure as described in item 1 of the patent application scope, wherein the cell isolation region includes at least an isolation ion implantation region or a shallow depression of the first conductivity type. Trench Isolation (STI) area. 591764 VI. Application patent scope 1 0 · — No connection I. Each of the plurality of common source diffusion regions on the first plurality of common source conductor substrates has an electric pad layer formed on the penetration Dielectric layer back #First side part and a first side wall source diffusion bit line. The plurality of configurable ones are common and a pair of side walls returning to the money gate area. The first part of the intersection is formed on the conductive surface of the chemical control gate, wherein the S-separated diffusion bit line array includes at least a semiconductor substrate of conductivity type; the regions and the plurality of micronizable common drain regions are alternately formed on, One of the miniaturizable opening regions is formed between the one and its adjacent miniaturizable common drain region; each of the source regions contains at least one second conductivity type, and the dopants are implanted by an automatic alignment method. It is formed on each surface, a pair of cash back, the first side of a pair of cash back, and a part of the surface adjacent to the side wall which can be miniaturized and opened, and a shallow groove is formed on the wall dielectric. One of the semiconductor substrates between the layers A chemical field oxide layer is formed between the pair of electrode layers to separate the common source diffusion region into a pair of fM condensation regions; and each of the regions includes at least the second diffusion region formed on a surface of the semiconductor substrate. A side wall dielectric cushion layer is formed on a part of the surface of an adjacent shrinkable t and placed on a part of a gate dielectric layer, and each of the knife regions includes at least a plurality of shrinkably formed and has the shrinkable The control gate is electrically conductive above a scaleable floating gate island and the second part of the scaleable island is formed in a portion of a gate dielectric layer. The above scaleable floating gate island has a half of the gate and a half of the half of the gate. The wall lies between a pair of surface conductive layers of the remaining buried layer; the micro-scale fraction of the island of chemical control is dielectric 591764. 6. A patent-application layer is formed on the top surface and a polycrystalline silicon oxide layer is formed on The inner side wall is formed on a part of the surface of the penetrating dielectric layer; a plurality of metal word lines are perpendicular to the plurality of common source regions and the plurality of micronizable common drain regions and have a plurality of metal words. Each of the lines It is integrated with the conductive island of the micronizable control gate, wherein the plurality of metal word lines, the conductive island of the micronizable control gate, the dielectric layer between the gates, and the micronizable floating gate island are all connected by a cover. Curtain photoresist steps are simultaneously formed; and a plurality of cell isolation regions are formed on the surface portion of the semiconductor substrate outside the plurality of metal word lines, the plurality of common source regions, and the plurality of micronizable common drain regions. 11 · The non-contact separated diffused bit line array according to item No. 丨 0 of the application scope, wherein each of the above-mentioned plurality of micronizable common drain regions further includes at least one shallow groove formed in the pair of etch-backs A surface portion of the semiconductor substrate between the second side wall dielectric pads and an etch-back second planarization field oxide layer are formed between the pair of etched second side wall dielectric pads and It is placed on the shallow groove of the semiconductor substrate to separate the common-drain diffusion area into a pair of buried-drain diffusion bit lines. 1 2. The contactless separated diffused bit line array as described in item No. 丨 0 of the patent application, wherein each of the above-mentioned plurality of scaleable common sink regions includes at least one common conductive line formed in the pair. Etch the second side wall dielectric pad and place it on a locally doped common-drain diffusion region of the second conductivity type formed within the common-drain diffusion region and etch back a second planarization oxide Thing Page 46 591764 VI. Scope of patent application The second side wall dielectric cushion layer described in item 10 is not connected to the plurality of miniaturizable opening and closing gate conductive islands by forming a fourth side edge An island or a doped complex crystal island is covered with the plurality of dilatable islands by forming a dielectric spar layer spar island in the third side wall of the plurality. A non-connected multiple cell isolation area described in item 10 is an isolation ion implantation area or a non-connected first conductivity type area described in item 10 is used as a threshold voltage forbidden area The semiconductor layer, which is formed below the electrical layer, is formed on the pair of etch-back conductive lines. 1 3. As claimed in the patent application line array, wherein the side wall of each of the plurality of micronizable micro-controllers contains a doped polycrystalline stone evening crane (WSi2) island and is located on the side wall of the micro-narrowable floating gate. A heteromulticrystalite or doped non 1 4 · such as a patent-applied fan line array, wherein the STI) region of the first conductivity type is described above. 15 · If applying for a patented line array, wherein the above-mentioned area containing a shallow ion implantation area is formed to form a gate region of the gate intermediary 0 t, and is located at the common drain-point separation diffusion site A dielectric pad within the plurality of common source regions within each of the meta regions is defined to each of the common source regions covered with each of the tungsten (W) or silicidated regions to define at least doping points Each of the discrete diffusion bits includes at least one shallow groove isolation (the point-separated diffusion bit ion implantation area includes at least adjustment and a deep ion is located on a surface portion of the micronizable sub-substrate 591764. There are a total of back-edge types and a number of control surfaces. • A type of non-contact discrete diffusion bit line array including at least one semiconductor substrate of a first conductivity type; β. A common source area and a plurality of Above the micronized common dip zone alternating ground substrate, one of the micronizable open gate systems is formed, and the openings are between each of the complex > original regions and its adjacent minimizable common dip zone; the plural Each of the common source regions includes at least a second conductivity type common source diffusion region formed on a surface portion of the semiconductor substrate and a plurality of first side wall dielectric chirped layers formed on adjacent miniaturizable gate opening regions. On the wall of the semiconductor substrate and on a part of a surface of the penetrating dielectric layer; each of the plurality of miniaturizable common drain regions including at least a second drain common drain region is formed on the semiconductor substrate; One surface portion—the etch-back second side wall dielectric cushion layer is formed on the adjacent side wall of the micronizable element and is placed on a part of the surface of a gate dielectric layer to form a conductive pipeline. Dielectric on the second etched back side wall A layer of the second conductive type formed on the hetero-diffusion region of the second conductivity type formed within the common-drain diffusion region and a second planarizing oxide layer remaining on the pair of etched-back second sidewall spacers Each of the micronizable gates is formed alternately with at least a plurality of micronizable gate conductive islands and is provided with the micronizable control gate conductive island-portion It is formed above the miniaturized floating island of Gemachi and the P part of the conductive island between the micro-controllable islands is formed on a part of a gate dielectric layer. The above-mentioned micronizable floating gate in the basin The island has a half-diameter scale-type electrical control scale-down scale 591764 VI. Patent Application Range A dielectric layer is formed on the top surface and a polycrystalline silicon oxide layer is formed on its inner side wall. A plurality of metals are formed on a part of the surface of the penetrating dielectric layer. The word line is perpendicular to the complex common source region and the complex scalable common sink region and each of the complex metal word lines is integrated with the conductive island integration of the scalable control gate, wherein the complex metallic word described above Lines, the conductive island of the micronizable control gate, the dielectric layer between the gates, and the floating micron island are simultaneously formed by a mask photoresist step; and a plurality of cell cell isolation regions are formed in the plurality of metal words A surface portion of the semiconductor substrate outside the line, the plurality of common source regions, and the plurality of scalable common drain regions. 1 7. The non-contact separated diffused bit line array according to item 16 of the scope of the patent application, wherein each of the plurality of common source regions further includes at least one common source conductive pipeline formed in the pair of back # 第One side wall dielectric pad layer is disposed on a highly doped common source diffusion region of the second conductivity type formed within the common source diffusion region and an etched back first planarized oxide layer Formed between the pair of etched back side wall dielectric pads and placed on the common source conductive pipeline. 1 8. The contactless separated diffused bit line array according to item 16 of the scope of patent application, wherein each of the plurality of common source regions further includes at least one shallow groove formed in the pair of etch-back first A surface portion of the semiconductor substrate between the side wall dielectric pads and an etch-back first planarization field oxidation Page 49 591764 VI. Patent application scope An object layer is formed between the pair of etched back side wall dielectric pads and placed on the shallow groove of the semiconductor substrate to separate the common source diffusion region into a pair of buried layers. Layer source diffusion bit line. 19. The contactless separated diffusion bit line array as described in item 16 of the scope of the patent application, wherein the micronizable floating gate island located within each of the micronizable gate opening regions is formed by A third side wall dielectric pad layer over the side walls of the common source region is used to define each of the micronizable break-out regions that includes at least doped polycrystalline silicon or doped amorphous silicon islands. The scaleable control gate conductive island within is defined by at least a doped polycrystalline silicon island or doped by a fourth side wall dielectric pad formed on a side wall of the common source region. The polycrystalline silicon islands are covered with tungsten (W) or tungsten silicide (WSi 2) islands. 20. The non-contact separated diffusion bit line array according to item 16 of the scope of the patent application, wherein each of the plurality of cell isolation regions includes at least one isolation ion implantation region of the first conductivity type. Or a shallow groove isolation (ST I) region, and an ion implantation region of the first conductivity type includes at least one shallow ion implantation region as a threshold voltage adjustment and a deep ion implantation region to form a breakdown prohibition A region is formed on a surface portion of the semiconductor substrate under the gate dielectric layer within each of the miniaturizable opening regions. Page 50