FR3041147B1 - Procede d'integration d'au moins une interconnexion 3d pour la fabrication de circuit integre - Google Patents

Procede d'integration d'au moins une interconnexion 3d pour la fabrication de circuit integre

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Publication number
FR3041147B1
FR3041147B1 FR1558544A FR1558544A FR3041147B1 FR 3041147 B1 FR3041147 B1 FR 3041147B1 FR 1558544 A FR1558544 A FR 1558544A FR 1558544 A FR1558544 A FR 1558544A FR 3041147 B1 FR3041147 B1 FR 3041147B1
Authority
FR
France
Prior art keywords
interconnect
integrating
integrated circuit
circuit manufacturing
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1558544A
Other languages
English (en)
Other versions
FR3041147A1 (fr
Inventor
Ayad Ghannam
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
3dis Tech
Original Assignee
3dis Tech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 3dis Tech filed Critical 3dis Tech
Priority to FR1558544A priority Critical patent/FR3041147B1/fr
Priority to EP16770715.7A priority patent/EP3350827A1/fr
Priority to PCT/EP2016/071674 priority patent/WO2017046153A1/fr
Priority to US15/759,735 priority patent/US10438923B2/en
Publication of FR3041147A1 publication Critical patent/FR3041147A1/fr
Application granted granted Critical
Publication of FR3041147B1 publication Critical patent/FR3041147B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/24011—Deposited, e.g. MCM-D type
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    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H01L2224/24051—Conformal with the semiconductor or solid-state device
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    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24105—Connecting bonding areas at different heights
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    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/24146—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24265—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2499—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids
    • H01L2224/24991—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids being formed on the semiconductor or solid-state body to be connected
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2499—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids
    • H01L2224/24996—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/24998—Reinforcing structures, e.g. ramp-like support
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/82051—Forming additional members
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/19011—Structure including integrated passive components
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
FR1558544A 2015-09-14 2015-09-14 Procede d'integration d'au moins une interconnexion 3d pour la fabrication de circuit integre Active FR3041147B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR1558544A FR3041147B1 (fr) 2015-09-14 2015-09-14 Procede d'integration d'au moins une interconnexion 3d pour la fabrication de circuit integre
EP16770715.7A EP3350827A1 (fr) 2015-09-14 2016-09-14 Procede d'integration d'au moins une interconnexion 3d pour la fabrication de circuit integre
PCT/EP2016/071674 WO2017046153A1 (fr) 2015-09-14 2016-09-14 Procede d'integration d'au moins une interconnexion 3d pour la fabrication de circuit integre
US15/759,735 US10438923B2 (en) 2015-09-14 2016-09-14 Method for integrating at least one 3D interconnection for the manufacture of an integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1558544A FR3041147B1 (fr) 2015-09-14 2015-09-14 Procede d'integration d'au moins une interconnexion 3d pour la fabrication de circuit integre

Publications (2)

Publication Number Publication Date
FR3041147A1 FR3041147A1 (fr) 2017-03-17
FR3041147B1 true FR3041147B1 (fr) 2018-02-02

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
FR1558544A Active FR3041147B1 (fr) 2015-09-14 2015-09-14 Procede d'integration d'au moins une interconnexion 3d pour la fabrication de circuit integre

Country Status (4)

Country Link
US (1) US10438923B2 (fr)
EP (1) EP3350827A1 (fr)
FR (1) FR3041147B1 (fr)
WO (1) WO2017046153A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3119048A1 (fr) * 2021-01-21 2022-07-22 Commissariat A L'energie Atomique Et Aux Energies Alternatives Interconnexion avec ame
DE102022200340A1 (de) 2022-01-13 2023-07-13 Robert Bosch Gesellschaft mit beschränkter Haftung Mikromechanische Sensoreinrichtung

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010024022A (ko) * 1997-09-17 2001-03-26 이고르 와이. 칸드로스 금속 침전물의 적절한 열처리에 의해 개선된 재료 특성을갖는 구조물을 제조하기 위한 방법
US20030006493A1 (en) * 2001-07-04 2003-01-09 Matsushita Electric Industrial Co., Ltd. Semiconductor device and manufacturing method thereof
KR20040089453A (ko) * 2002-03-28 2004-10-21 신꼬오덴기 고교 가부시키가이샤 배선 구조체 및 이의 제조 방법
NO317846B1 (no) * 2002-12-23 2004-12-20 Laerdal Medical As Anordning for plassering pa brystet pa en pasient, for a samvirke med hendene pa en person som utforer brystkompresjoner .
US6972480B2 (en) * 2003-06-16 2005-12-06 Shellcase Ltd. Methods and apparatus for packaging integrated circuit devices
JP3904541B2 (ja) * 2003-09-26 2007-04-11 沖電気工業株式会社 半導体装置内蔵基板の製造方法
JP2006270009A (ja) * 2005-02-25 2006-10-05 Seiko Epson Corp 電子装置の製造方法
EP1883107A3 (fr) * 2006-07-07 2014-04-09 Imec Procédé pour la formation de dispositifs microélectroniques empaquetés et dispositifs ainsi obtenus
US7807508B2 (en) * 2006-10-31 2010-10-05 Tessera Technologies Hungary Kft. Wafer-level fabrication of lidded chips with electrodeposited dielectric coating
EP2575166A3 (fr) * 2007-03-05 2014-04-09 Invensas Corporation Puces ayant des contacts arrière reliés par des trous de passage aux contacts avant
TWI341628B (en) * 2008-02-12 2011-05-01 Taiwan Tft Lcd Ass Contact structure and bonding structure
FR2965659B1 (fr) 2010-10-05 2013-11-29 Centre Nat Rech Scient Procédé de fabrication d'un circuit intégré
KR20160006032A (ko) * 2014-07-08 2016-01-18 삼성전자주식회사 칩, 이를 이용하는 칩 적층 패키지 및 그 제조방법

Also Published As

Publication number Publication date
FR3041147A1 (fr) 2017-03-17
US20180254258A1 (en) 2018-09-06
US10438923B2 (en) 2019-10-08
WO2017046153A1 (fr) 2017-03-23
EP3350827A1 (fr) 2018-07-25

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