SG10201906679RA - Chip manufacturing method - Google Patents
Chip manufacturing methodInfo
- Publication number
- SG10201906679RA SG10201906679RA SG10201906679RA SG10201906679RA SG10201906679RA SG 10201906679R A SG10201906679R A SG 10201906679RA SG 10201906679R A SG10201906679R A SG 10201906679RA SG 10201906679R A SG10201906679R A SG 10201906679RA SG 10201906679R A SG10201906679R A SG 10201906679RA
- Authority
- SG
- Singapore
- Prior art keywords
- chip manufacturing
- chip
- manufacturing
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/38—Removing material by boring or cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67248—Temperature monitoring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018143126A JP7072993B2 (en) | 2018-07-31 | 2018-07-31 | Chip manufacturing method |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201906679RA true SG10201906679RA (en) | 2020-02-27 |
Family
ID=69383822
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201906679RA SG10201906679RA (en) | 2018-07-31 | 2019-07-18 | Chip manufacturing method |
Country Status (5)
Country | Link |
---|---|
JP (1) | JP7072993B2 (en) |
KR (1) | KR20200014195A (en) |
CN (1) | CN110783185B (en) |
SG (1) | SG10201906679RA (en) |
TW (1) | TWI800668B (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7273756B2 (en) * | 2020-03-18 | 2023-05-15 | 株式会社東芝 | Semiconductor device and its manufacturing method |
JP7450426B2 (en) | 2020-03-24 | 2024-03-15 | 株式会社ディスコ | Processing method of workpiece |
KR102405460B1 (en) * | 2020-06-26 | 2022-06-07 | 매그나칩 반도체 유한회사 | Semiconductor Die Forming and Packaging Method Using Ultrashort pulse Laser Micromachining |
CN113649709A (en) * | 2021-08-16 | 2021-11-16 | 湖北三维半导体集成创新中心有限责任公司 | Wafer cutting method |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3583279B2 (en) * | 1998-01-13 | 2004-11-04 | 三菱電機株式会社 | Drilling method |
JP4694845B2 (en) | 2005-01-05 | 2011-06-08 | 株式会社ディスコ | Wafer division method |
JP2011035302A (en) * | 2009-08-05 | 2011-02-17 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
US8383984B2 (en) | 2010-04-02 | 2013-02-26 | Electro Scientific Industries, Inc. | Method and apparatus for laser singulation of brittle materials |
WO2014130830A1 (en) | 2013-02-23 | 2014-08-28 | Raydiance, Inc. | Shaping of brittle materials with controlled surface and bulk properties |
JP2015020195A (en) | 2013-07-19 | 2015-02-02 | アイシン精機株式会社 | Laser processor, laser processing method and laser oscillator |
JP6189700B2 (en) * | 2013-10-03 | 2017-08-30 | 株式会社ディスコ | Wafer processing method |
CN104716066B (en) * | 2015-03-20 | 2018-03-30 | 上海华力微电子有限公司 | One kind detects the defects of figure bottom photoetching glue residua detection method |
JP6587911B2 (en) * | 2015-11-16 | 2019-10-09 | 株式会社ディスコ | Wafer division method |
CN106229309B (en) * | 2016-07-20 | 2019-05-07 | 日月光半导体(上海)有限公司 | Package substrate and its manufacturing method |
-
2018
- 2018-07-31 JP JP2018143126A patent/JP7072993B2/en active Active
-
2019
- 2019-07-05 KR KR1020190081485A patent/KR20200014195A/en not_active Application Discontinuation
- 2019-07-09 CN CN201910614448.5A patent/CN110783185B/en active Active
- 2019-07-18 SG SG10201906679RA patent/SG10201906679RA/en unknown
- 2019-07-26 TW TW108126555A patent/TWI800668B/en active
Also Published As
Publication number | Publication date |
---|---|
JP2020021786A (en) | 2020-02-06 |
JP7072993B2 (en) | 2022-05-23 |
CN110783185B (en) | 2023-10-10 |
KR20200014195A (en) | 2020-02-10 |
TW202008452A (en) | 2020-02-16 |
CN110783185A (en) | 2020-02-11 |
TWI800668B (en) | 2023-05-01 |
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