MA36343B1 - Procédé de métallisation en cuivre destiné à la fabrication d'un circuit intégré en utilisant la technologie wafer level packaging 3d - Google Patents

Procédé de métallisation en cuivre destiné à la fabrication d'un circuit intégré en utilisant la technologie wafer level packaging 3d

Info

Publication number
MA36343B1
MA36343B1 MA36343A MA36343A MA36343B1 MA 36343 B1 MA36343 B1 MA 36343B1 MA 36343 A MA36343 A MA 36343A MA 36343 A MA36343 A MA 36343A MA 36343 B1 MA36343 B1 MA 36343B1
Authority
MA
Morocco
Prior art keywords
integrated circuit
wafer level
packaging technology
manufacturing
metallization process
Prior art date
Application number
MA36343A
Other languages
English (en)
Other versions
MA20150146A1 (fr
Inventor
Zahraoui Said
Sbiaa Zouhair
Original Assignee
Nemotek Technologies
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nemotek Technologies filed Critical Nemotek Technologies
Priority to MA36343A priority Critical patent/MA36343B1/fr
Priority to PCT/MA2014/000055 priority patent/WO2015147620A1/fr
Publication of MA20150146A1 publication Critical patent/MA20150146A1/fr
Publication of MA36343B1 publication Critical patent/MA36343B1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Procédé de métallisation 'à base de,cuivre de ligne de connexion (rdl) 32 et de vias traversant 34 (fig .La) destiné à la fabrication d'un circuit intégré en généralet d'un capteur d'image en particulier en utilisant ta technologie wafer level packaging 3d , permettant de réduire le co,ût defabrication et d'avoir une meilleure performance électrique au niveau du dit capteur d'image 1 notamment pour la réalisation des interconnexions dans des circuits intégrés en trois dimensions.
MA36343A 2013-10-14 2013-10-14 Procédé de métallisation en cuivre destiné à la fabrication d'un circuit intégré en utilisant la technologie wafer level packaging 3d MA36343B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
MA36343A MA36343B1 (fr) 2013-10-14 2013-10-14 Procédé de métallisation en cuivre destiné à la fabrication d'un circuit intégré en utilisant la technologie wafer level packaging 3d
PCT/MA2014/000055 WO2015147620A1 (fr) 2013-10-14 2014-12-15 Procédé de métallisation en cuivre destiné à la fabrication d'un circuit intégré en utilisant la technologie wafer level packaging 3d

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
MA36343A MA36343B1 (fr) 2013-10-14 2013-10-14 Procédé de métallisation en cuivre destiné à la fabrication d'un circuit intégré en utilisant la technologie wafer level packaging 3d

Publications (2)

Publication Number Publication Date
MA20150146A1 MA20150146A1 (fr) 2015-05-29
MA36343B1 true MA36343B1 (fr) 2016-04-29

Family

ID=52589735

Family Applications (1)

Application Number Title Priority Date Filing Date
MA36343A MA36343B1 (fr) 2013-10-14 2013-10-14 Procédé de métallisation en cuivre destiné à la fabrication d'un circuit intégré en utilisant la technologie wafer level packaging 3d

Country Status (2)

Country Link
MA (1) MA36343B1 (fr)
WO (1) WO2015147620A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10211052B1 (en) * 2017-09-22 2019-02-19 Lam Research Corporation Systems and methods for fabrication of a redistribution layer to avoid etching of the layer

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10356885B4 (de) * 2003-12-03 2005-11-03 Schott Ag Verfahren zum Gehäusen von Bauelementen und gehäustes Bauelement
CN101675516B (zh) * 2007-03-05 2012-06-20 数字光学欧洲有限公司 具有通过过孔连接到前侧触头的后侧触头的芯片
KR100889553B1 (ko) * 2007-07-23 2009-03-23 주식회사 동부하이텍 시스템 인 패키지 및 그 제조 방법
US8710680B2 (en) * 2010-03-26 2014-04-29 Shu-Ming Chang Electronic device package and fabrication method thereof
JP5352534B2 (ja) * 2010-05-31 2013-11-27 パナソニック株式会社 半導体装置及びその製造方法
JP5810921B2 (ja) * 2012-01-06 2015-11-11 凸版印刷株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
MA20150146A1 (fr) 2015-05-29
WO2015147620A1 (fr) 2015-10-01

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