TW200703524A - Method for fabricating conductive line - Google Patents

Method for fabricating conductive line

Info

Publication number
TW200703524A
TW200703524A TW094122796A TW94122796A TW200703524A TW 200703524 A TW200703524 A TW 200703524A TW 094122796 A TW094122796 A TW 094122796A TW 94122796 A TW94122796 A TW 94122796A TW 200703524 A TW200703524 A TW 200703524A
Authority
TW
Taiwan
Prior art keywords
conductive line
substrate
conductive
conductive layer
fabricating conductive
Prior art date
Application number
TW094122796A
Other languages
Chinese (zh)
Other versions
TWI263288B (en
Inventor
Pin-Yao Wang
Liang-Chuan Lai
Jeng-Huan Yang
Original Assignee
Powerchip Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powerchip Semiconductor Corp filed Critical Powerchip Semiconductor Corp
Priority to TW094122796A priority Critical patent/TWI263288B/en
Priority to US11/164,950 priority patent/US7235442B2/en
Application granted granted Critical
Publication of TWI263288B publication Critical patent/TWI263288B/en
Publication of TW200703524A publication Critical patent/TW200703524A/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40114Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324Gate electrodes for transistors with a floating gate
    • H01L29/42336Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method for fabricating a conductive line is provided. First, a substrate, in which two or more insulated structures have been formed, is provided. A first conductive layer is formed between every two insulated structures. Then, a dielectric layer is formed on the substrate. Pattern the dielectric layer to form an opening making the first conductive layer exposed. After that, a second conductive layer is formed on the substrate. Remove a portion of second conductive layer outside of the opening to form a conductive line. As scale of the device is getting smaller, the size and the accuracy of position of the conductive line would not be limited by design rules of lithography if the provided method is applied. Therefore, a conductive line is formed to effectively and electrically connect semiconductors.
TW094122796A 2005-07-06 2005-07-06 Method for fabricating conductive line TWI263288B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW094122796A TWI263288B (en) 2005-07-06 2005-07-06 Method for fabricating conductive line
US11/164,950 US7235442B2 (en) 2005-07-06 2005-12-12 Method for fabricating conductive line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094122796A TWI263288B (en) 2005-07-06 2005-07-06 Method for fabricating conductive line

Publications (2)

Publication Number Publication Date
TWI263288B TWI263288B (en) 2006-10-01
TW200703524A true TW200703524A (en) 2007-01-16

Family

ID=37618791

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094122796A TWI263288B (en) 2005-07-06 2005-07-06 Method for fabricating conductive line

Country Status (2)

Country Link
US (1) US7235442B2 (en)
TW (1) TWI263288B (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7955644B2 (en) * 2006-07-10 2011-06-07 California Institute Of Technology Method for selectively anchoring large numbers of nanoscale structures
US8846143B2 (en) 2006-07-10 2014-09-30 California Institute Of Technology Method for selectively anchoring and exposing large numbers of nanoscale structures
KR100900301B1 (en) * 2007-04-27 2009-06-02 삼성전자주식회사 Memory Semiconductor Devices With Buried Bit Line And Methods Of Fabricating The Same
US7959969B2 (en) 2007-07-10 2011-06-14 California Institute Of Technology Fabrication of anchored carbon nanotube array devices for integrated light collection and energy conversion
EP2381972A2 (en) 2009-01-27 2011-11-02 California Institute Of Technology Drug delivery and substance transfer facilitated by nano-enhanced device having aligned carbon nanotubes protruding from device surface
US9115424B2 (en) 2010-04-07 2015-08-25 California Institute Of Technology Simple method for producing superhydrophobic carbon nanotube array
WO2012079066A2 (en) 2010-12-10 2012-06-14 California Institute Of Technology Method for producing graphene oxide with tunable gap
US8976507B2 (en) 2011-03-29 2015-03-10 California Institute Of Technology Method to increase the capacitance of electrochemical carbon nanotube capacitors by conformal deposition of nanoparticles
WO2013090844A1 (en) 2011-12-14 2013-06-20 California Institute Of Technology Sharp tip carbon nanotube microneedle devices and their fabrication
WO2014022314A1 (en) 2012-07-30 2014-02-06 California Institute Of Technology Nano tri-carbon composite systems and manufacture

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420220B1 (en) * 1999-04-16 2002-07-16 Advanced Micro Devices, Inc. Method of forming electrode for high performance semiconductor devices
TWI233665B (en) * 2004-02-12 2005-06-01 Powerchip Semiconductor Corp Method of fabricating a flash memory

Also Published As

Publication number Publication date
US20070010053A1 (en) 2007-01-11
US7235442B2 (en) 2007-06-26
TWI263288B (en) 2006-10-01

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