JP5486376B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5486376B2 JP5486376B2 JP2010080938A JP2010080938A JP5486376B2 JP 5486376 B2 JP5486376 B2 JP 5486376B2 JP 2010080938 A JP2010080938 A JP 2010080938A JP 2010080938 A JP2010080938 A JP 2010080938A JP 5486376 B2 JP5486376 B2 JP 5486376B2
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Description
はじめに、本発明の第1実施形態による半導体装置を以下に説明する。
次に、本発明の第2実施形態による半導体装置の説明を行う。本実施形態の半導体装置は、GND配線3のレイアウトが異なる。
次に、本発明の第3実施形態による半導体装置の説明を行う。本実施形態の半導体装置は、GND配線3のレイアウトが異なる。
2、2a〜2d 新パッド
3 GND配線
4、4a〜4h パッド
5 回路
6 信号配線
7 スルーホール
10 第一の半導体装置
11 パッド
20 第二の半導体装置
21 シリコン基板
22 多層配線層
23a〜23c 第1〜第3配線層
24a〜24c 第1〜第3層間絶縁膜
30 再配線層
31 絶縁膜
32 ポリイミド
40 封止樹脂
50 パッケージ基板
60 ボンディングワイヤ
100 チップ
101 キャパシタ
110 基板
120 多層配線
130、130a、130b 層間絶縁膜
140、140a、140b 信号配線
150 メタル部材
200 電極
300、300a、300b 絶縁膜
400 外部端子
500 再配線
Claims (5)
- 回路の形成された基板と、
前記基板上に形成される複数の配線層と前記複数の配線層の最上層において所定の位置に形成されるパッドとを具備する多層配線層と、
前記多層配線層上の適切な位置に設けられた新パッドと、前記新パッドと前記パッドとを接続する再配線とを具備する再配線層と
を備え、
前記多層配線層は、
前記回路への電気信号を伝送する信号配線と、
前記再配線あるいは前記新パッドと前記回路との間の配線層に設けられたGND配線とを含み、
前記GND配線は、前記新パッドの配置が想定される想定位置と、前記再配線の形成が想定される想定ルートに対応して形成され、
前記GND配線は、前記多層配線層の前記複数の配線層のうちいずれかの層、あるいは複数の層にまたがって形成され、
前記GND配線層は、格子状に形成され、
前記GND配線は、前記新パッドが形成されるべき前記多層配線層の外周に沿って形成され、
前記GND配線は、レイアウト、及び、回路特性の制約の範囲内で面積を可能な限り広くし、
前記再配線は、前記パッドと前記新パッドとを接続している区間では、平面視において、格子状に形成された前記GND配線の一部と重なって形成されている半導体装置。 - 前記再配線層は、前記パッド及び前記新パッドとは別の第1及び第2のパッドを接続する第2の再配線をさらに含み、前記第2の再配線は、前記第1のパッドと前記第2のパッドを接続している区間では、平面視において前記GND配線と重なって形成されている請求項1に記載の半導体装置。
- 前記第1の再配線が平面視において前記GND配線と重なっている区間は、前記第2の再配線が平面視において前記GND配線と重なっている区間より長いことを特徴とする請求項2に記載の半導体装置。
- 前記第1の再配線の一部と前記第2の再配線の一部は、略平行に延在していることを特徴とする請求項2に記載の半導体装置。
- 平面視において前記第1の再配線と重なるGND配線の、前記第1の再配線の延在方向と直交する方向の長さは、平面視において前記第2の配線と重なるGND配線の、前記第2の再配線の延在方向と直行する方向の長さより、長いことを特徴とする請求項2に記載の半導体装置。
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US12/929,968 US8237287B2 (en) | 2010-03-31 | 2011-02-28 | Semiconductor device |
CN201110085619.3A CN102208394B (zh) | 2010-03-31 | 2011-03-31 | 半导体器件 |
US13/490,871 US8436469B2 (en) | 2010-03-31 | 2012-06-07 | Semiconductor device |
US13/752,219 US8796860B2 (en) | 2010-03-31 | 2013-01-28 | Semiconductor device |
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JP5486376B2 (ja) * | 2010-03-31 | 2014-05-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9209124B2 (en) | 2010-05-11 | 2015-12-08 | Xintec Inc. | Chip package |
US9437478B2 (en) * | 2010-05-11 | 2016-09-06 | Xintec Inc. | Chip package and method for forming the same |
US8507321B2 (en) | 2010-05-11 | 2013-08-13 | Chao-Yen Lin | Chip package and method for forming the same |
US9425134B2 (en) * | 2010-05-11 | 2016-08-23 | Xintec Inc. | Chip package |
US20130146345A1 (en) * | 2011-12-12 | 2013-06-13 | Kazuki KAJIHARA | Printed wiring board and method for manufacturing the same |
US10403572B2 (en) * | 2016-11-02 | 2019-09-03 | Samsung Electronics Co., Ltd. | Semiconductor device and semiconductor package including the same |
JP7144951B2 (ja) | 2018-03-20 | 2022-09-30 | キオクシア株式会社 | 半導体装置 |
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CN102208394B (zh) | 2014-07-23 |
US20120241971A1 (en) | 2012-09-27 |
US20110241216A1 (en) | 2011-10-06 |
US8436469B2 (en) | 2013-05-07 |
US20130140717A1 (en) | 2013-06-06 |
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