JP7144951B2 - 半導体装置 - Google Patents
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- JP7144951B2 JP7144951B2 JP2018053315A JP2018053315A JP7144951B2 JP 7144951 B2 JP7144951 B2 JP 7144951B2 JP 2018053315 A JP2018053315 A JP 2018053315A JP 2018053315 A JP2018053315 A JP 2018053315A JP 7144951 B2 JP7144951 B2 JP 7144951B2
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
実施形態に係る接続導体は、接続ワイヤ40に限定されるものではなく、配線15と積層体20の上面に設けられた第1導体30とを、積層体20の外側で電気的に接続するものであれば良い。そのような例として、TAB(Taped Automated Bonding)もしくはVCI(Vertical Circuit Interconnection)を挙げることができる。
Claims (6)
- ベース部材と、
前記ベース部材上に配置され、前記ベース部材の上面と交差する方向に積層された複数の半導体チップを含み、前記複数の半導体チップのうちの最上段に位置する半導体チップの上面に第1絶縁部材が設けられた積層体と、
前記積層体の前記第1絶縁部材上に設けられた第1導体と、
前記第1導体を覆い、前記第1絶縁部材の開口内において前記第1絶縁部材の上端よりも低い下端を有する第2絶縁部材と、
前記ベース部材の上面に設けられた第2導体と、
前記第1導体と前記第2導体とを接続する接続導体と、
前記積層体および前記接続導体を前記ベース部材上にモールドした樹脂部材と、
を備え、
前記複数の半導体チップは、機能素子が配置された素子面と、前記素子面とは反対側の裏面と、を有し、前記裏面から前記素子面へ至る貫通電極をそれぞれ含み、
前記積層体は、前記複数の半導体チップの前記貫通電極を含み、各半導体チップに電気的に接続された共通端子を有し、
前記第1絶縁部材および前記第2絶縁部材は、それぞれポリイミドを含み、
前記共通端子は、前記複数の半導体チップのうちの最下段に位置する半導体チップの下面に設けられた下端と、前記複数の半導体チップのうちの前記最上段に位置する半導体チップの上面に設けられた上端と、を有し、
前記第1導体は、前記第1絶縁部材の前記開口内において前記共通端子の上端及び前記第2絶縁部材の間に設けられ、かつ前記共通端子の上端に接続された配線部と、前記第2絶縁部材の開口内に設けられたボンディングパッド部と、を含み、
前記接続導体は、前記第1導体の前記ボンディングパッド部に接続され、
前記第2導体は、前記接続導体を介して前記第1導体に接続されると共に、前記共通端子の下端に電気的に接続された半導体装置。 - 前記複数の前記半導体チップは、それぞれ、前記素子面が前記ベース部材と向き合うように積層され、
前記第1導体は、前記最上段に位置する半導体チップの裏面上に設けられ、
前記第1導体は、前記最上段に位置する半導体チップの貫通電極に接続される請求項1記載の半導体装置。 - 前記機能素子は、複数のメモリセルを含む請求項1または2に記載の半導体装置。
- 前記ベース部材の下面に配置された電源端子をさらに備え、
前記第2導体は、前記電源端子に電気的に接続された請求項1~3のいずれか1つに記載の半導体装置。 - 前記複数の半導体チップは、それぞれの前記裏面に設けられた接続バンプを介して相互に接続される請求項1~4のいずれか1つに記載の半導体装置。
- 前記積層体上に設けられ、前記第1導体を含む複数の第1導体と、
前記ベース部材の上面に設けられ、前記第2導体を含む複数の第2導体と、
前記複数の第1導体と前記複数の第2導体とをそれぞれ接続する複数の接続導体と、
をさらに備え、
前記積層体は、前記複数の半導体チップに共有される、前記共通端子を含む複数の共通端子を含み、
前記複数の第1導体は、前記複数の共通端子の上端にそれぞれ接続され、
前記複数の第2導体は、前記複数の接続導体を介して前記複数の第1導体にそれぞれ接続されると共に、複数の共通端子の下端にそれぞれ電気的に接続され、
前記複数の共通端子は、相互に異なる電位を前記複数の半導体チップに供給することができる請求項1~5のいずれか1つに記載の半導体装置。
Priority Applications (4)
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JP2018053315A JP7144951B2 (ja) | 2018-03-20 | 2018-03-20 | 半導体装置 |
TW107124767A TWI695484B (zh) | 2018-03-20 | 2018-07-18 | 半導體裝置 |
CN201810895900.5A CN110310946B (zh) | 2018-03-20 | 2018-08-08 | 半导体装置 |
US16/121,150 US10593649B2 (en) | 2018-03-20 | 2018-09-04 | Semiconductor device |
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JP2018053315A JP7144951B2 (ja) | 2018-03-20 | 2018-03-20 | 半導体装置 |
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JP2019165179A JP2019165179A (ja) | 2019-09-26 |
JP7144951B2 true JP7144951B2 (ja) | 2022-09-30 |
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TW (1) | TWI695484B (ja) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002057271A (ja) | 2000-08-10 | 2002-02-22 | Matsushita Electric Ind Co Ltd | 半導体装置、およびその製造方法 |
JP2007194444A (ja) | 2006-01-20 | 2007-08-02 | Elpida Memory Inc | 積層型半導体装置 |
JP2017152648A (ja) | 2016-02-26 | 2017-08-31 | 東芝メモリ株式会社 | 半導体装置 |
Family Cites Families (11)
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JPS5936968B2 (ja) | 1980-12-16 | 1984-09-06 | 日揮株式会社 | エタノ−ルまたはアセトアルデヒドから酢酸を製造する方法 |
JP4858692B2 (ja) | 2006-06-22 | 2012-01-18 | 日本電気株式会社 | チップ積層型半導体装置 |
JP5486376B2 (ja) | 2010-03-31 | 2014-05-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8710654B2 (en) | 2011-05-26 | 2014-04-29 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
JP5936968B2 (ja) | 2011-09-22 | 2016-06-22 | 株式会社東芝 | 半導体装置とその製造方法 |
JP5677489B2 (ja) | 2013-03-07 | 2015-02-25 | 株式会社日立製作所 | 半導体装置 |
JP2015056563A (ja) * | 2013-09-12 | 2015-03-23 | 株式会社東芝 | 半導体装置およびその製造方法 |
TWI616979B (zh) * | 2014-03-14 | 2018-03-01 | Toshiba Memory Corp | 半導體裝置及其製造方法 |
US10438929B2 (en) * | 2014-09-17 | 2019-10-08 | Toshiba Memory Corporation | Semiconductor device |
JP6479579B2 (ja) * | 2015-05-29 | 2019-03-06 | 東芝メモリ株式会社 | 半導体装置 |
JP6753743B2 (ja) * | 2016-09-09 | 2020-09-09 | キオクシア株式会社 | 半導体装置の製造方法 |
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- 2018-03-20 JP JP2018053315A patent/JP7144951B2/ja active Active
- 2018-07-18 TW TW107124767A patent/TWI695484B/zh active
- 2018-08-08 CN CN201810895900.5A patent/CN110310946B/zh active Active
- 2018-09-04 US US16/121,150 patent/US10593649B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2002057271A (ja) | 2000-08-10 | 2002-02-22 | Matsushita Electric Ind Co Ltd | 半導体装置、およびその製造方法 |
JP2007194444A (ja) | 2006-01-20 | 2007-08-02 | Elpida Memory Inc | 積層型半導体装置 |
JP2017152648A (ja) | 2016-02-26 | 2017-08-31 | 東芝メモリ株式会社 | 半導体装置 |
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Publication number | Publication date |
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TWI695484B (zh) | 2020-06-01 |
TW201941399A (zh) | 2019-10-16 |
CN110310946B (zh) | 2023-07-18 |
US10593649B2 (en) | 2020-03-17 |
US20190295987A1 (en) | 2019-09-26 |
CN110310946A (zh) | 2019-10-08 |
JP2019165179A (ja) | 2019-09-26 |
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