CN110299344B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN110299344B
CN110299344B CN201810895152.0A CN201810895152A CN110299344B CN 110299344 B CN110299344 B CN 110299344B CN 201810895152 A CN201810895152 A CN 201810895152A CN 110299344 B CN110299344 B CN 110299344B
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contact pad
semiconductor
electrode
functional layer
electrically connected
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CN110299344A (zh
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筑山慧至
小柳胜
伊东干彦
河崎一茂
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Kioxia Corp
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Kioxia Corp
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

实施方式提供一种能够实现高速信号收发的半导体装置。半导体装置具备：基底部件；以及多个半导体芯片，积层在基底部件上，且经由连接部件相互电连接；多个半导体芯片中的第1半导体芯片包含：半导体衬底，具有元件面及其相反侧的背面；功能层，设置在元件面上；以及多个贯通电极，在半导体衬底中从背面延伸到元件面，电连接于功能层；第1半导体芯片经由连接于多个贯通电极的连接部件而电连接于多个半导体芯片中相邻的第2半导体芯片；功能层包含：第1接触垫；以及第2接触垫，位于多个半导体芯片的积层方向上的半导体衬底与第1接触垫之间的层级；多个贯通电极包含：第1贯通电极，连接于第1接触垫；以及第2贯通电极，连接于第2接触垫。

Description

半导体装置
[相关申请]
本申请享有以日本专利申请2018-55227号(申请日：2018年3月22日)为基础申请的优先权。本申请是通过参照该基础申请而包含基础申请的全部内容。
技术领域
实施方式涉及一种半导体装置。
背景技术
存在基底衬底上积层多个半导体芯片的构造的半导体装置。这种半导体装置中，将基底衬底上的配线与各半导体芯片之间用金属线电连接，并经由基底衬底的配线将外部电路与各芯片电连接。然而，对于外部电路与各半导体芯片之间的高速信号的收发，金属线的寄生电容及寄生电感成为了障碍。
发明内容
实施方式提供一种能够实现高速信号收发的半导体装置。
实施方式的半导体装置具备：基底部件；以及多个半导体芯片，积层在所述基底部件上，且经由连接部件相互电连接；所述多个半导体芯片中的第1半导体芯片包含：半导体衬底，具有元件面及其相反侧的背面；功能层，设置在所述元件面上；以及多个贯通电极，在所述半导体衬底中从所述背面延伸到所述元件面，电连接于所述功能层；所述第1半导体芯片是经由连接于所述多个贯通电极的所述连接部件而电连接于所述多个半导体芯片中相邻的第2半导体芯片；所述功能层包含：第1接触垫；以及第2接触垫，位于所述多个半导体芯片的积层方向上的所述半导体衬底与所述第1接触垫之间的层级；所述多个贯通电极包含：第1贯通电极，连接于所述第1接触垫；以及第2贯通电极，连接于所述第2接触垫。
附图说明
图1是表示实施方式的半导体装置的示意剖视图。
图2是以示意的方式表示实施方式的半导体装置的连接构造的局部剖视图。
图3是以示意的方式表示实施方式的半导体装置的另一连接构造的局部剖视图。
图4是表示实施方式的半导体装置的功能层的构成的框图。
图5是表示实施方式的半导体装置的功能层的示意剖视图。
具体实施方式
以下，一边参照附图，一边对实施方式进行说明。对于附图中的同一部分标附同一编号并适当省略其详细说明，而对不同部分进行说明。此外，附图是示意性或概念性的图，各部分的厚度与宽度的关系、部分间的大小的比率等未必与实物相同。另外，即使在表示相同部分的情况下，根据附图也存在相互的尺寸或比率不同地被表示出来的情况。
进而，用各图中所示的X轴、Y轴及Z轴来说明各部分的配置及构成。X轴、Y轴、Z轴相互正交，分别表示X方向、Y方向、Z方向。另外，存在将Z方向作为上方且将其相反方向作为下方进行说明的情况。
图1是表示实施方式的半导体装置1的示意剖视图。半导体装置1具备基底部件10及多个半导体芯片SC1～SCn。半导体芯片SC1～SCn积层在基底部件10上。另外，半导体芯片SC1～SCn经由连接部件(以下为微凸点13)而相互电连接。
半导体芯片SC1～SCn-1包含多个贯通电极VC(例如硅通孔(Through SiliconVia：TSV))，且经由连接于各个贯通电极VC的微凸点13而相互电连接。在半导体芯片SC1～SCn中位于最下段的半导体芯片SC1的下表面，设置有配线15。配线15电连接于半导体芯片SC1。半导体芯片SC1是利用连接于配线15的连接凸点17而连接于基底部件10。
半导体芯片SC1～SCn隔着微凸点13依次倒装片接合。微凸点13例如具有直径5～50μm的尺寸，且以10～100μm的间距配置在半导体衬底SS的背面上。贯通电极VC沿着半导体衬底SS的背面以例如10～100μm的间距配置。
如图1所示，半导体装置1还具备配置在基底部件10与半导体芯片SC1之间的逻辑芯片20。逻辑芯片20例如经由倒装片凸点(以下为FC凸点23)连接于配线15。逻辑芯片20与半导体芯片SC1～SCn经由配线15进行例如数据及指令的收发。
基底部件10具有与配置有半导体芯片SC1～SCn的上表面为相反侧的下表面，多个连接凸点25配置在基底部件10的下表面。连接凸点25经由设置在基底部件10的配线及连接插塞(未图示)而电连接于半导体芯片SC1～SCn及逻辑芯片20。连接凸点25将半导体装置1例如连接于未图示的安装衬底，并且将半导体芯片SC1～SCn及逻辑芯片20连接于外部电路。
如此，半导体装置1中，通过将半导体芯片SC1～SCn经由贯通电极VC及微凸点13相互连接，从而能让它们与逻辑芯片20之间进行高速信号的收发。
图2及图3是以示意的方式表示实施方式的半导体装置1的连接构造的局部剖视图。图2是表示将半导体芯片SC1～SCn相互连接的端子部TP1的示意剖视图。图3是表示另一端子部TP2的示意剖视图。
如图2及图3所示，半导体芯片SC1～SCn分别包含半导体衬底SS与功能层FL。半导体衬底SS例如具有元件面SST及其相反侧的背面SSB。功能层FL例如包含存储元件，设置在元件面SST之上。
图2所示的端子部TP1包含贯通电极VC1与微凸点CP。贯通电极VC1将半导体衬底SS从背面SSB贯通到元件面SST，电连接于功能层FL。微凸点CP设置在功能层FL的正面侧。
贯通电极VC1利用绝缘膜31而与半导体衬底SS电绝缘。另外，贯通电极VC1经由微凸点13连接于与半导体衬底SS的背面SSB侧相邻的半导体芯片的功能层FL。微凸点CP经由另一微凸点13连接于与功能层FL的正面侧相邻的半导体芯片的背面。
功能层FL在贯通电极VC1与微凸点CP之间包含多个接触垫CMB、CM0、CM1及CM2。接触垫CMB、CM0、CM1及CM2在从贯通电极VC1朝向微凸点CP的方向上依次配置。
在各接触垫间设置有层间绝缘膜33。接触垫CMB隔着绝缘膜35设置在半导体衬底SS上。接触垫CMB经由多个接触插塞C0连接于接触垫CM0。接触垫CM0经由多个接触插塞C1连接于接触垫CM1。另外，接触垫CM1经由多个接触插塞C2连接于接触垫CM2。另外，接触垫CM1例如设置在与Z方向上的功能层FL的配线层M1的层级相同的层级，且连接于配线层M1中的配线。
贯通电极VC1贯穿绝缘膜35而延伸，连接于接触垫CMB。微凸点CP贯穿覆盖功能层FL表面的绝缘膜37而延伸，连接于接触垫CM2。连接各接触垫间的接触插塞C0、C1及C2的X方向及Y方向的宽度比贯通电极VC1的X方向及Y方向的宽度窄，且比微凸点CP的X方向及Y方向的宽度窄。
图3所示的端子部TP2包含贯通电极VC2与微凸点CP。贯通电极VC2将半导体衬底SS从背面SSB贯通到元件面SST，电连接于功能层FL。贯通电极VC2利用绝缘膜31而与半导体衬底SS电绝缘。
在端子部TP2，未设置接触垫CMB及接触插塞C0，贯通电极VC2直接连接于接触垫CM0。另外，贯通电极VC2连接于接触垫CM0的部分的X方向的宽度W2比贯通电极VC1连接于接触垫CMB的部分的X方向的宽度W1(参照图2)宽。
图4是表示实施方式的半导体装置1的功能层FL的构成的框图。功能层FL例如为存储元件，包含存储单元阵列MCA与控制电路DRC。
控制电路DRC例如经由行解码器R/D、列解码器C/D、数据控制电路DCC、接口电路I/F及升压电路U/C来控制存储单元阵列MCA的动作。
如图4所示，对功能层FL供给例如外部电压VCC、VPP及VSS。另外，接口电路I/F例如与逻辑芯片20之间进行数据及指令的收发。
外部电压VCC例如被供给至降压电路D/C，降压电路D/C向功能道内的各电路块供给内部电压VDD。外部电压VPP例如被供给至升压电路U/C，升压电路U/C例如向行解码器供给编程电压，向存储单元阵列MCA供给数据删除电压。
接口电路I/F例如经由端子部TP1进行数据及指令的收发。外部电压VCC、VPP及VSS例如经由多个端子部TP2被分别供给。
在端子部TP2，例如未设置接触垫CMB及接触插塞C0，贯通电极VC2直接连接于接触垫CM0。由此，能降低贯通电极VC2与微凸点CP之间的电阻。
例如，随着功能层FL中所包含的存储单元阵列MCA及各电路的微细化进展，接触插塞C0、C1及C2的X方向及Y方向的宽度也变窄，而内部阻抗变大。因此，贯通电极VC与微凸点CP之间的内部阻抗也变大，因其电压降低而使得经由端子部TP供给至半导体芯片SC1～SCn的电压变得各不相同，而有产生各功能层FL的误动作的担忧。
本实施方式中，通过经由端子部TP2供给外部电压，从而能够降低其内部阻抗，抑制被供给至半导体芯片SC1～SCn的电压的差。另一方面，在端子部TP1，由于使用的是与贯通电极VC2相比X方向及Y方向的宽度较窄的贯通电极VC1，所以在逻辑芯片20与各功能层FL的接口电路I/F之间能够进行更高速的收发。
图5是例示实施方式的半导体装置的功能层FL的示意剖视图。功能层FL例如为包含经三维配置的存储单元MC的NAND(Not and，与非)型存储元件。
如图5所示，存储单元阵列MCA包含积层在半导体衬底SS上方的多个电极层(例如选择栅极SGS、字线WL、选择栅极SGD)及半导体通道SC。半导体通道SC贯穿多个电极层而在Z方向上延伸。存储单元MC设置在半导体通道SC与字线WL交叉的部分。
在多个电极层中位于最下层的选择栅极SGS与半导体衬底SS之间，设置有源极层SL。源极层SL连接于半导体通道SC。另外，在半导体衬底SS与源极层SL之间，配置有包含设置在半导体衬底SS表层的晶体管Tr的电路。
在多个电极层的上方，设置有配线层M0及M1。配线层M0位于多个电极层与配线层M1之间，例如包含连接于半导体通道SC的位线BL及连接于各电极层的栅极配线GL。
在存储单元阵列MCA，配置有接触插塞CG、CS、CC及VB。接触插塞CG将各电极层连接于栅极配线GL。接触插塞CS将源极层SL连接于配线层M0中的其它配线。接触插塞CC将下层的电路连接于配线层M0中进而其它的配线。另外，接触插塞VB将配线层M0中的配线连接于配线层M1中的配线。
端子部TP1包含设置在贯通电极VC1与微凸点CP(参照图2)之间的接触垫CMB、接触垫CM0及接触垫CM1。
如图5所示，接触垫CMB配置在与Z方向上的源极层SL的层级相同的位置。接触垫CM0配置在与Z方向上的配线层M0的层级相同的位置。接触垫CM1配置在与Z方向上的配线层M1的层级相同的位置。另外，接触垫CM1在未图示的部分与配线层M1中的配线连接。
接触垫CMB与接触垫CM0经由多个接触插塞C0而电连接。接触插塞C0配置在与存储单元阵列MCA中的接触插塞CG、CS及CC相同的层级。也就是说，在半导体芯片SC1～SCn的制造过程中，接触插塞C0是在与接触插塞CG、CS及CC同一制造过程中形成。因此，接触插塞C0具有与接触插塞CG、CS及CC大致相同的尺寸。
进而，接触垫CM0与接触垫CM1经由多个接触插塞C1而电连接。接触插塞C1配置在与存储单元阵列MCA中的接触插塞VB相同的层级。也就是说，在半导体芯片SC1～SCn的制造过程中，接触插塞C1是在与接触插塞VB同一制造过程中形成，具有与接触插塞VB大致相同的尺寸。
如此，在端子部TP1，连接贯通电极VC1与微凸点CP之间的接触垫CMB～CM1、接触插塞C0及C1是与存储单元阵列MCA同时形成。因此，当存储单元阵列MCA的微细化进展时，接触插塞C0及C1的尺寸也缩小，而其内部阻抗变大。因此，在为了向功能层FL供给外部电压而设置的端子部TP2，减少接触垫CMB～CM1的层数，将贯通电极VC2连接于更上层的接触垫。由此，能够抑制被供给至功能层FL的电压VCC、VPP及VSS的偏差。图5所示的功能层FL还包含配置在未图示部分的端子部TP2。
已对本发明的几个实施方式进行了说明，但这些实施方式是作为例子提出的，并未意图限定发明的范围。这些新颖的实施方式能以其它各种方式实施，且能够在不脱离发明主旨的范围内进行各种省略、替换、变更。这些实施方式或其变化包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明及其均等的范围内。
[符号的说明]
1 半导体装置
10 基底部件
13 微凸点
15 配线
17、25 连接凸点
20 逻辑芯片
23 FC凸点
31、35、37 绝缘膜
33 层间绝缘膜
C/D 列解码器
C0、C1、C2、CC、CG、CS、VB 接触插塞
CM0、CM1、CM2、CMB 接触垫
CP 微凸点
SC1～SCn 半导体芯片
FL 功能层
SS 半导体衬底
TP、TP1、TP2 端子部
VC、VC1、VC2 贯通电极
M0、M1 配线层
MC 存储单元
MCA 存储单元阵列
DCC 数据控制电路
DRC 控制电路
R/D 行解码器
I/F 接口电路
U/C 升压电路
D/C 降压电路
WL 字线
SGD、SGS 选择栅极
SC 半导体通道
SL 源极层
BL 位线
GL 栅极配线
SSB 背面
SST 元件面
Tr 晶体管

Claims (19)

1.一种半导体装置，具备：
基底部件；以及
多个半导体芯片，积层在所述基底部件上，经由连接部件而相互电连接；且
所述多个半导体芯片中的第1半导体芯片包含：半导体衬底，具有元件面及其相反侧的背面；功能层，设置在所述元件面上；以及多个贯通电极，在所述半导体衬底中从所述背面延伸到所述元件面，电连接于所述功能层；
所述第1半导体芯片经由连接于所述多个贯通电极的所述连接部件而电连接于所述多个半导体芯片中相邻的第2半导体芯片；
所述功能层包含：第1接触垫；以及第2接触垫，位于所述多个半导体芯片的积层方向上的所述半导体衬底与所述第1接触垫之间的层级；
所述多个贯通电极包含：第1贯通电极，连接于所述第1接触垫；以及第2贯通电极，连接于所述第2接触垫；
所述多个半导体芯片分别包含将所述多个贯通电极与所述半导体衬底电绝缘的绝缘膜。
2.根据权利要求1所述的半导体装置，其中所述第1半导体芯片构成为经由所述第1贯通电极及所述第1接触垫向所述功能层供给外部电压。
3.一种半导体装置，具备：
基底部件；
多个半导体芯片，积层在所述基底部件上，经由连接部件而相互电连接；以及
设置在所述多个半导体芯片中配置在最接近所述基底部件的位置上的半导体芯片与所述基底部件之间且向所述多个半导体芯片发送信号的另一半导体芯片；且
所述多个半导体芯片中的第1半导体芯片包含：半导体衬底，具有元件面及其相反侧的背面；功能层，设置在所述元件面上；以及多个贯通电极，在所述半导体衬底中从所述背面延伸到所述元件面，电连接于所述功能层；
所述第1半导体芯片经由连接于所述多个贯通电极的所述连接部件而电连接于所述多个半导体芯片中相邻的第2半导体芯片；
所述功能层包含：第1接触垫；以及第2接触垫，位于所述多个半导体芯片的积层方向上的所述半导体衬底与所述第1接触垫之间的层级；
所述多个贯通电极包含：第1贯通电极，连接于所述第1接触垫；以及第2贯通电极，连接于所述第2接触垫；
所述第1半导体芯片构成为经由所述第2贯通电极及所述第2接触垫向所述功能层发送所述信号。
4.一种半导体装置，具备：
基底部件；以及
多个半导体芯片，积层在所述基底部件上，经由连接部件而相互电连接；且
所述多个半导体芯片中的第1半导体芯片包含：半导体衬底，具有元件面及其相反侧的背面；功能层，设置在所述元件面上；以及多个贯通电极，在所述半导体衬底中从所述背面延伸到所述元件面，电连接于所述功能层；
所述第1半导体芯片经由连接于所述多个贯通电极的所述连接部件而电连接于所述多个半导体芯片中相邻的第2半导体芯片；
所述功能层包含：第1接触垫；以及第2接触垫，位于所述多个半导体芯片的积层方向上的所述半导体衬底与所述第1接触垫之间的层级；
所述多个贯通电极包含：第1贯通电极，连接于所述第1接触垫；以及第2贯通电极，连接于所述第2接触垫；
所述第2贯通电极的与所述积层方向交叉的第1方向的宽度比所述第1贯通电极的所述第1方向的宽度窄。
5.一种半导体装置，具备：
基底部件；以及
多个半导体芯片，积层在所述基底部件上，经由连接部件而相互电连接；且
所述多个半导体芯片中的第1半导体芯片包含：半导体衬底，具有元件面及其相反侧的背面；功能层，设置在所述元件面上；以及多个贯通电极，在所述半导体衬底中从所述背面延伸到所述元件面，电连接于所述功能层；
所述第1半导体芯片经由连接于所述多个贯通电极的所述连接部件而电连接于所述多个半导体芯片中相邻的第2半导体芯片；
所述功能层包含：第1接触垫；以及第2接触垫，位于所述多个半导体芯片的积层方向上的所述半导体衬底与所述第1接触垫之间的层级；
所述多个贯通电极包含：第1贯通电极，连接于所述第1接触垫；以及第2贯通电极，连接于所述第2接触垫；
所述功能层包含：配线层，位于所述积层方向上与所述第1接触垫的层级最接近的层级；以及第3接触垫，位于与所述配线层的所述积层方向的层级相同的层级，连接于所述配线层中的配线；
所述第2接触垫位于所述第2贯通电极与所述第3接触垫之间，经由多个第1接触插塞而电连接于所述第3接触垫；
所述多个第1接触插塞在与所述积层方向交叉的第1方向上的宽度比所述第1贯通电极及所述第2贯通电极的所述第1方向的宽度窄。
6.根据权利要求5所述的半导体装置，其中所述功能层还包含位于所述第2接触垫与所述第3接触垫之间的第4接触垫；
所述第2接触垫经由所述多个第1接触插塞而连接于所述第4接触垫；
所述第4接触垫经由多个第2接触插塞而连接于所述第3接触垫。
7.一种半导体装置，具备：
基底部件；以及
多个半导体芯片，积层在所述基底部件上，经由连接部件而相互电连接；且
所述多个半导体芯片中的第1半导体芯片包含：半导体衬底，具有元件面及其相反侧的背面；功能层，设置在所述元件面上；以及多个贯通电极，在所述半导体衬底中从所述背面延伸到所述元件面，电连接于所述功能层；
所述第1半导体芯片经由连接于所述多个贯通电极的所述连接部件而电连接于所述多个半导体芯片中相邻的第2半导体芯片；
所述功能层包含：第1接触垫；以及第2接触垫，位于所述多个半导体芯片的积层方向上的所述半导体衬底与所述第1接触垫之间的层级；
所述多个贯通电极包含：第1贯通电极，连接于所述第1接触垫；以及第2贯通电极，连接于所述第2接触垫；
所述多个半导体芯片还包含与所述第1半导体芯片相邻的第3半导体芯片；
所述第1半导体芯片位于所述第2半导体芯片与所述第3半导体芯片之间，且经由所述连接部件之外的另一连接部件而电连接于所述第3半导体芯片；
所述功能层包含连接于所述另一连接部件的第5接触垫。
8.根据权利要求7所述的半导体装置，其中所述第1接触垫及所述第2接触垫位于所述积层方向上的所述第5接触垫与所述半导体衬底之间的层级。
9.根据权利要求7所述的半导体装置，其中所述功能层包含：配线层，位于所述积层方向上与所述第1接触垫的层级接近的层级；以及第3接触垫，位于与所述配线层的所述积层方向的层级相同的层级，连接于所述配线层中的配线；且
所述第5接触垫经由多个第3接触插塞而连接于所述第3接触垫。
10.一种半导体装置，具备：
基底部件；以及
多个存储芯片，积层在所述基底部件上，经由连接部件而相互电连接；
所述多个存储芯片中的第1存储芯片包含：半导体衬底，具有元件面及其相反侧的背面；存储单元阵列，设置在所述元件面上，包含多个存储单元；端子部，电连接于所述存储单元阵列；以及多个贯通电极，在所述半导体衬底中从所述背面延伸到所述元件面，连接于所述端子部；
所述第1存储芯片经由连接于所述多个贯通电极的所述连接部件而电连接于所述多个存储芯片中相邻的第2存储芯片；
所述端子部包含：第1接触垫；以及第2接触垫，位于所述多个存储芯片的积层方向上的所述半导体衬底与所述第1接触垫之间的层级；
所述多个贯通电极包含：第1贯通电极，连接于所述第1接触垫；以及第2贯通电极，连接于所述第2接触垫。
11.根据权利要求10所述的半导体装置，其中所述第1存储芯片还包含设置在所述半导体衬底与所述存储单元阵列之间的电路；
所述第1存储芯片构成为经由所述第1贯通电极及所述第1接触垫而被供给外部电压至所述电路。
12.根据权利要求11所述的半导体装置，其中所述第1存储芯片构成为经由所述第2贯通电极及所述第2接触垫而被传送信号至所述电路。
13.根据权利要求12所述的半导体装置，其中所述第1存储芯片还包含：第3接触垫，设置在所述端子部；以及配线层，包含连接于所述存储单元阵列及所述第3接触垫的配线；
所述2接触垫位于所述第2贯通电极与所述第3接触垫之间，经由多个第1接触插塞而电连接于所述第3接触垫。
14.根据权利要求13所述的半导体装置，其中所述存储单元阵列包含：多个电极层，在所述积层方向上积层；半导体层，在所述积层方向上贯穿所述多个电极层；以及多个第2接触插塞，连接所述多个电极层与所述配线层中的配线；
所述多个第2接触插塞位于与所述多个第1接触插塞在所述积层方向上的层级相同的层级。
15.根据权利要求13所述的半导体装置，其中所述配线层包含将所述第3接触垫与所述电路连接的配线。
16.根据权利要求13所述的半导体装置，其中所述第3接触垫位于与所述积层方向上的所述配线层的层级相同的层级。
17.根据权利要求13所述的半导体装置，其中所述端子部还包含位于所述第2接触垫与所述第3接触垫之间的第4接触垫；
所述第2接触垫经由所述多个第1接触插塞而连接于所述第4接触垫；
所述第4接触垫经由多个第3接触插塞而连接于所述第3接触垫。
18.根据权利要求13所述的半导体装置，其中与所述积层方向交叉的第1方向上的所述多个第1接触插塞的宽度比所述第2贯通电极的所述第1方向的宽度窄。
19.根据权利要求10所述的半导体装置，其中与所述积层方向交叉的第1方向上的所述第1贯通电极的宽度比所述第1方向上的所述第2贯通电极的宽度宽。
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