TWI806423B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI806423B
TWI806423B TW111105221A TW111105221A TWI806423B TW I806423 B TWI806423 B TW I806423B TW 111105221 A TW111105221 A TW 111105221A TW 111105221 A TW111105221 A TW 111105221A TW I806423 B TWI806423 B TW I806423B
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Taiwan
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pad
insulating
conductive material
semiconductor device
semiconductor
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TW111105221A
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TW202247393A (zh
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渡辺慎也
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日商鎧俠股份有限公司
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Abstract

本實施方式之半導體裝置具備第1絕緣層。第1焊墊露出於第1絕緣層之表面。第2絕緣層接合於第1絕緣層。第2焊墊露出於第2絕緣層之表面，且接合於第1焊墊。於自相對於第1絕緣層之表面大致垂直方向之第1俯視時，於第1焊墊之內側，存在第1導電性材料、及蝕刻速率較第1導電性材料低之第1絕緣性材料。第1絕緣性材料於第1導電性材料之內側呈島嶼狀設置。

Description

半導體裝置
本實施方式係關於一種半導體裝置。
近年來，開發了將複數個半導體晶片彼此貼合而將焊墊電接合之技術。另一方面，於CMP(Chemical Mechanical Polishing，化學機械拋光)法等研磨方法中，有時由於被研磨之材質之差異，而產生碟狀變形(凹陷)。若接合面之焊墊因碟狀變形而凹陷，則於將複數個半導體晶片彼此貼合時，存在焊墊間之接觸電阻上升，或者產生焊墊間之開路不良之情況。
一實施方式提供一種可抑制所貼合之半導體晶片間之接觸電阻上升或者抑制開路不良之半導體裝置。
本實施方式之半導體裝置具備第1絕緣層。第1焊墊露出於第1絕緣層之表面。第2絕緣層接合於第1絕緣層。第2焊墊露出於第2絕緣層之表面，且接合於第1焊墊。於自相對於第1絕緣層之表面大致垂直方向之第1俯視時，於第1焊墊之內側，存在第1導電性材料、及蝕刻速率較第1導電性材料低之第1絕緣性材料。第1絕緣性材料於第1導電性材料之內側呈島嶼狀設置。
根據上述構成，可提供一種可抑制所貼合之半導體晶片間之接觸電阻上升或者抑制開路不良之半導體裝置。
以下，參照圖式對本發明之實施方式進行說明。本實施方式並不限定本發明。於以下之實施方式中，半導體晶片之上下方向有時與依據重力加速度之上下方向不同。圖式係模式性之圖或概念性之圖，各部分之比率等未必與實物相同。於說明書與圖式中，對與上文中針對已出現之圖式敍述過之內容相同之要素標註相同之符號並適當省略詳細之說明。
(第1實施方式)圖1係表示第1實施方式之半導體封裝1之構成例之剖視圖。本實施方式之半導體封裝1係半導體記憶體之封裝之例子。然而，本實施方式亦可應用於其他半導體裝置。
半導體封裝1具備配線基板10、金屬凸塊20、焊料球70、控制器晶片30、包含積層之複數個記憶體晶片之記憶體晶片積層體40、以貫通各記憶體晶片之方式設置之電極50、及密封樹脂60。
配線基板10具備絕緣體11、配線層12、及阻焊劑層13。絕緣體11例如使用玻璃環氧樹脂等絕緣材料。配線層12係設置於絕緣體11之表面及背面之導電體。配線層12例如使用銅等低電阻金屬材料。阻焊劑層13設置於配線層12之上。
金屬凸塊20設置於配線基板10之表面側，且電性地連接於配線層12之一部分。焊料球70設置於配線基板10之背面側，且電性地連接於配線層12之一部分。
控制器晶片30設置於配線基板10之表面上方。控制器晶片30以控制複數個記憶體晶片之方式設置。
記憶體晶片積層體40積層於控制器晶片30之上。複數個記憶體晶片例如為搭載NAND(Not And，反及)型記憶胞之半導體晶片。各記憶體晶片及控制器晶片30經由電極50而電性地連接。電極50傳遞電源電力、接地電壓、控制信號、或資料等。電極50例如使用鎢、鎳、銅、金、鋁、多晶矽等導電性材料。
密封樹脂60設置於配線基板10之表面上，且將控制器晶片30及記憶體晶片積層體40密封。
圖2係表示第1實施方式之半導體封裝1之一部分之構成例之剖視圖。於圖2中，表示所積層之2個記憶體晶片40＿1、40＿2之剖面。記憶體晶片40＿1與記憶體晶片40＿2於接合面B＿chip中接合。
記憶體晶片40＿1包括包含記憶胞陣列MCA1之陣列晶片CH＿A1、及包含CMOS(Complementary Metal Oxide Semiconductor，互補金屬氧化物半導體)電路CMOS1之電路晶片CH＿C1。記憶體晶片40＿2包括包含記憶胞陣列MCA2之陣列晶片CH＿A2、及包含CMOS電路CMOS2之電路晶片CH＿C2。 於記憶體晶片40＿1中，亦可將記憶胞陣列MCA1或CMOS1之任一者設為第1半導體電路，將另一者設為第2半導體電路。 於記憶體晶片40＿2中，亦可將記憶胞陣列MCA2或CMOS2之任一者設為第1半導體電路，將另一者設為第2半導體電路。 亦可隔著接合面B＿chip，將記憶體晶片40＿1包含之記憶胞陣列MCA1及CMOS1設為第1半導體電路，將記憶體晶片40＿2包含之記憶胞陣列MCA2及CMOS2設為第2半導體電路。
(記憶體晶片40＿1)陣列晶片CH＿A1包含由層間絕緣膜ILD1＿1被覆之記憶胞陣列MCA1。記憶胞陣列MCA1具有於Z方向上積層且相互絕緣之複數個字元線WL1、及以於積層方向(Z方向)上貫通所積層之複數個字元線WL1之方式延伸之複數個柱狀體CL1。對應於字元線WL1與柱狀體CL1之交叉點而設置有記憶胞MC1。複數個柱狀體CL1之一端共通連接於源極線SL1。複數個柱狀體CL1之另一端連接於在Y方向上延伸之位元線BL1之任一個。
記憶胞陣列MCA1設置於陣列區域R＿Arr。字元線WL1於X方向上延伸至階台區域R＿Trr，且於階台區域R＿Trr中呈階梯狀形成。對呈階梯狀形成之各字元線WL1之階梯面，連接有接觸插塞CC1。接觸插塞CC1經由配線層W1＿1電性地連接於分別設置於陣列區域R＿Arr之焊墊P1＿1a與字元線WL1之間。焊墊P1＿1a係自層間絕緣膜ILD1＿1之表面露出，且設置於陣列晶片CH＿A1之接合面B＿mc1之電極焊墊。配線層W1＿1經由接觸插塞CC1將記憶胞陣列MCA1與焊墊P1＿1a之間電性地連接。
於陣列區域R＿Arr及階台區域R＿Trr之周圍，設置有周邊區域R＿Pri。周邊區域R＿Pri亦可設置於不僅包含記憶體晶片之周邊部而且亦包含記憶體晶片之中央部在內之各種位置。於周邊區域R＿Pri，接觸插塞Cpri1以於Z方向上貫通陣列晶片CH＿A1之層間絕緣膜ILD1＿1之方式設置。接觸插塞Cpri1之一端經由配線層W1＿1電性地連接於設置於周邊區域R＿Pri之接合面B＿mc1之焊墊P1＿1a。接觸插塞Cpri1之另一端電性地連接於設置於陣列晶片CH＿A1之與接合面B＿mc1相反一面之焊墊P1＿1b。
電路晶片CH＿C1設置於陣列晶片CH＿A1之下方(-Z方向)，且包含由層間絕緣膜ILD1＿2被覆之CMOS電路CMOS1。CMOS電路CMOS1設置於半導體層SUB1上，係包含P型MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金屬氧化物半導體場效電晶體)及N型MOSFET之電路。CMOS電路CMOS1亦可包含其他半導體元件(例如，電阻元件、電容元件)。CMOS電路CMOS1由層間絕緣膜ILD1＿2被覆。於層間絕緣膜ILD1＿2，設置有多層配線層W1＿2。多層配線層W1將CMOS電路CMOS1與焊墊P1＿2a之間電性地連接。焊墊P1＿2a係自層間絕緣膜ILD1＿2之表面露出，且設置於電路晶片CH＿C1之接合面B＿mc1之電極焊墊。焊墊P1＿2a亦可設置於陣列區域R＿Arr、階台區域R＿Trr及周邊區域R＿Pri中之任一個區域。
於電路晶片CH＿C1之周邊區域R＿Pri，設置有貫通電極TSV1。貫通電極TSV1係電極50之一部分。貫通電極TSV1於Z方向上貫通半導體層SUB1，且電性地連接於焊墊P1＿2a與焊墊P1＿2b之間。焊墊P1＿2b係設置於與接合面B＿mc1相反側之貫通電極TSV1之端部之電極焊墊。
陣列晶片CH＿A1與電路晶片CH＿C1於接合面B＿mc1被貼合。於接合面B＿mc1中，層間絕緣膜ILD1＿1、ILD1＿2被接合，焊墊P1＿1a與P1＿2a被接合。藉此，電路晶片CH＿C1之CMOS電路CMOS1經由多層配線層W1＿2、焊墊P1＿2a、P1＿1a及接觸插塞CC1電性地連接於記憶胞陣列MCA1。其結果，CMOS電路CMOS1可控制記憶胞陣列MCA1。又，貫通電極TSV1經由焊墊P1＿2a、P1＿1a及配線層W1＿1電性地連接於接觸插塞Cpri1。貫通電極TSV1例如係為了能夠將電源電力或接地電位共通地傳遞至晶片間而設置。
(記憶體晶片40＿2)陣列晶片CH＿A2包含由層間絕緣膜ILD2＿1被覆之記憶胞陣列MCA2。記憶胞陣列MCA2具有於Z方向上積層且相互絕緣之複數個字元線WL2、及以於積層方向(Z方向)上貫通所積層之複數個字元線WL2之方式延伸之複數個柱狀體CL2。對應於字元線WL2與柱狀體CL2之交叉點而設置有記憶胞MC2。複數個柱狀體CL2之一端共通連接於源極線SL2。複數個柱狀體CL2之另一端連接於在Y方向上延伸之位元線BL2之任一個。
記憶胞陣列MCA2設置於陣列區域R＿Arr。字元線WL2於X方向上延伸至階台區域R＿Trr，且於階台區域R＿Trr中呈階梯狀形成。針對呈階梯狀形成之各字元線WL2之階梯面，連接有接觸插塞CC2。接觸插塞CC2經由配線層W2＿1電性地連接於分別設置於陣列區域R＿Arr之焊墊P2＿1a與字元線WL2之間。焊墊P2＿1a係露出於層間絕緣膜ILD2＿1之表面且設置於陣列晶片CH＿A2之接合面B＿mc2之電極焊墊。配線層W2＿1經由接觸插塞CC2將記憶胞陣列MCA2與焊墊P2＿1a之間電性地連接。
於陣列區域R＿Arr及階台區域R＿Trr之周圍，設置有周邊區域R＿Pri。於周邊區域R＿Pri，接觸插塞Cpri2以於Z方向上貫通陣列晶片CH＿A2之層間絕緣膜ILD2＿1之方式設置。接觸插塞Cpri2之一端經由配線層W2＿1電性地連接於設置於周邊區域R＿Pri之接合面B＿mc2之焊墊P2＿1a。接觸插塞Cpri2之另一端電性地連接於設置於陣列晶片CH＿A2之與接合面B＿mc2相反一面之焊墊P2＿1b。
電路晶片CH＿C2設置於陣列晶片CH＿A2之下方(-Z方向)，且包含由層間絕緣膜ILD2＿2被覆之CMOS電路CMOS2。CMOS電路CMOS2設置於半導體層SUB2上，係包含P型MOSFET及N型MOSFET之電路。CMOS電路CMOS2亦可包含其他半導體元件(例如，電阻元件、電容元件)。CMOS電路CMOS2由層間絕緣膜ILD2＿2被覆。於層間絕緣膜ILD2＿2，設置有多層配線層W2＿2。多層配線層W2＿2將CMOS電路CMOS2與焊墊P2＿2a之間電性地連接。焊墊P2＿2a係露出於層間絕緣膜ILD2＿2之表面且設置於電路晶片CH＿C2之接合面B＿mc2之電極焊墊。焊墊P2＿2a亦可設置於陣列區域R＿Arr、階台區域R＿Trr及周邊區域R＿Pri中之任一個區域。
於電路晶片CH＿C2之周邊區域R＿Pri，設置有貫通電極TSV2。貫通電極TSV2於Z方向上貫通半導體層SUB2，且電性地連接於焊墊P2＿2a與焊墊P2＿2b之間。焊墊P2＿2b係設置於與接合面B＿mc2相反側之貫通電極TSV2之端部之電極焊墊。
陣列晶片CH＿A2與電路晶片CH＿C2於接合面B＿mc2被貼合。於接合面B＿mc2中，層間絕緣膜ILD2＿1、ILD2＿2被接合，焊墊P2＿1a與P2＿2a被接合。藉此，電路晶片CH＿C2之CMOS電路CMOS2經由多層配線層W2＿2、焊墊P2＿2a、P2＿1a及接觸插塞CC2電性地連接於記憶胞陣列MCA2。其結果，CMOS電路CMOS2可控制記憶胞陣列MCA2。又，貫通電極TSV2經由焊墊P2＿2a、P2＿1a及配線層W2＿1電性地連接於接觸插塞Cpri2。貫通電極TSV2例如亦係為了能夠將電源電力或接地電位共通地傳遞至晶片間而設置。
(記憶體晶片40＿1、40＿2間之接合)記憶體晶片40＿1與記憶體晶片40＿2於接合面B＿chip被接合。於接合面B＿chip中，焊墊P1＿1b與焊墊P2＿1b被接合。記憶體晶片40＿1與40＿2經由相互接合之焊墊P1＿1b、P2＿1b電性地連接。藉此，貫通電極TSV1、TSV2及接觸插塞Cpri1、Cpri2被電性地連接，例如，可將電源電力或接地電位於所積層之複數個記憶體晶片40＿1、40＿2間共通地傳遞。
(焊墊P1＿1a等之構成)圖3A係表示焊墊P1＿1a之構成例之俯視圖。於圖3A中，於自相對於陣列晶片CH＿A1之層間絕緣膜ILD1＿1之表面(接合面B＿mc1)大致垂直方向之第1俯視(自Z方向觀察之俯視)時，焊墊P1＿1a自層間絕緣膜ILD1＿1之表面露出。於上述俯視時，焊墊P1＿1a之周邊被層間絕緣膜ILD1＿1包圍，例如，該焊墊P1＿1a具有大致八邊形之形狀。焊墊P1＿1a之平面形狀亦可為八邊形以外之多邊形、大致圓形、大致橢圓形。
於焊墊P1＿1a之內側，設置有障壁金屬膜101＿1a、導電性材料102＿1a、及絕緣性材料103＿1a。於焊墊P1＿1a之外側，設置有層間絕緣膜ILD1＿1。
障壁金屬膜101＿1a設置於焊墊P1＿1a之外緣，且設置於層間絕緣膜ILD1＿1或絕緣性材料103＿1a與導電性材料102＿1a之間。障壁金屬膜101＿1a例如使用鈦膜及氮化鈦膜之積層膜等導電性材料。
導電性材料102＿1a設置於由障壁金屬膜101＿1a包圍之焊墊P1＿1a之內側。導電性材料102＿1a例如使用銅、鎢等導電性材料。絕緣性材料103＿1a於導電性材料102＿1a之內側呈島嶼狀設置，其周圍由導電性材料102＿1a包圍。
於上述俯視時，複數個絕緣性材料103＿1a於導電性材料102＿1a之表面，分別於Y方向上延伸，且具有細長形狀。又，於上述俯視時，複數個絕緣性材料103＿1a於導電性材料102＿1a之表面，於相對於Y方向正交之X方向上呈條紋狀或線與間隙狀排列。換言之，複數個絕緣性材料103＿1a設置為大致平行地延伸之狹縫狀或短條狀。複數個絕緣性材料103＿1a於上述俯視時，設置於焊墊P1＿1a之內側，且未到達障壁金屬膜101＿1a及層間絕緣膜ILD1＿1。再者，絕緣性材料103＿1a亦可於焊墊P1＿1a之下方與層間絕緣膜ILD1＿1相連。絕緣性材料103＿1a可使用與層間絕緣膜ILD1＿1相同之材料(例如，氧化矽膜)。
又，於上述俯視時，焊墊P1＿1a之絕緣性材料103＿1a之面積小於導電性材料102＿1a之面積。藉由使導電性材料102＿1a之面積相對較大，而與電路晶片CH＿C1之焊墊P1＿2a之導電性材料102＿2a之接觸面積變大，可將焊墊P1＿1a與焊墊P1＿2a之間之接觸電阻抑制得較低。
此處，絕緣性材料103＿1a由CMP步驟中之蝕刻速率較導電性材料102＿1a之材料(例如，銅或鎢等金屬材料)低之材料(例如，可使用氧化矽膜等氧化膜、或氮化矽膜等氮化膜、碳化矽膜等碳化膜、或該等之複合材料等)形成。例如，絕緣性材料103＿1a亦可由較導電性材料102＿1a之材料更難研磨之物理上較硬之材料形成。或者，絕緣性材料103＿1a亦可由較導電性材料102＿1a之材料更難利用研磨劑(漿料)進行化學蝕刻之材料形成。因此，於CMP步驟中，絕緣性材料103＿1a於導電性材料102＿1a之內側成為支柱，可緩和導電性材料102＿1a之中央部之膜厚變薄而出現凹陷(碟狀變形)。
焊墊P1＿1a之X方向或Y方向之寬度Wp1＿1a例如約為1 μm。絕緣性材料103＿1a之寬度W103＿1a例如約為幾十nm。
由虛線表示之配線層W1＿1設置於焊墊P1＿1a之下。配線層W1＿1經由通孔觸點V1＿1電性地連接於焊墊P1＿1a。於本實施方式中，9個通孔觸點V1＿1設置於焊墊P1＿1a與配線層W1＿1之間。然而，通孔觸點V1＿1之個數並不限定為9個，可為任意。又，圖3C係表示配線層W1＿1之構成之一例之俯視圖。配線層W1＿1於上述俯視時於焊墊P1＿1a之下方於大致方形之框內形成為十字形狀。於配線層W1＿1上，設置有9個通孔觸點V1＿1。又，配線層W1＿1亦可並非十字形狀，而為立體形狀。
圖3B係表示焊墊P1＿1a之構成例之剖視圖。圖3B表示沿著圖3A之B-B線之剖面。焊墊P1＿1a填埋於層間絕緣膜ILD1＿1內，且露出於層間絕緣膜ILD1＿1之表面。導電性材料102＿1a經由通孔觸點V1＿1電性地連接於設置於上述導電性材料102＿1a之下之配線層W1＿1。絕緣性材料103＿1a可係層間絕緣膜ILD1＿1之一部分，亦可係相同材料。再者，導電性材料102＿1a之高度例如約為1 μm。
如此，根據本實施方式，焊墊P1＿1a包含絕緣性材料103＿1a，上述絕緣性材料103＿1a於自相對於接合面B＿mc1大致垂直之方向俯視時，於導電性材料102＿1a之內側呈島嶼狀設置。絕緣性材料103＿1a由蝕刻速率較導電性材料102＿1a低之材料形成。因此，於對層間絕緣膜ILD1＿1及導電性材料102＿1a進行研磨之CMP步驟中，絕緣性材料103＿1a於導電性材料102＿1a內成為支柱，可緩和導電性材料102＿1a之碟狀變形。
於未設置絕緣性材料103＿1a之情形時，導電性材料102＿1a以相對較寬之面積被研磨。於該情形時，於導電性材料102＿1a之內側，呈大幅度碟狀變形地凹陷。
相對於此，根據本實施方式，絕緣性材料103＿1a將導電性材料102＿1a分為相對較小之面積，於導電性材料102＿1a內成為支柱。藉此，抑制導電性材料102＿1a之內側產生碟狀變形。
絕緣性材料103＿1a較佳為於導電性材料102＿1a內大致均等地配置。藉此，可抑制局部大幅度地產生導電性材料102＿1a之碟狀變形。
圖3A及圖3B對焊墊P1＿1a進行了說明，但關於焊墊P1＿2a、P2＿1a、P2＿2a、P1＿2b、P2＿1b亦可同樣地構成。藉此，關於焊墊P1＿1a以外之其他焊墊P1＿2a、P2＿1a、P2＿2a、P1＿2b、P2＿1b，同樣地，於CMP步驟中抑制碟狀變形。再者，焊墊P1＿2a、P2＿1a、P2＿2a、P1＿2b、P2＿1b之構成只要參照圖3A及圖3B便可容易地理解，故而省略其詳細之說明。
圖4係表示接合面B＿mc1之部分之構成例之剖視圖。陣列晶片CH＿A1側之焊墊P1＿1a與電路晶片CH＿C1側之焊墊P1＿2a於接合面B＿mc1被接合。
焊墊P1＿1a及焊墊P1＿2a均具有圖3A及圖3B所示之構成。因此，與圖3A所示之焊墊P1＿1a同樣地，於自相對於層間絕緣膜ILD1＿2之表面大致垂直之方向俯視時，於焊墊P1＿2a之內側，設置有障壁金屬膜101＿2a、導電性材料102＿2a、及絕緣性材料103＿2a。於焊墊P1＿2a之外側，設置有層間絕緣膜ILD1＿2。
再者，於以下之焊墊P1＿2a之說明中，圖3A及圖3B之焊墊P1＿1a、層間絕緣膜ILD1＿1、障壁金屬膜101＿1a、導電性材料102＿1a、及絕緣性材料103＿1a分別被改稱為焊墊P1＿2a、層間絕緣膜ILD1＿2、障壁金屬膜101＿2a、導電性材料102＿2a、及絕緣性材料103＿2a。
障壁金屬膜101＿2a設置於焊墊P1＿2a之外緣，且設置於層間絕緣膜ILD1＿2或絕緣性材料103＿2a與導電性材料102＿2a之間。障壁金屬膜101＿2a例如使用鈦膜及氮化鈦膜之積層膜等導電性材料。
導電性材料102＿2a設置於由障壁金屬膜101＿2a包圍之焊墊P1＿2a之內側。導電性材料102＿2a例如使用銅、鎢等導電性材料。絕緣性材料103＿2a於導電性材料102＿2a之內側呈島嶼狀設置，其周圍由導電性材料102＿2a包圍。
於上述俯視時，複數個絕緣性材料103＿2a於導電性材料102＿2a之表面，分別於Y方向上延伸，且具有細長形狀。又，於上述俯視時，複數個絕緣性材料103＿2a於導電性材料102＿2a之表面，於相對於Y方向正交之X方向上呈條紋狀或線與間隙狀排列。換言之，複數個絕緣性材料103＿2a設置為大致平行地延伸之狹縫狀或短條狀。複數個絕緣性材料103＿2a於上述俯視時，設置於焊墊P1＿2a之內側，且未到達障壁金屬膜101＿2a及層間絕緣膜ILD1＿2。再者，絕緣性材料103＿2a可使用與層間絕緣膜ILD1＿2相同之材料(例如，氧化矽膜)。
此處，絕緣性材料103＿2a由蝕刻速率較導電性材料102＿2a之材料(例如，銅或鎢等金屬材料)低之材料(例如，氧化矽膜)形成。例如，絕緣性材料103＿2a亦可由較導電性材料102＿2a之材料更難研磨之物理上較硬之材料形成。或者，絕緣性材料103＿2a亦可由較導電性材料102＿2a之材料更難利用研磨劑(漿料)進行化學蝕刻之材料形成。因此，於CMP步驟中，絕緣性材料103＿2a於導電性材料102＿2a之內側成為支柱，可緩和導電性材料102＿2a之碟狀變形。
焊墊P1＿2a之X方向或Y方向之寬度Wp1＿2a例如約為1 μm。絕緣性材料103＿2a之寬度W103＿2a例如約為幾十nm。
焊墊P1＿2a填埋於層間絕緣膜ILD1＿2內，且露出於層間絕緣膜ILD1＿2之表面。導電性材料102＿2a電性地連接於設置於導電性材料102＿2a之下之配線層W1＿2。絕緣性材料103＿2a可係層間絕緣膜ILD1＿2之一部分，亦可係相同材料。再者，導電性材料102＿2a之高度例如約為1 μm。
如此，焊墊P1＿1a、P1＿2a具有大致相同之構成。焊墊P1＿1a與焊墊P1＿2a於焊墊P1＿1a與焊墊P1＿2a之接合面B＿mc1，以絕緣性材料103＿1a之延伸方向與絕緣性材料103＿2a之延伸方向成為大致相同之方向(例如，Y方向)之方式被接合。藉此，於將陣列晶片CH＿A1與電路晶片CH＿C1貼合時，如圖4所示，導電性材料102＿1a與導電性材料102＿2a於接合面B＿mc1以大致對向地一致之方式被接合。此時，焊墊P1＿1a、P1＿2a幾乎不會產生碟狀變形，導電性材料102＿1a、102＿2a於接合面B＿mc1幾乎不會凹陷。即，導電性材料102＿1a、102＿2a於接合面B＿mc1中設置於大致同一面。因此，雖然於導電性材料102＿1a及導電性材料102＿2a各自之內側設置有絕緣性材料103＿1a、103＿2a，但是導電性材料102＿1a及導電性材料102＿2a於接合面B＿mc1能夠以充分低之電阻接合。
若不設置絕緣性材料103＿1a、103＿2a，則雖然接合面B＿mc1中之導電性材料102＿1a、102＿2a之面積相應地變寬，但是導電性材料102＿1a、102＿2a容易因CMP步驟中之碟狀變形而產生接合不良。因此，擔心導電性材料102＿1a與導電性材料102＿2a之間之接觸電阻變高。
相對於此，根據本實施方式，由於設置有絕緣性材料103＿1a、103＿2a，故而接合面B＿mc1中之導電性材料102＿1a、102＿2a之面積相應地變小。然而，導電性材料102＿1a、102＿2a之碟狀變形得到抑制，導電性材料102＿1a、102＿2a於接合面B＿mc1幾乎不會凹陷。因此，可使導電性材料102＿1a與導電性材料102＿2a之間之接觸電阻較低且穩定。
接下來，對第1實施方式之焊墊P1＿1a、P1＿2a之製造方法進行說明。
圖5～圖11係表示第1實施方式之焊墊P1＿1a之製造方法之一例之剖視圖。再者，焊墊P1＿2a之製造方法與焊墊P1＿1a之製造方法相同，故而省略其詳細之說明。
首先，於陣列晶片CH＿A1之基板(例如，矽基板)形成記憶胞陣列MCA1及層間絕緣膜ILD1＿1等。接下來，於陣列晶片CH＿A1之層間絕緣膜ILD1＿1形成配線層W1＿1。接下來，於配線層W1＿1及層間絕緣膜ILD1＿1上進而堆積絕緣膜。絕緣膜可係與層間絕緣膜ILD1＿1相同之材料(例如，氧化矽膜)。因此，亦將配線層W1＿1上之絕緣膜稱為層間絕緣膜ILD1＿1。藉此，獲得圖5所示之構造。
接下來，使用微影技術及蝕刻技術，對配線層W1＿1上之層間絕緣膜ILD1＿1進行加工。藉此，如圖6所示，將配線層W1＿1上之層間絕緣膜ILD1＿1加工成通孔觸點V1＿1之圖案。
接下來，如圖7所示，於層間絕緣膜ILD1＿1及配線層W1＿1上堆積障壁金屬膜201＿1a及導電性材料202＿1a。障壁金屬膜201＿1a例如使用鈦膜與氮化鈦膜之積層膜等。導電性材料202＿1a例如使用銅、鎢等導電性材料。
接下來，使用CMP法，對障壁金屬膜201＿1a及導電性材料202＿1a進行研磨，直至層間絕緣膜ILD1＿1露出為止。藉此，如圖8所示，形成包括障壁金屬膜201＿1a及導電性材料202＿1a之通孔觸點V1＿1。
接下來，於通孔觸點V1＿1上進而堆積絕緣膜。絕緣膜可係與層間絕緣膜ILD1＿1相同之材料(例如，氧化矽膜)。因此，亦將通孔觸點V＿1上之絕緣膜稱為層間絕緣膜ILD1＿1。接下來，使用微影技術及蝕刻技術，如圖9所示，將通孔觸點V1＿1上之層間絕緣膜IL＿1加工成焊墊P1＿1a之圖案。此處，亦可於焊墊P1＿1a形成第1凹部Con＿1，於其周圍形成第1絕緣層，於第1凹部之內側形成第1絕緣性材料。
接下來，如圖10所示，於層間絕緣膜ILD1＿1及通孔觸點V1＿1上堆積障壁金屬膜101＿1a及導電性材料102＿1a。障壁金屬膜101＿1a例如使用鈦膜與氮化鈦膜之積層膜等。導電性材料102＿1a例如使用銅、鎢等導電性材料。
接下來，使用CMP法，對障壁金屬膜101＿1a及導電性材料102＿1a進行研磨，直至層間絕緣膜ILD1＿1露出為止。藉此，如圖11所示，形成包含障壁金屬膜101＿1a及導電性材料102＿1a之焊墊P1＿1a。再者，於CMP步驟中露出之層間絕緣膜ILD1＿1成為上述絕緣性材料103＿1a。
此處，如圖3A所示，絕緣性材料103＿1a於導電性材料102＿1a之內側設置成島嶼狀(例如，條紋狀或線與間隙狀)。於障壁金屬膜101＿1a及導電性材料102＿1a之CMP步驟中，絕緣性材料103＿1a於導電性材料102＿1a內作為支柱發揮功能。藉此，焊墊P1＿1a中導電性材料102＿1a之碟狀變形(凹陷)得到抑制。
以上，對陣列晶片CH＿A1之焊墊P1＿1a之製造方法進行了說明。電路晶片CH＿C1之焊墊P1＿2a雖然連接於CMOS電路CMOS1，但是與焊墊P1＿1a同樣地形成。因此，焊墊P1＿2a中導電性材料102＿2a之碟狀變形(凹陷)亦得到抑制。
陣列晶片CH＿A1之焊墊P1＿1a及電路晶片CH＿C1之焊墊P1＿2a之碟狀變形得到抑制。因此，於將陣列晶片CH＿A1與電路晶片CH＿C1貼合時，如圖4所示，焊墊P1＿1a與焊墊P1＿2a幾乎無間隙地充分接合。其結果，可抑制陣列晶片CH＿A1與電路晶片CH＿C1之間之焊墊間之接觸電阻上升，抑制開路不良。
以上，對陣列晶片CH＿A1與電路晶片CH＿C1之間之接合進行了說明，但本實施方式亦可應用於記憶體晶片40＿1、40＿2間之接合。
(記憶體晶片40＿1、40＿2間之接合)如圖2所示，記憶體晶片40＿1與記憶體晶片40＿2於接合面B＿chip被接合。記憶體晶片40＿1、40＿2具有相互相同之構成。
於接合面B＿chip中，記憶體晶片40＿1之焊墊P1＿2b與記憶體晶片40＿2之焊墊P2＿1b電性地連接。焊墊P1＿2b經由再配線層(未圖示)電性地連接於設置於記憶體晶片40＿1之電路晶片CH＿C1之貫通電極TSV1。焊墊P2＿1b電性地連接於記憶體晶片40＿2之陣列晶片CH＿A2之接觸插塞Cpri2。
此處，焊墊P1＿2b、P2＿1b可分別具有與圖3A及圖3B所示之焊墊P1＿1a相同之構成。藉此，焊墊P1＿2b與焊墊P1＿1a與圖4所示之焊墊P1＿1a與焊墊P1＿2a同樣地被接合。因此，於記憶體晶片40＿1、40＿2間之接合中亦可獲得本實施方式之效果。
圖12～圖17係表示電路晶片CH＿C1之貫通電極TSV1之區域之形成步驟之一例之剖視圖。
首先，使用半導體製造製程，於基板(例如，矽基板)SUB1上形成CMOS電路CMOS1。如圖12所示，CMOS電路CMOS1經由焊墊P1＿2b及配線W1＿2(或者貫通電極之承接電極)電性地連接於貫通電極TSV1。再者，於圖13以後，省略了CMOS電路CMOS1、焊墊P1＿2b及配線W1＿2之圖示。
接下來，使用微影技術及蝕刻技術於貫通電極TSV1之形成區域形成孔。於該孔之內壁成膜間隔絕緣膜SP1。接下來，使用鍍覆法等，於間隔絕緣膜(例如，氧化矽膜)SP1之內側填埋貫通電極TSV1之材料(例如，銅、鎢)。接下來，於基板SUB1上堆積層間絕緣膜ILD1＿2。藉此，獲得圖12所示之構造。
如此，貫通電極TSV1於形成CMOS電路之後形成。因此，由於在CMOS電路之高溫熱處理之後形成貫通電極TSV1，故而貫通電極TSV1之材料(例如，銅、鎢)可使用鍍覆法成膜。貫通電極TSV1之CMOS電路側之端部既可與CMOS電路電性地連接，亦可與外部電極電性地連接。
接下來，將電路晶片CH＿C1與陣列晶片CH＿A1貼合。此時，焊墊P1＿1a與焊墊P1＿2a被接合(參照圖2)。
接下來，如圖13所示，使基板SUB1之上下反轉。接下來，如圖14所示，對基板SUB1之背面側進行蝕刻，而使貫通電極TSV1及間隔絕緣膜SP1之端部露出。
接下來，如圖15所示，將絕緣膜91、92堆積於基板SUB1及貫通電極TSV1上。絕緣膜91例如為氮化矽膜，絕緣膜92例如為氧化矽膜。
接下來，如圖16所示，使用CMP法對絕緣膜91、92進行研磨，直至使貫通電極TSV1露出為止。藉此，貫通電極TSV1形成於基板SUB1內。貫通電極TSV1於利用間隔絕緣膜SP1與基板SUB1電性地絕緣之狀態下，貫通基板SUB1。
接下來，如圖17所示，形成再配線層RW1。接下來，於再配線層RW1上形成焊墊P1＿2b。焊墊P1＿2b之構成及形成方法與參照圖3A～圖11所說明之內容相同。
然後，將記憶體晶片40＿1、40＿2貼合。藉此，如圖2所示，焊墊P1＿2b與焊墊P2＿1b貼合。
再者，當於陣列晶片CH＿A1設置有貫通電極之情形時，陣列晶片CH＿A1之貫通電極亦可與圖12～圖17所示之方法同樣地形成。
(變化例1)圖18A～圖18D係表示焊墊P1＿1a之製造方法之另一例之剖視圖。再者，焊墊P1＿2a之製造方法與焊墊P1＿1a之製造方法相同，故而省略其詳細之說明。
於形成圖5所示之構造之後，使用微影技術及蝕刻技術，對配線層W1＿1上之層間絕緣膜ILD1＿1進行加工。藉此，如圖18A所示，將配線層W1＿1上之層間絕緣膜ILD1＿1加工成通孔觸點V1＿1之圖案。
接下來，再次使用微影技術及蝕刻技術，對層間絕緣膜ILD1＿1進行加工，如圖18B所示，將層間絕緣膜ILD1＿1之上部加工成焊墊P1＿1a之圖案。藉此，焊墊P1＿1a之圖案形成於層間絕緣膜ILD1＿1之上部，通孔觸點V1＿1之圖案以接在焊墊P1＿1a之圖案之下之方式形成。
接下來，如圖18C所示，於層間絕緣膜ILD1＿1及配線層W1＿1上堆積障壁金屬膜101＿1a及導電性材料102＿1a。
接下來，使用CMP法，對障壁金屬膜101＿1a及導電性材料102＿1a進行研磨，直至層間絕緣膜ILD1＿1露出為止。藉此，如圖18D所示，同時形成包括障壁金屬膜101＿1a及導電性材料102＿1a之通孔觸點V1＿1及焊墊P1＿1a。於該CMP步驟中，絕緣性材料103＿1a於導電性材料102＿1a之內側成為支柱，可緩和導電性材料102＿1a之碟狀變形。
變化例1中，同時形成通孔觸點V1＿1及焊墊P1＿1a。因此，變化例1可利用較第1實施方式少之步驟形成焊墊P1＿1a。變化例1之其他製造步驟可與第1實施方式相同。因此，本變化例1可獲得與第1實施方式相同之效果。
(變化例2)圖19A～圖19G係表示焊墊P1＿1a之製造方法之又一例之剖視圖。再者，焊墊P1＿2a之製造方法與焊墊P1＿1a之製造方法相同，故而省略其詳細之說明。
於形成圖5所示之構造之後，使用微影技術及蝕刻技術，將配線層W1＿1上之層間絕緣膜ILD1＿1中焊墊P1＿1a之整個形成區域之層間絕緣膜ILD1＿1去除。藉此，獲得圖19A所示之構造。
接下來，如圖19B所示，於層間絕緣膜ILD1＿1及配線層W1＿1上堆積障壁金屬膜101＿1a及導電性材料102＿1a。
接下來，使用CMP法，對障壁金屬膜101＿1a及導電性材料102＿1a進行研磨，直至層間絕緣膜ILD1＿1露出為止。藉此，如圖19C所示，障壁金屬膜101＿1a及導電性材料102＿1a形成於焊墊P1＿1a之整個形成區域。
接下來，使用微影技術及蝕刻技術，對導電性材料102＿1a之上部進行加工，將處於絕緣性材料103＿1a之形成區域之導電性材料102＿1a去除。藉此，獲得圖19D所示之構造。
接下來，如圖19E所示，於層間絕緣膜ILD1＿1及導電性材料102＿1a上堆積障壁金屬膜101＿3。
接下來，如圖19F所示，將絕緣性材料103＿1a堆積於障壁金屬膜101＿3上。
接下來，使用CMP法，對絕緣性材料103＿1a進行研磨，直至層間絕緣膜ILD1＿1露出為止。藉此，如圖19G所示，形成焊墊P1＿1a。於該CMP步驟中，即便導電性材料102＿1a露出，絕緣性材料103＿1a於導電性材料102＿1a之內側亦會成為支柱，從而可緩和導電性材料102＿1a之碟狀變形。
於變化例2中，通孔觸點V1＿1設置於焊墊P1＿1a之整個形成區域。於該情形時，焊墊P1＿1a經由通孔觸點V1＿1連接於配線層W1＿1。
變化例2中，同樣地，同時形成通孔觸點V1＿1及焊墊P1＿1a。因此，變化例2可利用較第1實施方式少之步驟形成焊墊P1＿1a。變化例2之其他形成步驟可與第1實施方式相同。因此，本變化例2可獲得與第1實施方式相同之效果。再者，使用由變化例2形成之焊墊P1＿1a之實施方式將參照圖25於下文敍述。
(變化例3)圖20A～圖20F係表示電路晶片CH＿C1之貫通電極TSV1之區域之形成步驟之另一例之剖視圖。於該變化例中，於形成CMOS電路並使基板SUB1反轉之後，形成貫通電極TSV1。
首先，將未圖示之CMOS電路形成於基板SUB1上，於其上堆積層間絕緣膜ILD1＿2。藉此，獲得圖20A所示之構造。
接下來，如圖20B所示，使用微影技術及蝕刻技術於貫通電極TSV1之形成區域形成孔。
接下來，如圖20C所示，於該孔之內壁成膜間隔絕緣膜SP1，並進行回蝕，藉此將處於孔底部之間隔絕緣膜SP1去除。
接下來，如圖20D所示，使用鍍覆法等，於間隔絕緣膜SP1之內側填埋貫通電極TSV1之材料。
如此，貫通電極TSV1於形成CMOS電路之後形成。因此，由於在CMOS電路之高溫熱處理之後形成貫通電極TSV1，故而貫通電極TSV1之材料(例如，銅、鎢)可使用鍍覆法成膜。
接下來，使用CMP法，對貫通電極TSV1之材料進行研磨，直至間隔絕緣膜SP1之表面露出為止。藉此，如圖20E所示，貫通電極TSV1形成於基板SUB1內。貫通電極TSV1於利用間隔絕緣膜SP1與基板SUB1電性地絕緣之狀態下，貫通基板SUB1。
接下來，如圖20F所示，形成再配線層RW1。接下來，於再配線層RW1上形成焊墊P1＿2b。焊墊P1＿2b之構成及形成方法如參照圖3A～圖11所說明。
然後，將記憶體晶片40＿1、40＿2貼合。藉此，如圖2所示，焊墊P1＿2b與焊墊P2＿1b被貼合。
再者，當於陣列晶片CH＿A1設置有貫通電極之情形時，陣列晶片CH＿A1之貫通電極亦可與本變化例同樣地形成。
(第2實施方式)圖21係表示第2實施方式之焊墊P1＿2a之構成例之俯視圖。如第1實施方式般，於焊墊P1＿1a與焊墊P1＿2a為相同構成之情形時，若於圖4之X方向上使焊墊P1＿1a與焊墊P1＿2a相對偏移，則擔心導電性材料102＿1a與絕緣性材料103＿2a對向，導電性材料102＿2a與絕緣性材料103＿1a對向。於該情形時，擔心導電性材料102＿1a與導電性材料102＿12a之接觸面積變得極小，焊墊P1＿1a與焊墊P1＿2a之接觸電阻變高，且變得不穩定。
相對於此，於第2實施方式中，於自Z方向觀察之俯視時，焊墊P1＿2a之絕緣性材料103＿2a於相對於X及Y方向傾斜之方向上延伸。焊墊P1＿1a之構成可與第1實施方式之焊墊P1＿1a之構成相同。
圖22係表示第2實施方式之接合面B＿mc1之區域之構成例之剖視圖。於第2實施方式中，於將陣列晶片CH＿A1與電路晶片CH＿C1貼合時，焊墊P1＿1a與焊墊P1＿2a於接合面B＿mc1中，以絕緣性材料103＿1a之延伸方向(例如，Y方向)與絕緣性材料103＿2a之延伸方向(相對於X及Y方向傾斜之方向)交叉之方式接合。再者，沿著圖21之B-B線之剖面表示為圖22之焊墊P1＿2a。
自與基板垂直之方向觀察，彼此分離之複數個絕緣性材料103＿1a與導電性材料102＿2a一部分重疊，分離之複數個絕緣性材料103＿2a與導電性材料102＿1a一部分重疊。 由於絕緣性材料103＿1a之延伸方向與絕緣性材料103＿2a之延伸方向交叉，故而即便焊墊P1＿1a與焊墊P1＿2a於X或Y方向上某程度地偏移，導電性材料102＿1a與導電性材料102＿2a之接觸面積亦不那麼降低。因此，第2實施方式中，可相對於接合面B＿mc1中之焊墊P1＿1a與焊墊P1＿2a之偏移使接觸電阻低且穩定。
(第3實施方式) 圖23係表示第3實施方式之焊墊P1＿1a之構成例之俯視圖。於第2實施方式中，於自Z方向觀察之俯視時，焊墊P1＿1a之導電性材料102＿1a於層間絕緣膜ILD1＿1之表面，具有包括於X方向上延伸之細長形狀與於Y方向上延伸之細長形狀之網眼構造。因此，於自Z方向觀察之俯視時，絕緣性材料103＿1a於層間絕緣膜ILD1＿1之表面形成為島嶼狀(點狀)，於X方向及Y方向上呈矩陣狀二維排列。於將絕緣材料103＿1a之一個設為第1絕緣部In1＿1時，會形成與上述第1絕緣部In1＿1於Y方向上排列且最接近之第2絕緣部In2＿1、及與上述第1絕緣部In1＿1於X方向上排列且最接近之第3絕緣部In3＿1。
絕緣性材料103＿1a由蝕刻速率較導電性材料102＿1a之材料(例如，銅或鎢等金屬材料)低之材料(例如，氧化矽膜)形成。例如，絕緣性材料103＿1a亦可由較導電性材料102＿1a之材料更難研磨之物理上較硬之材料形成。或者，絕緣性材料103＿1a亦可由較導電性材料102＿1a之材料更難利用研磨劑(漿料)進行化學蝕刻之材料形成。因此，於CMP步驟中，絕緣性材料103＿1a於導電性材料102＿1a之內側成為支柱，可緩和導電性材料102＿1a之碟狀變形。
又，焊墊P1＿2a亦具有與圖23之焊墊P1＿1a相同之構成。因此，雖然未圖示，但是焊墊P1＿2a同樣地，於自Z方向觀察之俯視時，導電性材料102＿2a於層間絕緣膜ILD1＿2之表面中，具有包括於X方向上延伸之細長形狀與於Y方向上延伸之細長形狀之網眼構造。即，於自Z方向觀察之俯視時，絕緣性材料103＿2a於層間絕緣膜ILD1＿2之表面形成為島嶼狀(點狀)，於X方向及Y方向上呈矩陣狀二維排列。因此，於CMP步驟中，絕緣性材料103＿2a於導電性材料102＿2a之內側成為支柱，可緩和導電性材料102＿2a之碟狀變形。
藉此，能夠使導電性材料102＿1a與導電性材料102＿2a之間之接觸電阻低且穩定。
再者，第3實施方式亦可與第1實施方式、第2實施方式、變化例1、變化例2之任一者組合。即，亦可使第3實施方式之焊墊P1＿1a與第1實施方式、第2實施方式、變化例1、變化例2之任一者之焊墊P1＿2a接合。
又，第3實施方式亦可用於記憶體晶片40＿1、40＿2間之接合。即，第3實施方式亦可應用於記憶體晶片40＿1之焊墊P1＿2b與記憶體晶片40＿2之焊墊P2＿1b。藉此，可抑制焊墊P1＿2b及焊墊P2＿1b之碟狀變形，且記憶體晶片40＿1、40＿2間之接合亦以低電阻穩定化。
(第4實施方式) 圖24係表示第4實施方式之焊墊P1＿2a之構成例之俯視圖。於第4實施方式中，於自Z方向觀察之俯視時，焊墊P1＿2a之導電性材料102＿2a於相對於X及Y方向傾斜之方向上延伸。焊墊P1＿1a之構成可與第1～第3實施方式、變化例1、2之任一者相同。第3實施方式之焊墊P1＿1a中於X方向、Y方向上最接近之點狀絕緣性材料之距離，與如第4實施方式般傾斜之情形時於X方向、Y方向上最接近之點狀絕緣性材料之距離不同。例如，於將絕緣材料103＿2a之一個設為第4絕緣部In4＿2時，會形成與上述第4絕緣部In4＿2於Y方向上排列且最接近之第5絕緣部In5＿2、及與上述第4絕緣部In4＿2於X方向上排列且最接近近之第6絕緣部In6＿2。於Y方向觀察時之第1絕緣部In1＿1與第2絕緣部In2＿1之距離較第4絕緣部In4＿2與第5絕緣部In5＿2之距離近。於X方向觀察時之第1絕緣部In1＿1與第3絕緣部In3＿1之距離較第4絕緣部In4＿2與第6絕緣部In6＿2之距離近。
於第4實施方式中，於將陣列晶片CH＿A1與電路晶片CH＿C1貼合時，焊墊P1＿1a與焊墊P1＿2a於接合面B＿mc1中，以導電性材料102＿1a之延伸方向與導電性材料102＿2a之延伸方向交叉之方式接合。由於絕緣性材料103＿1a之延伸方向與絕緣性材料103＿2a之延伸方向交叉，故而即便焊墊P1＿1a與焊墊P1＿2a於X或Y方向上某程度地偏移，導電性材料102＿1a與導電性材料102＿2a之接觸面積亦不那麼變化。因此，第4實施方式能夠相對於接合面B＿mc1中之焊墊P1＿1a與焊墊P1＿2a之偏移使接觸電阻穩定化。
第4實施方式之其他構成可與第1～第3實施方式之對應之構成相同。因此，第4實施方式亦可獲得第1～第3實施方式之任一者之效果。
(第5實施方式)圖25係表示第5實施方式之接合面B＿mc1之區域之構成例之剖視圖。於第5實施方式中，使用由上述變化例2形成之焊墊P1＿1a、P1＿2a。
於第5實施方式中，通孔觸點V1＿1設置於焊墊P1＿1a之下方，且共通地電性地連接於導電性材料102＿1a。通孔觸點V1＿1將導電性材料102＿1a電性地連接於配線層W1＿1。如此，通孔觸點V1＿1與導電性材料102＿1a作為一體設置於焊墊P1＿1a之整個形成區域。藉此，焊墊P1＿1a之導電性材料102＿1a因通孔觸點V1＿1及導電性材料102＿1a之體積膨脹(熱膨脹)而自接合面B＿mc1稍微鼓起。
又，關於焊墊P1＿2a亦同樣地，通孔觸點V1＿2設置於焊墊P1＿2a之下方，且共通地電性地連接於導電性材料102＿2a。通孔觸點V1＿2將導電性材料102＿2a電性地連接於配線層W1＿2。如此，通孔觸點V1＿2亦與導電性材料102＿2a作為一體設置於焊墊P1＿2a之整個形成區域。藉此，焊墊P1＿2a之導電性材料102＿2a因通孔觸點V1＿2及導電性材料102＿2a之體積膨脹(熱膨脹)而自接合面B＿mc1稍微鼓起。
藉由焊墊P1＿1a、P1＿2a自接合面B＿mc1相互鼓起，接合面B＿mc1中之焊墊P1＿1a、P1＿2a相互確實地接合。藉此，焊墊P1＿1a、P1＿2a可相互以低電阻穩定地連接。
對本發明之幾個實施方式進行了說明，但該等實施方式係作為示例而提出者，並不意圖限定發明之範圍。該等實施方式能夠以其他各種方式實施，於不脫離發明之主旨之範圍內，可進行各種省略、置換、變更。該等實施方式或其變化包含於發明之範圍或主旨中，同樣地包含於申請專利範圍中所記載之發明及與其均等之範圍中。  [相關申請案之引用]
本申請案基於2021年05月21日提出申請之在先日本專利申請案第2021-086411號之優先權而主張優先權利益，藉由引用將其全部內容併入本文中。
1:半導體封裝 10:配線基板 11:絕緣體 12:配線層 13:阻焊劑層 20:金屬凸塊 30:控制器晶片 40:記憶體晶片積層體 40＿1:記憶體晶片 40＿2:記憶體晶片 50:電極 60:密封樹脂 70:焊料球 91:絕緣膜 92:絕緣膜 101＿1a:障壁金屬膜 101＿2a:障壁金屬膜 102＿1a:導電性材料 102＿2a:導電性材料 103＿1a:絕緣性材料 103＿2a:絕緣性材料 201＿1a:障壁金屬膜 202＿1a:導電性材料 B＿chip:接合面 BL1:位元線 BL2:位元線 B＿mc1:接合面 B＿mc2:接合面 CC1:接觸插塞 CH＿A1:陣列晶片 CH＿A2:陣列晶片 CH＿C1:電路晶片 CH＿C2:電路晶片 CL1:柱狀體 CL2:柱狀體 CMOS1:CMOS電路 CMOS2:CMOS電路 Con＿1:第1凹部 Cpri1:接觸插塞 Cpri2:接觸插塞 ILD1＿1:層間絕緣膜 ILD1＿2:層間絕緣膜 ILD2＿1:層間絕緣膜 ILD2＿2:層間絕緣膜 In1＿1:第1絕緣部 In2＿1:第2絕緣部 In3＿1:第3絕緣部 In4＿2:第4絕緣部 In5＿2:第5絕緣部 In6＿2:第6絕緣部 MC1:記憶胞 MC2:記憶胞 MCA1:記憶胞陣列 MCA2:記憶胞陣列 P1＿1a:焊墊 P1＿1b:焊墊 P1＿2a:焊墊 P1＿2b:焊墊 P2＿1a:焊墊 P2＿1b:焊墊 P2＿2a:焊墊 P2＿2b:焊墊 R＿Arr:陣列區域 R＿Pri:周邊區域 R＿Trr:階台區域 RW1:再配線層 SL1:源極線 SL2:源極線 SP1:間隔絕緣膜 SUB1:半導體層 SUB2:半導體層 TSV1:貫通電極 TSV2:貫通電極 V1＿1:通孔觸點 V1＿2:通孔觸點 W1＿1:配線層 W1＿2:多層配線層 W2＿1:配線層 W2＿2:多層配線層 W103＿1a:寬度 WL1:字元線 Wp1＿1a:寬度
圖1係表示第1實施方式之半導體封裝之構成例之剖視圖。  圖2係表示第1實施方式之半導體封裝之一部分之構成例之剖視圖。  圖3A係表示焊墊之構成例之俯視圖。  圖3B係表示焊墊之構成例之俯視圖。  圖3C係表示配線層之構成之一例之俯視圖。  圖4係表示接合面之部分之構成例之剖視圖。  圖5係表示第1實施方式之焊墊之製造方法之一例之剖視圖。  圖6係表示接在圖5之後之焊墊之製造方法之一例之剖視圖。  圖7係表示接在圖6之後之焊墊之製造方法之一例之剖視圖。  圖8係表示接在圖7之後之焊墊之製造方法之一例之剖視圖。  圖9係表示接在圖8之後之焊墊之製造方法之一例之剖視圖。  圖10係表示接在圖9之後之焊墊之製造方法之一例之剖視圖。  圖11係表示接在圖10之後之焊墊之製造方法之一例之剖視圖。  圖12係表示電路晶片之貫通電極之區域之形成步驟之一例之剖視圖。  圖13係表示接在圖12之後之焊墊之製造方法之一例之剖視圖。  圖14係表示接在圖13之後之焊墊之製造方法之一例之剖視圖。  圖15係表示接在圖14之後之焊墊之製造方法之一例之剖視圖。  圖16係表示接在圖15之後之焊墊之製造方法之一例之剖視圖。  圖17係表示接在圖16之後之焊墊之製造方法之一例之剖視圖。  圖18A係表示焊墊之製造方法之另一例之剖視圖。  圖18B係表示接在圖18A之後之焊墊之製造方法之剖視圖。  圖18C係表示接在圖18B之後之焊墊之製造方法之剖視圖。  圖18D係表示接在圖18C之後之焊墊之製造方法之剖視圖。  圖19A係表示焊墊之製造方法之又一例之剖視圖。  圖19B係表示接在圖19A之後之焊墊之製造方法之剖視圖。  圖19C係表示接在圖19B之後之焊墊之製造方法之剖視圖。  圖19D係表示接在圖19C之後之焊墊之製造方法之剖視圖。  圖19E係表示接在圖19D之後之焊墊之製造方法之剖視圖。  圖19F係表示接在圖19E之後之焊墊之製造方法之剖視圖。  圖19G係表示接在圖19F之後之焊墊之製造方法之剖視圖。  圖20A係表示電路晶片之貫通電極之區域之形成步驟之另一例之剖視圖。  圖20B係表示接在圖20A之後之貫通電極之區域之形成步驟之另一例之剖視圖。  圖20C係表示接在圖20B之後之貫通電極之區域之形成步驟之另一例之剖視圖。  圖20D係表示接在圖20C之後之貫通電極之區域之形成步驟之另一例之剖視圖。  圖20E係表示接在圖20D之後之貫通電極之區域之形成步驟之另一例之剖視圖。  圖20F係表示接在圖20E之後之貫通電極之區域之形成步驟之另一例之剖視圖。  圖21係表示第2實施方式之焊墊之構成例之俯視圖。  圖22係表示第2實施方式之接合面之區域之構成例之剖視圖。  圖23係表示第3實施方式之焊墊之構成例之俯視圖。  圖24係表示第4實施方式之焊墊之構成例之俯視圖。  圖25係表示第5實施方式之接合面之區域之構成例之剖視圖。
101_1a:障壁金屬膜
102_1a:導電性材料
103_1a:絕緣性材料
ILD1_1:層間絕緣膜
P1_1a:焊墊
V1_1:通孔觸點
W1_1:配線層
W103_1a:寬度
Wp1_1a:寬度

Claims (14)

  1. 一種半導體裝置，其具備：基板，其設置有第1半導體電路；第1焊墊，其設置於上述基板；第1絕緣層，其設置於上述第1焊墊之外側；第2焊墊，其與上述第1焊墊接合；以及第2絕緣層，其設置於上述第2焊墊之外側，且與上述第1絕緣層接合；且上述第1焊墊於上述第1焊墊與上述第2焊墊之接合面，包含第1導電性材料、及設置於上述第1導電性材料之內側之第1絕緣性材料。
  2. 如請求項1之半導體裝置，其中於上述接合面，上述第1絕緣性材料之至少一部分在第1方向延伸。
  3. 如請求項1或2之半導體裝置，其中於上述接合面，上述第1絕緣性材料之面積小於上述第1導電性材料之面積。
  4. 如請求項1或2之半導體裝置，其中上述第2焊墊於上述接合面，包含第2導電性材料、及設置於上述第2導電性材料之內側之第2絕緣性材料。
  5. 如請求項2之半導體裝置，其中 上述第2焊墊於上述接合面，包含第2導電性材料、及設置於上述第2導電性材料之內側之第2絕緣性材料；於上述接合面，上述第2絕緣性材料之至少一部分於第2方向延伸，該第2方向係處於上述接合面內之方向且與上述第1方向不同。
  6. 如請求項1之半導體裝置，其中於上述接合面，上述第1絕緣性材料包含：第1絕緣部；第2絕緣部，其與上述第1絕緣部於第1方向排列且最接近上述第1絕緣部；及第3絕緣部，其與上述第1絕緣部於第2方向排列且最接近上述第1絕緣部，該第2方向係處於上述接合面內之方向且與上述第1方向垂直。
  7. 如請求項6之半導體裝置，其中於上述接合面，上述第2絕緣性材料包含：第4絕緣部；第5絕緣部，其與上述第4絕緣部於上述第1方向排列且最接近上述第4絕緣部；以及第6絕緣部，其與上述第4絕緣部於上述第2方向排列且最接近上述第4絕緣部；且將與上述第1絕緣部在上述第1方向最接近之上述第2絕緣部之距離設 為第1距離，將與上述第4絕緣部在上述第1方向最接近之上述第5絕緣部之距離設為第2距離時，上述第1距離與上述第2距離不同。
  8. 如請求項1之半導體裝置，其中上述第1半導體電路包含記憶胞陣列與控制上述記憶胞陣列之CMOS電路之任一者，且於隔著上述接合面而與上述第1半導體電路相反方向側，進而具備第2半導體電路，該第2半導體電路包含上述記憶胞陣列與控制上述記憶胞陣列之CMOS電路之另一者。
  9. 如請求項1之半導體裝置，其中上述第1半導體電路包含第1記憶胞陣列與控制上述第1記憶胞陣列之第1CMOS電路，且於隔著上述接合面而與上述第1半導體電路相反方向側，進而具備第2半導體電路，該第2半導體電路包含第2記憶胞陣列與控制上述第2記憶胞陣列之第2CMOS電路。
  10. 如請求項1之半導體裝置，其中上述第1絕緣層與上述第1絕緣性材料同時形成。
  11. 如請求項1之半導體裝置，其中 上述第1絕緣層及上述第1絕緣性材料包含氧與矽，上述第1導電性材料包含銅、金、或銅及金。
  12. 一種半導體裝置之製造方法，其係於第1基板設置第1半導體電路；設置覆蓋上述第1半導體電路之第1膜；於上述第1膜，以於第1凹部之周圍形成第1絕緣層，且於上述第1凹部之內側形成第1絕緣性材料之方式，形成上述第1凹部；於上述第1凹部設置第1導電材料；以露出上述第1絕緣層之表面及上述第1絕緣性材料之表面之方式研磨上述第1導電材料；於第2基板設置第2半導體電路；設置覆蓋上述第2半導體電路之第2膜；於上述第2膜，以於第2凹部之周圍形成第2絕緣層之方式，形成上述第2凹部；於上述第2凹部設置第2導電材料；以露出上述第2絕緣層之表面之方式研磨上述第2導電材料；以及將上述第1絕緣層與上述第2絕緣層接合，將上述第1導電材料與上述第2導電材料接合。
  13. 如請求項12之半導體裝置之製造方法，其中於形成上述第2凹部時，於上述第2凹部之內側形成第2絕緣性材料，於以露出上述第2絕緣層之表面之方式研磨上述第2導電材料時，亦 露出上述第2絕緣性材料之表面。
  14. 如請求項13之半導體裝置之製造方法，其中上述第1絕緣性材料包含各自分離之複數個第1部，上述第2絕緣性材料包含各自分離之複數個第2部，自與上述第1基板垂直之方向觀察，上述複數個第1部與上述第2導電材料重疊，上述複數個第2部與上述第1導電材料重疊。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110084574A1 (en) * 2008-06-26 2011-04-14 Michelin Recherche Et Technique S.A. Sandwich piezoelectric device with solid copper electrode
TWI458057B (zh) * 2008-05-28 2014-10-21 Renesas Electronics Corp Semiconductor device and manufacturing method thereof
US20160365497A1 (en) * 2015-06-10 2016-12-15 Samsung Electronics Co., Ltd. Light emitting device package
WO2021026865A1 (zh) * 2019-08-15 2021-02-18 深圳市汇顶科技股份有限公司 一种芯片互连结构、芯片及芯片互连方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI458057B (zh) * 2008-05-28 2014-10-21 Renesas Electronics Corp Semiconductor device and manufacturing method thereof
US20110084574A1 (en) * 2008-06-26 2011-04-14 Michelin Recherche Et Technique S.A. Sandwich piezoelectric device with solid copper electrode
US20160365497A1 (en) * 2015-06-10 2016-12-15 Samsung Electronics Co., Ltd. Light emitting device package
WO2021026865A1 (zh) * 2019-08-15 2021-02-18 深圳市汇顶科技股份有限公司 一种芯片互连结构、芯片及芯片互连方法

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