TWI497687B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

Info

Publication number
TWI497687B
TWI497687B TW100133441A TW100133441A TWI497687B TW I497687 B TWI497687 B TW I497687B TW 100133441 A TW100133441 A TW 100133441A TW 100133441 A TW100133441 A TW 100133441A TW I497687 B TWI497687 B TW I497687B
Authority
TW
Taiwan
Prior art keywords
substrate
metal layer
front surface
conductor
gap
Prior art date
Application number
TW100133441A
Other languages
English (en)
Other versions
TW201241987A (en
Inventor
Mitsuyoshi Endo
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of TW201241987A publication Critical patent/TW201241987A/zh
Application granted granted Critical
Publication of TWI497687B publication Critical patent/TWI497687B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/24146—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/82005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82031—Reshaping, e.g. forming vias by chemical means, e.g. etching, anodisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92132—Sequential connecting processes the first connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

半導體裝置及其製造方法
在本文中所述之實施例整體而言係關於一種半導體裝置及其製造方法。
相關申請案之相互參考
本申請案係基於且主張於2011年4月4日申請之前案日本專利申請案第2011-82951號案之優先權的利益；該案之全部內容併入本文作為參考。
隨著近來對於個人數位助理、儲存裝置等等之小型化的要求，因此對於以高密度安裝複數個半導體晶片的要求亦與日俱增。在此等情況下，已有研究一種具有複數個半導體晶片堆疊於其中之結構。例如，一種半導體模組係以如下之方式製造：在半導體晶圓之狀態中於每一半導體晶片上執行一操作測試，以便選擇非缺陷晶片，並且將該等非缺陷晶片堆疊在一起。通常，每一晶片具有一貫穿通孔、形成在該晶片之頂部表面上的連接墊、以及形成在該晶片之底部表面上的連接凸塊。形成在一上方晶片上之凸塊係連接至形成在一下方晶片上之襯墊，藉此電連接該上方及下方晶片。
然而，使用凸塊以連接半導體晶片會導致連接間距之增加。額外地，亦需要確保每一晶片具有一特定厚度以處理在凸塊與襯墊之間的連接。這些情況會妨礙該半導體模組之厚度的縮減。再者，堆疊晶片之數量的增加亦會造成該堆疊程序之生產量以及連接良率之降低。
在另一方面，亦有一種製造半導體模組之另一方法，其中半導體晶圓係先結合在一起且然後再分割成晶片。在此一方法中，可以省略用於提供晶圓之間之電連接的凸塊。這便可以解決當使用凸塊時所造成之上述問題。
當採用將結合之半導體晶圓分割成晶片之該方法時，便無法僅選擇出所要堆疊之非缺陷半導體晶片。因此，該方法需要一對應措施來避免當存在一缺陷半導體晶片時在整個半導體模組發生失效的情況。例如，以如下方式可以避免在整個半導體模組中發生失效的情況。亦即，針對被連接至一通孔焊墊之每一線路事先形成一修整區域，且若發現一缺陷晶片時，便施加一雷射束至該修整區域以斷開連接該對應的線路。
然而，斷開連接之線路數量的增加會造成修整區域之增加。這可能會導致設計自由度的限制且造成生產量的降低。此外，亦可能會發生諸如由於線路之不完整的熔接所造成之切割失效、由於線路之金屬材料之散射所造成之短路失效、以及由於一切割部分之形狀的控制困難所造成之切割穩定性不足等等的其他問題。尤其在使用銅線路的情況中，熔接及切割之困難度會增加，這會造成這些問題更為嚴重。
為了將半導體晶圓結合在一起，到目前為止還尚未建立用以確保在貫穿晶圓之通孔與形成在每一晶圓上之半導體元件之間的電連接以及用於確保與外部部分之電連接的有效結構或製造程序。
本發明之實施例係實現一種具有複數個晶片堆疊於其中之半導體裝置。
整體而言，依照一實施例，一第一基板包括一被提供在該第一基板之一第一前表面上方之第一半導體元件；一被電連接至該第一半導體元件且在該第一基板之第一前表面上方具有一第一間隙之第一金屬層；及一被形成在該第一金屬層及該第一前表面之各者上方之第一絕緣層。該第一基板亦包括一第一導體，其被埋設在一位在該第一金屬層之一形成位置處的第一通孔中，該第一通孔沿著該第一基板之厚度方向貫穿該第一基板。一第二基板包括一被提供在該第二基板之一第二前表面上方之第二半導體元件；及一第二導體，其被埋設在一沿著該第二基板之厚度方向貫穿該第二基板之第二通孔。與該第一基板之該第一前表面相對之一第一後表面及該第二基板之該第二前表面係結合在一起以連接該第一導體與該第二導體。該第一導體包括一第一部分及一第二部分，該第一部分在介於該第一金屬層與該第一前表面之間的範圍內具有等於該第一間隙之直徑的直徑；該第二部分在介於該第一金屬層及該第一後表面之間的範圍內具有大於該第一間隙之直徑且小於該第一金屬層之外徑的直徑。該第一絕緣層具有一形成在該第一金屬層上方之間隙，該間隙係大於該第一間隙且小於該第一金屬層之外徑。
本發明之實施例可實現一種具有複數個晶片堆疊於其中之半導體裝置。
一種半導體裝置及其製造方法之例示性實施例將參考附圖來詳細說明如下。然而本發明並未侷限於以下的實施例。
(第一實施例)
依照第一實施例之半導體裝置及其製造方法將參考圖式來予以說明。圖1係依照第一實施例之一通孔焊墊的概要平面圖。圖2至11係剖面圖，每一剖面圖概要說明依照第一實施例之半導體裝置之製造方法的例示性程序。如圖2所示，絕緣層12及14係形成在半導體晶圓10上，且由金屬(例如銅)製成之一通孔焊墊16係形成在絕緣層12上。通孔焊墊16在平面圖(在垂直於該半導體晶圓10之主表面之方向上)中具有一圓環形狀，且形成在該通孔焊墊16下方之絕緣層12於一中央部分處係曝露的。該通孔焊墊16在一末端部分處係連接至一金屬線路(以下稱之為「線路」)18。該線路18係連接至一未圖示之半導體元件(例如，諸如快閃記憶體或DRAM(動態隨機存取記憶體)之半導體記憶體)。如圖1所示，絕緣層14係被形成在一距該接合區之中心一預定距離或遠離該中心之一區域中，使得該通孔焊墊16之一部分(在距該接合區中心至該預定距離之範圍中的一部分)係被曝露。在此，A係表示該通孔焊墊16之外徑；B係表示該通孔焊墊16之一未由該絕緣層14所覆蓋之部分的外徑(該絕緣層14之一開口直徑)；且C係表示該通孔焊墊16之內徑(不包括該通孔焊墊之直徑)。在如上述之結構中，維持A>B>C之關係。例如，A為20微米；B為14微米；而C為7微米。
複數個晶片(例如針對300毫米之一晶圓大約超過700個晶片)係形成在該半導體晶圓10上，且每一晶片具有如圖1及2所示之通孔焊墊16的結構。在該半導體晶圓10之狀態中，以諸如探針卡之測試裝置在每一晶片上執行一操作測試。藉此，便可詳列出缺陷半導體晶片，這便可以產生圖式資料(其被稱之為晶圓圖)，其中表示出該等缺陷晶片在該半導體晶圓10上的位置。
接下來，如圖3所示，在一缺陷晶片之通孔焊墊16上塗覆一蝕刻劑71。因此，該通孔焊墊16之曝露部分便可被移除。以如上述之方式，便可以獲得該半導體晶圓10，其中每一缺陷晶片之通孔焊墊之一部分係被移除的。
然後，將該半導體晶圓10與一用作為基底基板之第二晶圓0堆疊在一起。該半導體晶圓0具有在數量上對應於該通孔焊墊16之數量之連接墊2。該半導體晶圓0與該半導體晶圓10係在半導體晶圓0之連接墊2經對準而定位在被提供於半導體晶圓10之每一晶片上之該通孔焊墊16的正上方的狀態結合在一起。在此第一實施例中，一黏著層6係用以將半導體晶圓0及10結合在一起。或者，該半導體晶圓0及10可直接結合在一起而無需使用該黏著層6。又或者，諸如一絕緣層之層體可被形成在該半導體晶圓0及該半導體晶圓10之其中一者或兩者上，且該半導體晶圓0及10可經由該絕緣層等等而被結合在一起。例如，可進一步形成一用以覆蓋絕緣層14及通孔焊墊16之絕緣層。此時，該晶圓0及該晶圓10之組合厚度可為例如775微米。
之後，在半導體晶圓0被固持之狀態下，將該半導體晶圓10之後表面研磨且拋光至20微米之厚度。此時，由於該半導體晶圓10係與該半導體晶圓0結合在一起，因此可以確保能夠承受拋光之剛性。在拋光之後，在該半導體晶圓10之後表面(拋光表面)上形成一絕緣層17，如圖4所示。
一光阻劑圖案(未圖示)係利用習知的技術而形成在後表面上，然後執行乾式蝕刻，藉此形成一通孔15。在該第一實施例中，沿著平行於該半導體晶圓10之主表面的方向所截取之該通孔15之橫截面具有一實質上呈圓形的形狀。在平面圖中，該橫截面之中心實質上與通孔焊墊16之中心重合，且該橫截面之內徑D(例如，10微米)滿足A>D>C之關係(A表示通孔焊墊16之外徑；C表示通孔焊墊16之內徑(不包括該通孔焊墊之直徑)；且D表示該通孔15之內徑)。因此，在用以形成貫穿該晶圓10之通孔15的蝕刻程序期間，該通孔焊墊16係在從該晶圓之通孔焊墊16之後表面之範圍中的一部分(包括絕緣層17及12)已被蝕刻之後用以作為一禁止蝕刻之遮罩。針對未由該通孔焊墊16所阻擋之該通孔焊墊16之一間隙部分持續進行蝕刻。蝕刻繼續進行，直到黏著層6被蝕刻達到該半導體晶圓0之電極墊2為止。
如此形成之通孔15具有階部，該等階部係形成在對應於通孔焊墊16之位置，如圖5所示。這導到兩個區域之形成：一大直徑區域，其範圍從半導體晶圓10之後表面至通孔焊墊16；及一小直徑區域，其範圍從通孔焊墊16至半導體晶圓0之電極墊2。在此例中，該電極墊2之一部分與該通孔焊墊16之一部分各者的表面(面向半導體晶圓10之後表面)係被曝露的。若執行蝕刻而使得通孔15之側表面實質上垂直於半導體晶圓10，則電極墊2之曝露的部分具有大約為7微米之直徑且通孔焊墊16之曝露部分具有大約10微米之直徑(然而，在此例中，通孔焊墊16具有其內徑約為7微米之圓環形狀)。因此，電極墊2之曝露區域實質上等於該通孔焊墊16之曝露區域。
之後，一絕緣薄膜13係形成在通孔15之內壁上。然後，如圖6所示，形成在面向半導體晶圓10之後表面之該表面上的絕緣薄膜13係藉由RIE(反應性離子蝕刻)而移除，使得絕緣薄膜13僅保留在該通孔15之側壁上。
此外，一電鍍種晶層係視需要而形成在通孔15中，且利用該半導體晶圓0作為一電鍍電極來實施銅電鍍。如圖7所示，一金屬11(例如銅)係填充在通孔15中。由於通孔15係形成在每一晶片區域中，因此電鍍係在複數個通孔15平行電連接至半導體晶圓0的狀態下來執行。使用半導體晶圓0作為一電極便可進行底部至頂部填充，減少空隙失效，並且增進半導體晶圓10中之通孔15之間的電鍍均勻性。此外，即使通孔具有一高縱橫比，仍可增進填充性質。
因此，該通孔焊墊16其面向半導體晶圓10之後表面側之表面係電連接至被形成在通孔15中之金屬11。在此同時，該電極墊2其面向晶圓10之後表面側的表面係電連接至被形成在通孔15中之金屬11。此外，通孔焊墊16之曝露區域係實質上等於電極墊2之曝露區域，這使得可令人滿意地保持曝露部分與被形成在通孔中之金屬11之間的電連接。
在此之後，重複相同的程序。詳言之，在另一半導體晶圓20之每一晶片區域上形成一半導體元件及一通孔焊墊26，且接著執行一失效測試。如圖3所示，在每一缺陷晶片中移除一預定線路。之後，如圖8所示，半導體晶圓20之元件表面與半導體晶圓10之後表面(拋光表面)便利用一黏著層72而結合在一起。然後，將半導體晶圓20之後表面予以拋光以藉此將半導體晶圓20薄化至20微米之厚度。在拋光表面上形成一絕緣薄膜23，然後在半導體晶圓20之後表面上執行蝕刻以藉此形成一通孔25。該通孔25具有大於通孔焊墊26之間隙之直徑的直徑，且形成該通孔25以使得該通孔25之中心與通孔焊墊26之中心在平面圖中係實質上重合。因此，通孔25具有一大直徑部分，其範圍從半導體晶圓20之後表面至通孔焊墊26，且具有一小直徑部分，其範圍從通孔焊墊26至被形成在通孔15中之金屬11。在蝕刻程序期間，半導體晶圓10之後表面與半導體晶圓20之前表面係經由黏著層72而結合在一起。因此，不僅半導體晶圓20且該黏著層72亦被蝕刻以曝露半導體晶圓10之金屬11。以如上述之方式，便可形成貫穿該半導體晶圓20之通孔25。在該絕緣薄膜23形成在側壁之後，利用該半導體晶圓0作為一電鍍電極而將金屬21填充在該通孔25中(圖8)。
圖9顯示一結構，其中半導體晶圓0、10、20、30、40係堆疊在一起(該結構之組件係顯示在其他圖式中，所以將其元件標號及說明予以省略)。然而，在此例中，經由一測試之結果已顯示出該半導體晶圓20在圖示位置處包括缺陷晶片。基於此一理由，該通孔焊墊之一部分係以如上述之方式利用一蝕刻劑予以移除，且接著將其他的半導體晶圓10及30堆疊在一起。這使得針對通孔之程序可以完成而不會在該半導體晶圓20中形成該通孔的期間被通孔焊墊所妨礙。因此，在半導體晶圓20中之晶片與被形成在通孔中之導體便可電連接。
之後，如圖10所示，該半導體晶圓0之前表面被研磨且拋光以曝露該連接墊2(電極)。該等半導體晶圓10至40堆疊在一起之該結構係具有80微米之厚度。因此，若該結構在半導體晶圓0之拋光期間被固持或夾持，則該半導體晶圓0便可被適當地拋光。這使得可以製造出一結構，其包括一貫穿整個結構之通孔及導體部分(曝露至半導體晶圓40之後表面的連接墊2及導體)，該等導體部分係電連接至該通孔且被曝露至該結構之前及後表面。
之後，藉由習知的技術(諸如鋸切或刻劃)將該半導體晶圓之堆疊層體結構分割成晶片。由於拋光及移除半導體晶圓0之一上方部分，該堆疊層體結構具有80微米或更大之厚度。這可促進有利地切割。
圖11顯示一結構，其中以如上述方式形成之半導體模組100-1及100-2係經由凸塊50而堆疊在一起。在圖11所示之結構中，該兩半導體模組100-1及100-2各自藉由堆疊四個半導體基板而形成。或者，具有不同數量(例如，五層或三層)之基板堆疊在一起之模組亦可被堆疊。例如，當具有4層結構之半導體模組包括一缺陷半導體晶片時，該半導體模組可以與一具有5層結構之半導體模組堆疊在一起。在另一方面，當具有4層結構之該半導體模組未包括缺陷半導體晶片時，該半導體模組可進一步與一具有4層結構之半導體模組堆疊在一起。因此，取決於存在或不存在一缺陷晶片之具有不同層體結構的半導體模組之堆疊便可以調整全部記憶體容量以維持恆定。
(第二實施例)
圖12係依照第二實施例之一半導體模組的概要示意圖。就用以實現與第一實施例所示之半導體模組之組件相同功能的該等組件而言，元件標號與其說明予以省略。
整體而言，通孔(及形成於其中之導體)係用於一信號線、一接地線、一電源線等等。在某些例子中，取決於所要的用途，有時並不需要將電極曝露至半導體模組之前表面。在此例中，如圖12所示，在半導體晶圓10中之通孔焊墊52可具有不包括間隙之一結構。絕緣層54及56係形成在通孔焊墊52中。在此例中，可採用以下之程序。亦即，製備一透明基底基板(諸如玻璃)以取代半導體晶圓0及基底基板，且該半導體晶圓10之前表面係利用一黏著層而暫時地結合在一起，如此使得可以拋光半導體晶圓10之後表面。然後，相同於第一實施例，該複數個結合的半導體晶圓係受到熱處理及其他處理，且將該半導體晶圓10與基底基板整體分離且移除。這導致降低半導體晶圓0之成本。亦可以採用一種結構，其中一欲電連接至一通孔的電極係被提供在半導體晶圓10上且在移除基底基板之後將該電極曝露至前表面。
亦有已知在堆疊一SOI(絕緣體上的矽)基板之後於基板之間利用一通孔來建立電導通的習知方法。詳言之，一具有一半導體元件形成於其上之晶圓之前表面(元件形成表面)及具有一半導體元件形成於其上之SOI基板之前表面(元件形成表面)係利用氧化物結合而結合在一起。之後，利用一蝕刻劑將形成在SOI基板之後表面側上之該Si基板移除以曝露一層SiO2 薄膜(BOX薄膜)。之後，形成一通孔以在該SOI基板與晶圓兩者之元件與該通孔之間形成電導通。然而，此結構係基於使用一昂貴SOI基板的前提，這會造成應用範圍的限制。此外，元件形成表面之結合可能會導致降低的結合良率。再者，亦尚未揭示任何形成貫穿一模組(一具有複數個半導體晶圓堆疊於其中之結構)的通孔之方法。不同於此一習知技術，上述實施例並未侷限於SOI基板且因此具有廣泛的可應用性。再者，在上述實施例中，該等元件形成表面並未結合在一起，藉此可防止結合良率被降低。再者，每一通孔係在該等晶圓結合在一起之後被形成在預定位置處。這提供了可以容易地形成貫穿該堆疊結構之通孔的優點，即使在大數量的晶圓被堆疊之情況下亦然。
應注意，本發明並未侷限於上述實施例，而是能以各種不同方式來予以修改。例如，欲堆疊之晶圓數量並未侷限於四個，而是可以堆疊八個或更多個晶圓。欲堆疊之晶圓的數量之增加可有助於用於分離或移除一晶圓或一基底基板之處理。
由於該基底基板之後會從該晶圓結構分離或移除，因此可以使用各種不同材料，包括半導體晶圓及透明基板(諸如玻璃)。然而，在執行一熱處理期間該分離/移除程序於之後被執行的例子中，有需要針對熱膨脹/收縮之考量來選擇一材料。應瞭解，當使用玻璃等等作為該基底基板時，便難以利用該基底基板來作為一電鍍電極。
亦可使用除了電鍍以外之方法來將一導體填充至一通孔中。亦不一定需要將導體填充於通孔中的所有空間。例如，該導體亦可被符合形狀地設置。
此外，只要在特定橫截面中滿足A(表示通孔焊墊之外徑)>B(表示該通孔焊墊其未由該上方絕緣薄膜所覆蓋之一部分的外徑)>C(表示通孔焊墊之內徑)的關係以及A>D(表示通孔直徑)>C之關係即可。詳言之，就間隙與直徑之間的量值關係而言，只要在特定橫截面(垂直於該基板之前表面之一表面)中之金屬層的間隙與該橫截面之直徑之間的量值關係得以確保即可。並不一定要在任何橫截面中確保該量值關係。例如，只要可以確保在一預定橫截面中之量值關係即可，在垂直橫截面中之該金屬層等等之間隙亦可大於該孔直徑。
圖13係一包括具有另一形狀之通孔焊墊之半導體裝置的概要平面圖。如圖13所示，一通孔焊墊504係例如具有一U形狀(由一上方絕緣層510所覆蓋之通孔焊墊504之輪廓係由虛線所示)。因此，在平行於圖13之橫向方向的一橫截面中，其保持A>B>C之關係。然而，在平行於圖13之縱向方向(垂直方向)的一橫截面中，該通孔焊墊504並未以預定間隔來提供，這造成無法定義A、B及C之間的關係。然而，在此一結構中，若具有橫截面為一圓形形狀且具有B>D>C之關係的通孔係形成在圖13的中心處，則該通孔焊墊在用以形成該通孔之蝕刻期間係作為一遮罩，藉此達成本發明之一目的。以同樣的觀點，應瞭解即使在例如以預定間隔彼此平行所形成之線路被用以取代該通孔焊墊的情況下，亦可獲得與第二實施例之通孔焊墊相同的功能。
換言之，通孔可經形成以滿足A>D>B之關係。同樣在此情況中，僅藉由移除在一缺陷晶片中之通孔焊墊之曝露部分係無法建立在通孔(形成於其中之導體)與通孔焊墊之間的電絕緣，但該通孔焊墊在用以形成該通孔之蝕刻期間係作為一遮罩。在實施例中使用名稱「通孔焊墊」係因為一通孔焊墊被提供在一貫穿通孔的中間且被電連接至形成在該通孔中之導體。然而，此相同功能亦可藉由使用線路或其他金屬薄膜來獲得。
當一通孔等等之橫截面具有一圓形形狀時，可以增進該導體之填充性質。每一通孔之橫截面的形狀並不侷限於圓形形狀，而是亦可以為矩形形狀或其他形狀。此外，該橫截面亦可以為錐形。
用以形成半導體元件及類似物之程序係可在用以結合該晶圓及該基底基板之程序之前或在該結合程序之後來實施。其他程序之順序可以自由地變更，其範圍乃係熟習此項技術者基於本發明之範疇而可以合理地瞭解。
每一基板之前表面包括該前表面及在該前表面附近延伸於高度及深度方向的一區域。在每一基板之前表面上之元件及類似物的形成係包括在該前表面上及在該前表面之附近區域中之元件的形成。
基板之結合包括經由一黏著層等等之基板的間接結合。再者，在若干孔被連續地形成之情況係指時間上的連續性，且包括在相同腔室中一次性地蝕刻兩個孔(在不禁止蝕刻劑成份變更的情況下)。再者，就電連接關係而言，並不一定要直接連接該等組件。該等組件亦可彼此間接地連接。
雖然已針對特定實施例來說明，然而這些實施例僅作為實例來呈現，且並不意欲限制本發明之範疇。實際上，在本文中所述之創新性實施例能以各種不同的其他形式來實施；再者，在不背離本發明之精神的情況下，可對在本文中所述之實施例之形式進行各種不同的省略、替代及變更。隨附的申請專利範圍及其均等物係意欲涵蓋落在本發明之範疇及精神內的此等形式及修飾。
0．．．半導體晶圓
2．．．電極墊
6．．．黏著層
8．．．線路
10．．．半導體晶圓
11．．．金屬
12．．．絕緣層
13．．．絕緣薄膜
14．．．絕緣層
15．．．通孔
16．．．通孔焊墊
17．．．絕緣層
18．．．線路
20．．．半導體晶圓
21．．．金屬
23．．．絕緣薄膜
25．．．通孔
26．．．通孔焊墊
30．．．半導體晶圓
40．．．半導體晶圓
50．．．通孔焊墊
52．．．通孔焊墊
54．．．絕緣層
56．．．絕緣層
71．．．蝕刻劑
72．．．黏著層
100-1．．．半導體模組
100-2．．．半導體模組
504．．．通孔焊墊
510．．．上方絕緣層
圖1係一概要平面圖，其中顯示依照一實施例之一通孔焊墊之附近的組態；圖2至11係截面圖，其等概要顯示依照第一實施例之一半導體裝置之製造方法的例示性程序；圖12係一概要示意圖，其中顯示依照第二實施例之半導體模組；及圖13係一半導體裝置之概要平面圖，該半導體裝置包括具有另一形狀之通孔焊墊。
50．．．通孔焊墊
100-1．．．半導體模組
100-2．．．半導體模組

Claims (16)

  1. 一種半導體裝置，包含：一第一基板結構，其包括：一第一基板；一第一金屬層，其在該第一基板之一第一前表面上方具有一第一間隙；一第一絕緣層，其被形成於該第一金屬層與該第一前表面之各者的上方；及一第一導體，其被埋設在位在該第一金屬層之一形成位置處的一第一通孔中，該第一通孔沿著該第一基板之厚度方向貫穿該第一基板；及一第二基板結構，其包括：一第二基板；一第二導體，其被埋設在沿著該第二基板之厚度方向貫穿該第二基板之一第二通孔中；一第二金屬層，其形成在該第二基板的一第二前表面的上方且具有一第二間隙；及一第二絕緣層，其形成在該第二金屬層及該第二前表面之各者的上方，其中，與該第一基板之該第一前表面相對之一第一後表面及該第二基板之該第二前表面係結合在一起以連接該第一導體與該第二導體，該第一導體包括一第一部分及一第二部分，該第一部分設置在該第一間隙中，該第二部分具有大於該第一間隙 之直徑且小於該第一金屬層之外徑的直徑且設置在該第一金屬層的背面和該第一基板的該第一後表面之間的範圍內，該第一導體的直徑在該第一部分及該第二部分間的邊界處不連續地改變，該第一絕緣層具有形成在該第一金屬層上方之一間隙，該間隙係大於該第一間隙且小於該第一金屬層之該外徑，該第二部分係位在該第一基板內，該第二導體包括一第三部分及一第四部分，該第三部分設置在該第二間隙中，該第四部分具有大於該第二間隙之直徑且小於該第二金屬層之外徑的直徑且設置在該第二金屬層的該背面和該第二基板的第二後表面之間的範圍內，該第二後表面相對於該第二前表面，該第二導體的直徑在該第三部分及該第四部分間的邊界處不連續地改變，該第二絕緣層具有形成在該第二金屬層上方之一間隙，該間隙係大於該第二間隙且小於該第二金屬層之該外徑，且該第四部分係位在該第二基板內。
  2. 如申請專利範圍第1項之半導體裝置，其中，該第一基板結構係藉由拋光該第一後表面而被薄化且接著被連接至該第二基板結構，且該第二基板結構係藉由拋光該第二後表面而被薄化。
  3. 如申請專利範圍第1項之半導體裝置，其中，該第一及第二基板結構各具有50微米或更小之厚度。
  4. 如申請專利範圍第1項之半導體裝置，其中，該第一基板結構進一步包括一電極，該電極被形成在該第一前表面之該第一導體之一形成位置的上方。
  5. 如申請專利範圍第4項之半導體裝置，其中，在該電極與該第一導體之該第一部分之間之一接觸區係實質上等於在該第一金屬層與該第一導體之該第二部分之間之一接觸區。
  6. 一種半導體裝置，包含：一第一基板結構，其包括：一第一基板；一第一金屬層，其在該第一基板之一第一前表面上方具有一第一間隙；一第一絕緣層，其被形成於該第一金屬層與該第一前表面之各者的上方；及一第一導體，其被埋設在位在該第一金屬層之一形成位置處的一第一通孔中，該第一通孔沿著該第一基板之厚度方向貫穿該第一基板；及一第二基板結構，其包括：一第二基板；及一第二導體，其被埋設在沿著該第二基板之厚度方向貫穿該第二基板之一第二通孔中；其中，與該第一基板之該第一前表面相對之一第一後表面及該第二基板之一第二前表面係結合在一起以連接該第一導體與該第二導體， 該第一導體包括一第一部分及一第二部分，該第一部分設置在該第一間隙中，該第二部分具有大於該第一間隙之直徑且小於該第一金屬層之外徑的直徑且設置在該第一金屬層的背面和該第一基板的該第一後表面之間的範圍內，該第一導體的直徑在該第一部分及該第二部分間的邊界處不連續地改變，該第一絕緣層具有形成在該第一金屬層上方之一間隙，該間隙係大於該第一間隙且小於該第一金屬層之該外徑，該第二部分係位在該第一基板內，該第一基板結構進一步包括一電極，該電極被形成在該第一前表面之該第一導體之一形成位置的上方，且該電極與該第一導體之該第一部分之間之一接觸區係實質上等於在該第一金屬層與該第一導體之該第二部分之間之一接觸區。
  7. 如申請專利範圍第6項之半導體裝置，其中，該第一基板結構係藉由拋光該第一後表面而被薄化且接著被連接至該第二基板結構，且該第二基板結構係藉由拋光該第二後表面而被薄化。
  8. 如申請專利範圍第6項之半導體裝置，其中，該第一及第二基板結構各具有50微米或更小之厚度。
  9. 一種半導體裝置，包含：一第一基板結構，其包括：一第一基板； 一第一金屬層；一第一絕緣層，其被形成於該第一金屬層與該第一基板的一第一前表面之各者的上方；一第一導體，其被埋設在位在該第一金屬層之一形成位置處的一第一通孔中，該第一通孔沿著該第一基板之厚度方向貫穿該第一基板；及一第二基板結構，其包括：一第二基板；一第二導體，其被埋設在沿著該第二基板之厚度方向貫穿該第二基板之一第二通孔中，一第二金屬層，其形成在該第二基板的一第二前表面的上方，且該第二金屬層具有一第二間隙；及一第二絕緣層，其形成在該第二金屬層及該第二前表面之各者的上方，其中，與該第一基板之該第一前表面相對之一第一後表面及該第二基板之該第二前表面係結合在一起以連接該第一導體與該第二導體，該第一導體在介於該第一前表面與該第一後表面之間的範圍內具有實質上相同的直徑，該第二導體包括一第一部分及一第二部分，該第一部分設置在該第二間隙中，該第二部分具有大於該第二間隙之直徑且小於該第二金屬層之外徑的直徑且設置在該第二金屬層的一後表面與該第二基板的一第二後表面之間的範圍內，該第二後表面係與該第二前表面相對，該第二導體 的直徑在該第一部分及該第二部分間的邊界處不連續地改變，該第二絕緣層具有形成在該第二金屬層上方之一間隙，該間隙係大於該第二間隙且小於該第二金屬層之該外徑，且該第二部分係位在該第二基板內。
  10. 如申請專利範圍第9項之半導體裝置，其中，該第一基板結構係藉由拋光該第一後表面而被薄化且接著被連接至該第二基板結構，且該第二基板結構係藉由拋光該第二後表面而被薄化。
  11. 一種半導體裝置的製造方法，包含：形成一第一半導體元件於一第一基板之一第一前表面的上方且形成被電連接至該第一半導體元件的一第一金屬層於該第一基板之該第一前表面上方；結合該第一基板之該第一前表面與一基底基板；拋光該第一基板之一第一後表面，該第一後表面係與該第一前表面相對；在該第一後表面中形成具有一預定直徑之一第一通孔；在該第一通孔中形成一第一導體以電連接該第一金屬層與該第一導體；形成一第二半導體元件於一第二基板之一第二前表面上方且形成被電連接至該第二半導體元件且具有一第一間隙之一第二金屬層於該第二基板之該第二前表面上方； 結合該第二基板之該第二前表面與該第一基板之該第一後表面；拋光該第二基板之一第二後表面，該第二後表面係與該第二前表面相對；在該第二基板中形成一第二通孔以與該第一導體之一形成位置連通；在該第二通孔中形成一第二導體；移除該基底基板之一部分；及分割包括至少已結合在一起之該第一基板與該第二基板之一結構，其中，在該第二通孔之該形成步驟中，該第二基板係利用該第二金屬層作為一遮罩而被蝕刻，該第二金屬層在介於該第二後表面與該第二金屬層之間的範圍中具有大於該第一間隙之直徑的直徑且在介於該第二金屬層與該第二前表面之間的範圍中具有該第一間隙，且在該第二導體之該形成步驟中，該第二導體被連接至該第二金屬層。
  12. 一種半導體裝置的製造方法，包含：形成一第一半導體元件於一第一基板之一第一前表面的上方且形成被電連接至該第一半導體元件的一第一金屬層於該第一基板之該第一前表面上方；結合該第一基板之該第一前表面與一基底基板；拋光該第一基板之一第一後表面，該第一後表面係與 該第一前表面相對；在該第一後表面中形成具有一預定直徑之一第一通孔；在該第一通孔中形成一第一導體以電連接該第一金屬層與該第一導體；形成一第二半導體元件於一第二基板之一第二前表面上方且形成被電連接至該第二半導體元件且具有一第一間隙之一第二金屬層於該第二基板之該第二前表面上方；結合該第二基板之該第二前表面與該第一基板之該第一後表面；拋光該第二基板之一第二後表面，該第二後表面係與該第二前表面相對；在該第二基板中形成一第二通孔以與該第一導體之一形成位置連通；在該第二通孔中形成一第二導體；移除該基底基板之一部分；及分割包括至少已結合在一起之該第一基板與該第二基板之一結構，其中，該第二通孔具有實質上等於該第一通孔之直徑的直徑，在該第二金屬層形成之後，在該第二金屬層已形成於其上之該第二基板之該第二前表面的上方形成一絕緣層，該絕緣層具有一小於該第二金屬層之外徑且大於該第一間 隙之第二間隙，在該第二金屬層形成之後且在該第一及第二基板結合之前，當該第二半導體元件具有缺陷時，該第二金屬層係利用該絕緣層作為一遮罩而被蝕刻以使得該第二金屬層之該第一間隙與該絕緣層之該第二間隙具有相同的直徑，且在該第二導體之該形成步驟中，該第二導體與該第二金屬層被斷開連接。
  13. 如申請專利範圍第11或12項之半導體裝置的製造方法，其進一步包含重複從該第二半導體元件與該第二金屬層形成於該第二基板上方至形成該第二導體之一程序，直到欲被堆疊之基板的數量達到一預定數量為止。
  14. 如申請專利範圍第11或12項之半導體裝置的製造方法，其中，該基底基板係一透明基板；且在該基底基板之移除步驟中，該透明基板係與該結構分離。
  15. 如申請專利範圍第11或12項之半導體裝置的製造方法，其中，該第一基底基板係一半導體基板與一導體基板中之一者，且在該第一導體之該形成步驟中，該第一導體係藉由利用以該基底基板作為一電鍍電極之電鍍而被填充在該第一通孔中。
  16. 如申請專利範圍第11或12項之半導體裝置的製 造方法，其中，該第一及第二後表面被拋光以將第一及第二基板之各者拋光至50微米或更小之厚度。
TW100133441A 2011-04-04 2011-09-16 半導體裝置及其製造方法 TWI497687B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011082951A JP2012221998A (ja) 2011-04-04 2011-04-04 半導体装置ならびにその製造方法

Publications (2)

Publication Number Publication Date
TW201241987A TW201241987A (en) 2012-10-16
TWI497687B true TWI497687B (zh) 2015-08-21

Family

ID=46926100

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100133441A TWI497687B (zh) 2011-04-04 2011-09-16 半導體裝置及其製造方法

Country Status (3)

Country Link
US (2) US8884396B2 (zh)
JP (1) JP2012221998A (zh)
TW (1) TWI497687B (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MX344799B (es) 2011-05-01 2017-01-06 Halkey-Roberts Corp Válvula macho de reflujo.
JP5548173B2 (ja) 2011-08-31 2014-07-16 株式会社東芝 半導体基板及びその製造方法
US9040837B2 (en) * 2011-12-14 2015-05-26 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US9096419B2 (en) * 2012-10-01 2015-08-04 Qualcomm Mems Technologies, Inc. Electromechanical systems device with protrusions to provide additional stable states
US9536777B2 (en) * 2013-03-13 2017-01-03 Taiwan Semiconductor Manufacutring Company, Ltd. Interconnect apparatus and method
US9147662B1 (en) * 2013-12-20 2015-09-29 Stats Chippac Ltd. Integrated circuit packaging system with fiber-less substrate and method of manufacture thereof
JP5959071B2 (ja) * 2014-08-25 2016-08-02 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ 半導体構造中の貫通電極の形成方法
KR102320821B1 (ko) * 2014-09-11 2021-11-02 삼성전자주식회사 반도체 패키지
CN104503648B (zh) * 2015-01-09 2017-06-09 京东方科技集团股份有限公司 一种内嵌式触摸屏及显示装置
JP6251406B2 (ja) * 2015-01-16 2017-12-20 雫石　誠 半導体素子とその製造方法
CN104716060A (zh) * 2015-03-16 2015-06-17 中国航天科技集团公司第九研究院第七七一研究所 一种tsv多层芯片键合方法
US10074625B2 (en) * 2015-09-20 2018-09-11 Qualcomm Incorporated Wafer level package (WLP) ball support using cavity structure
US10636767B2 (en) 2016-02-29 2020-04-28 Invensas Corporation Correction die for wafer/die stack
US10840190B1 (en) * 2019-05-16 2020-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
CN112201645B (zh) * 2020-09-18 2024-04-12 武汉新芯集成电路制造有限公司 套刻标识、晶圆的套刻误差测量方法及晶圆的堆叠方法
JP2022141179A (ja) 2021-03-15 2022-09-29 キオクシア株式会社 半導体装置の製造方法、及び半導体装置
CN115172325B (zh) * 2021-04-01 2023-06-20 长鑫存储技术有限公司 半导体结构及其形成方法、堆叠结构

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007158078A (ja) * 2005-12-06 2007-06-21 Zycube:Kk 半導体装置とその製造方法
US20080315395A1 (en) * 2007-06-21 2008-12-25 Sung Min Kim Stacked semiconductor package and method for manufacturing the same
US20090014891A1 (en) * 2007-07-11 2009-01-15 Industrial Technology Research Institute Three-dimensional die-stacking package structure and method for manufacturing the same
TW200924058A (en) * 2007-09-11 2009-06-01 Ibm Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias
US20090209063A1 (en) * 2003-08-26 2009-08-20 Samsung Electronics Co., Ltd. Chipstack package and manufacturing method thereof
TW201044546A (en) * 2009-03-25 2010-12-16 Lsi Corp A three-dimensional electronics package

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006080337A1 (ja) 2005-01-31 2006-08-03 Nec Corporation 半導体装置およびその製造方法と、積層型半導体集積回路
US8049327B2 (en) 2009-01-05 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via with scalloped sidewalls
JP2010212297A (ja) 2009-03-06 2010-09-24 Toshiba Corp 半導体装置および半導体装置の製造方法
US8487444B2 (en) 2009-03-06 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional system-in-package architecture
JP5172751B2 (ja) 2009-03-19 2013-03-27 株式会社東芝 三次元積層型半導体集積回路の製造方法
JP2012039005A (ja) 2010-08-10 2012-02-23 Toshiba Corp 半導体装置およびその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090209063A1 (en) * 2003-08-26 2009-08-20 Samsung Electronics Co., Ltd. Chipstack package and manufacturing method thereof
JP2007158078A (ja) * 2005-12-06 2007-06-21 Zycube:Kk 半導体装置とその製造方法
US20080315395A1 (en) * 2007-06-21 2008-12-25 Sung Min Kim Stacked semiconductor package and method for manufacturing the same
US20090014891A1 (en) * 2007-07-11 2009-01-15 Industrial Technology Research Institute Three-dimensional die-stacking package structure and method for manufacturing the same
TW200924058A (en) * 2007-09-11 2009-06-01 Ibm Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias
TW201044546A (en) * 2009-03-25 2010-12-16 Lsi Corp A three-dimensional electronics package

Also Published As

Publication number Publication date
US8884396B2 (en) 2014-11-11
JP2012221998A (ja) 2012-11-12
US20120248579A1 (en) 2012-10-04
TW201241987A (en) 2012-10-16
US20120248624A1 (en) 2012-10-04

Similar Documents

Publication Publication Date Title
TWI497687B (zh) 半導體裝置及其製造方法
JP5723915B2 (ja) 貫通シリコンビアを使用する半導体実装プロセス
US8410615B2 (en) Semiconductor device and method for manufacturing the same
KR101187214B1 (ko) 본드 패드를 통과하여 연장된 비아를 갖는 마이크로전자 소자를 포함하는 적층형 마이크로전자 어셈블리
US8981558B2 (en) Semiconductor device
US20090189256A1 (en) Manufacturing process of semiconductor device and semiconductor device
WO2012011932A1 (en) Methods of forming semiconductor elements using micro-abrasive particle stream
TWI514491B (zh) 半導體基板及其製造方法
US20070267738A1 (en) Stack-type semiconductor device having cooling path on its bottom surface
JP2013247139A (ja) 半導体装置及びその製造方法
US8552534B2 (en) Laminated semiconductor substrate, semiconductor substrate, laminated chip package and method of manufacturing the same
CN115249621B (zh) 一种半导体封装结构及其制备方法
JP2006041512A (ja) マルチチップパッケージ用集積回路チップの製造方法及びその方法により形成されたウエハ及びチップ
KR101128895B1 (ko) 반도체 소자의 오버레이 버니어 및 그 제조 방법
KR101163218B1 (ko) 반도체 칩 및 그 제조방법
WO2015001662A1 (ja) 半導体装置およびその製造方法
KR20090114492A (ko) 반도체 장치 및 그 제조 방법
KR101624851B1 (ko) 내장형 재배선을 갖는 반도체 장치 및 이의 제조 방법
JP2012134526A (ja) 半導体装置
TWI806423B (zh) 半導體裝置
TWI433284B (zh) 可堆疊式封裝結構及其製造方法及半導體封裝結構
JP2011091358A (ja) 半導体基板、積層チップパッケージおよび半導体プレート並びにこれらの製造方法
KR20100069003A (ko) 적층형 반도체 패키지 및 그 제조 방법
KR20110050963A (ko) 반도체 패키지 제조방법
KR20120022193A (ko) 반도체 소자 및 그 형성 방법

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees