WO2015001662A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- WO2015001662A1 WO2015001662A1 PCT/JP2013/068511 JP2013068511W WO2015001662A1 WO 2015001662 A1 WO2015001662 A1 WO 2015001662A1 JP 2013068511 W JP2013068511 W JP 2013068511W WO 2015001662 A1 WO2015001662 A1 WO 2015001662A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 101
- 238000004519 manufacturing process Methods 0.000 title claims description 39
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- 238000000034 method Methods 0.000 claims description 44
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
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- 238000005530 etching Methods 0.000 claims description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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Definitions
- the present invention relates to a semiconductor device including a through silicon via and a method for manufacturing the same.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2007-520051
- a seed layer is formed on the side wall of a hole formed in a substrate, coated with a conductive layer, and a conductive material or non-conductive material is formed in the remaining space inside.
- a conductive via with a filler material introduced is described.
- Patent Document 2 describes a semiconductor chip provided with a first wiring pattern and a second wiring pattern for electrically connecting a through via and an external connection terminal. ing.
- the main roles of through silicon vias in semiconductor devices are signal propagation, clock supply, and power supply. Since signals are directly exchanged between semiconductor elements, it is preferable to use a wiring in a layer close to the semiconductor element (hereinafter referred to as a lower layer wiring) as a connection wiring for the silicon through electrode for signal propagation. On the other hand, since it is necessary to supply the clock and the power supply to a relatively wide range without loss, the connection wiring of the silicon through electrode for clock supply and power supply is a wiring in a layer far from the semiconductor element that can reduce the wiring resistance ( Hereinafter, it is preferable to use an upper layer wiring).
- the present invention provides a semiconductor device satisfying a low parasitic resistance and a large allowable current by forming a silicon through electrode connected to the upper layer wiring and a silicon through electrode connected to the lower layer wiring.
- the present invention first forms a first connection wiring made of lower layer wiring and a second connection wiring made of upper layer wiring on the main surface of the substrate. Then, after forming a first opening reaching the first connection wiring and a second opening reaching the second connection wiring from the back surface of the substrate through the substrate, each of the first opening and the second opening A first silicon through electrode connected to the first connection wiring and a second silicon through electrode connected to the second connection wiring are formed inside.
- a semiconductor device satisfying a low parasitic resistance and a large allowable current can be provided by forming a silicon through electrode connected to the upper layer wiring and a silicon through electrode connected to the lower layer wiring.
- FIG. 7 is a cross-sectional view of the principal part for explaining the manufacturing process of the semiconductor device according to Example 1.
- FIG. FIG. 2 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 1;
- FIG. 3 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 2;
- FIG. 4 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 3;
- FIG. 5 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 4;
- FIG. 6 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 5;
- FIG. 7 is an essential part cross-sectional view of the same place as that in FIG. 1 during the manufacturing process of the semiconductor device, following FIG. 6;
- 10 is a fragmentary cross-sectional view illustrating a manufacturing step of a semiconductor device according to Example 2.
- FIG. FIG. 9 is an essential part cross-sectional view of the same place as that in FIG. 8 during the manufacturing process of the semiconductor device, following FIG. 8;
- FIG. 10 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 9;
- FIG. 11 is a principal part cross-sectional view of the same place as in FIG.
- FIG. 12 is an essential part cross-sectional view of the same place as that in FIG. 8 during the manufacturing process of the semiconductor device, following FIG. 11;
- FIG. 13 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 12;
- FIG. 14 is an essential part cross-sectional view of the same place as that in FIG. 8 during the manufacturing process of the semiconductor device, following FIG. 13;
- FIG. 10 is an essential part cross-sectional view showing, on an enlarged scale, a part of a lower layer wiring (first connection wiring) and a first through silicon via electrode according to Example 2;
- FIG. 10 is an essential part cross-sectional view showing, on an enlarged scale, a part of a lower layer wiring (first connection wiring) and a first through silicon via electrode according to Example 2;
- FIG. 10 is an essential part cross-sectional view showing, on an enlarged scale, a part of a lower layer wiring (first connection wiring) and a first through silicon via electrode
- FIG. 10 is an enlarged plan view showing a main part of a lower layer wiring (first connection wiring) and a part of a first silicon through electrode according to Example 2;
- FIG. 10 is a graph showing a penetration probability distribution of a Kelvin resistor including a first through silicon via according to Example 2.
- 6 is a scanning electron micrograph showing a connection portion between a first through silicon via electrode and a first connection wiring according to Example 2;
- the constituent elements are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.
- the through silicon via has a role of supplying a clock and power to the entire semiconductor device in addition to signal propagation. Therefore, it is necessary to connect the connection wiring formed in the semiconductor device and the silicon through electrode to distribute the power supplied from the silicon through electrode to the entire semiconductor device.
- Patent Document 1 describes a manufacturing process in which a metal wiring is filled in an opening formed in a silicon substrate to form a silicon through electrode, and then a connection wiring connected to the silicon through electrode is formed. Further, in Patent Document 2, a first wiring pattern and a second wiring pattern are simultaneously formed on the front surface side of a semiconductor substrate by a multilayer wiring structure, and then penetrated through only the semiconductor substrate from the back surface side of the semiconductor substrate. A manufacturing process is described in which a hole is formed, and then a metal film is filled in the through hole to form a through via connected to the second wiring pattern.
- connection wiring is limited to the same wiring layer.
- connection wiring When only the lower layer wiring is used as the connection wiring, it is necessary to connect the connection wiring and the upper layer wiring through a plurality of wiring layers and connection holes, which increases the parasitic resistance and increases the power consumption. In addition, since the current density allowed by one through silicon via is limited, it is necessary to increase the number of through silicon vias.
- the silicon through electrode is once connected to the connection wiring and then connected to the semiconductor element via the multilayer wiring.
- the formation area of the multilayer wiring that can be used for other applications is originally occupied by the multilayer wiring used for connection with the connection wiring, reducing the wiring resources available for other applications, and the chip size. Increase or the number of wiring layers increases.
- the semiconductor device according to the first embodiment is a semiconductor device in which electrical connection can be taken out of the chip through the silicon through electrodes directly connected to the upper layer wiring and the lower layer wiring in the same chip.
- FIGS. 1 to 7 are cross-sectional views of relevant parts showing a method for manufacturing a semiconductor device.
- a device protection insulating film 300 made of, for example, silicon oxide is formed on the main surface of a silicon substrate 100 (planar substantially circular semiconductor thin plate called a semiconductor wafer in this stage) 100. Subsequently, using a sputtering method, a lithography method, an etching method, a CVD (Chemical Vapor Deposition) method, or the like, the metal wiring 200, 201, 202, 203, the first connection wiring 210, the second connection wiring 220, A wiring interlayer insulating film 310 is formed.
- the metal wiring 200 and the first connection wiring 210 are formed of the same wiring layer (single layer), and the metal wirings 202 and 203 and the second connection wiring 220 are formed of the same wiring layer (single layer).
- the second connection wiring 220 is formed, for example, in a rectangular region having a side of 10 ⁇ m in a plan view.
- the metal wirings 200, 201, 202, 203, the first connection wiring 210, and the second connection wiring 220 are mainly composed of, for example, copper (Cu), and the wiring interlayer insulating film 310 is composed of, for example, silicon oxide and an organic group. Silicon oxide is the main constituent material. Since copper (Cu) has a lower resistivity than aluminum (Al), it is effective as a means for reducing wiring delay.
- the silicon substrate 100 is a substrate on which a so-called pre-process has been completed, and an integrated circuit including semiconductor elements and wirings for connecting them is formed in a predetermined region of the main surface.
- the distance H between the bottom surface of the first connection wiring 210 and the bottom surface of the second connection wiring 220 is set to 2.0 ⁇ m, for example.
- the fixed substrate 130 for example, a substrate containing silicon oxide as a main component is used
- the adhesive 340 for example, a substrate that can be peeled off by ultraviolet irradiation is used.
- a resist mask is formed on the back surface of the silicon substrate 100 by using a lithography method, and then a part of the silicon substrate 100 is etched by using a dry etching method to obtain device protection insulation.
- the first through hole 400 and the second through hole 410 are formed so that the film 300 is exposed. Thereafter, the resist mask is removed.
- the first through hole 400 is laid out above the first connection wiring 210, and the second through hole 410 is positioned above the second connection wiring 220.
- infrared alignment that enables alignment with a pattern formed on the main surface side of the silicon substrate 100 is performed.
- the resist mask is formed directly on the back surface of the silicon substrate 100 here, the resist mask may be formed after an insulating material such as a silicon nitride film or a silicon oxide film is formed on the back surface of the silicon substrate 100.
- a back surface insulating film 320 made of, for example, silicon oxide is formed on the entire back surface of the silicon substrate 100 including the inner walls of the first through hole 400 and the second through hole 410. Subsequently, the entire surface is etched back by a dry etching method to remove the back surface insulating film 320 located on the bottom surfaces of the first through hole 400 and the second through hole 410, and further remove the device protection insulating film 300. Thus, the first opening 401 that exposes a part of the first connection wiring 210 is formed.
- the dry etching method having strong anisotropy is used to remove the back surface insulating film 320 and the device protection insulating film 300, the back surface insulation formed on the inner walls of the first through hole 400 and the second through hole 410 is used.
- the film 320 can be left as it is.
- the entire surface is etched back by a dry etching method, and the wiring interlayer insulating film 310 located on the bottom surface of the second through hole 410 is removed. Thereby, the second opening 411 exposing a part of the second connection wiring 220 is formed.
- the inside of each of the first opening 401 and the second opening 411 is made of copper (Cu ) Embed with film.
- the first through silicon via electrode 230 electrically connected to the first connection wiring 210 is removed by removing the excess copper (Cu) film and the plating seed film using a CMP (Chemical Mechanical Polishing) method,
- the second through silicon via electrode 240 electrically connected to the second connection wiring 220 is formed.
- the silicon substrate 100 on which the semiconductor element and the multilayer wiring are formed is peeled off from the fixed substrate 130 by being irradiated with ultraviolet rays or the like, and transferred to a dicing tape.
- the silicon device 100 is completed by separating the silicon substrate 100 on which the semiconductor elements and the multilayer wirings are formed using a dicing apparatus.
- the metal wiring 204 is formed so that the solder bump 270 and the first silicon through electrode 230 and the second silicon through electrode 240 are electrically connected using a flip chip bonder or the like.
- a semiconductor device is mounted on the chip mounting member 120 formed.
- the first through silicon via electrode 230 for signal propagation connected to the first connection wiring 210 formed of the lower layer wiring is formed, and the upper layer wiring is formed.
- a second through silicon via electrode 240 for supplying a clock and for supplying power connected to the second connection wiring 220 can be formed.
- the first connection wiring is composed of a plurality of metal wirings due to wiring width restrictions. Therefore, when the first opening reaching the first connection wiring is formed in the silicon substrate, the wiring interlayer insulating film between the adjacent metal wiring and the metal wiring is etched, and the reliability of the wiring is lowered. There is. Therefore, the second embodiment provides a technique that can prevent the reliability of the wiring from being lowered even if the wiring interlayer insulating film between the adjacent metal wirings is etched.
- the semiconductor device according to the second embodiment is a semiconductor device in which electrical connection can be taken out of the chip through the silicon through electrodes directly connected to the upper layer wiring and the lower layer wiring in the same chip.
- the difference from the first embodiment described above is that the first connection wiring is composed of two layers of metal wiring.
- FIGS. 8 to 14 are cross-sectional views of relevant parts showing a method for manufacturing a semiconductor device.
- a device protection insulating film 300 made of, for example, silicon oxide is formed on the main surface of a silicon substrate 100 (planar substantially circular semiconductor thin plate called a semiconductor wafer in this stage) 100.
- the metal wiring 200, 201, 202, 203, the first connection wiring (A) 210, the first connection wiring (B) 211, and the like using a sputtering method, a lithography method, an etching method, a CVD method, and the like.
- the second connection wiring 220 and the wiring interlayer insulating film 310 are formed.
- the metal wiring 200 and the first connection wiring (A) 210 are formed by the same wiring layer (single layer), and the metal wiring 201 and the first connection wiring (B) 211 are formed by the same wiring layer (single layer).
- the metal wirings 202 and 203 and the second connection wiring 220 are formed by the same wiring layer (single layer).
- the first connection wiring (A) 210 and the first connection wiring (B) 211 are composed of a plurality of wirings formed apart from each other as shown in FIGS. 15 and 16 described later.
- the second connection wiring 220 is formed, for example, in a rectangular region having a side of 10 ⁇ m in a plan view.
- the metal wirings 200, 201, 202, 203, the first connection wiring (A) 210, the first connection wiring (B) 211, and the second connection wiring 220 are mainly composed of, for example, copper (Cu) and have a wiring interlayer.
- the insulating film 310 is mainly composed of, for example, silicon oxide and organic group-containing silicon oxide. Since copper (Cu) has a lower resistivity than aluminum (Al), it is effective as a means for reducing wiring delay.
- the silicon substrate 100 is a substrate on which a so-called pre-process has been completed, and an integrated circuit including semiconductor elements and wirings for connecting them is formed in a predetermined region of the main surface.
- the distance H between the bottom surface of the first connection wiring (A) 210 and the bottom surface of the second connection wiring 220 is set to 2.0 ⁇ m, for example.
- the fixed substrate 130 for example, a substrate containing silicon oxide as a main component is used
- the adhesive 340 for example, a substrate that can be peeled off by ultraviolet irradiation is used.
- a resist mask is formed on the back surface of the silicon substrate 100 using a lithography method, and then a part of the silicon substrate 100 is etched using a dry etching method to obtain device protection insulation.
- the first through hole 400 and the second through hole 410 are formed so that the film 300 is exposed. Thereafter, the resist mask is removed.
- the first through hole 400 is laid out above the first connection wiring (A) 210, and the second through hole 410 is positioned above the second connection wiring 220.
- infrared alignment that enables alignment with a pattern formed on the main surface side of the silicon substrate 100 is performed.
- the resist mask is formed directly on the back surface of the silicon substrate 100 here, the resist mask may be formed after an insulating material such as a silicon nitride film or a silicon oxide film is formed on the back surface of the silicon substrate 100.
- a back insulating film 320 made of, for example, silicon oxide is formed on the entire back surface of the silicon substrate 100 including the inner walls of the first through hole 400 and the second through hole 410. Subsequently, the entire surface is etched back by a dry etching method to remove the back surface insulating film 320 located on the bottom surfaces of the first through hole 400 and the second through hole 410, and further remove the device protection insulating film 300. Thus, the first opening 401 exposing a part of the first connection wiring (A) 210 and a part of the second connection wiring (B) 211 is formed.
- the first connection wiring (A) 210 is composed of a plurality of metal wirings spaced apart from each other. For this reason, the wiring interlayer insulating film 310 between the adjacent metal wirings constituting the first connection wiring (A) 210 is etched by over-etching when the first opening 401 is formed. However, as shown in FIG. 16 to be described later, in the plan view, a plurality of second connection wirings (B) 211 are configured so as to alternate with a plurality of metal wirings configuring the first connection wiring (A) 210. Metal wiring is arranged.
- the back surface insulating film formed on the inner walls of the first through hole 400 and the second through hole 410 320 can be left with almost the same film thickness.
- the entire surface is etched back by a dry etching method, and the wiring interlayer insulating film 310 located on the bottom surface of the second through hole 410 is removed. Thereby, the second opening 411 exposing a part of the second connection wiring 220 is formed.
- the inside of each of the first opening 401 and the second opening 411 is made of copper (Cu ) Embed with film.
- the CMP method the excess copper (Cu) film and the plating seed film were removed, and the first connection wiring (A) 210 and the first connection wiring (B) 211 were electrically connected.
- the first silicon through electrode 230 and the second silicon through electrode 240 electrically connected to the second connection wiring 220 are formed.
- the silicon substrate 100 on which the semiconductor element and the multilayer wiring are formed is peeled off from the fixed substrate 130 by being irradiated with ultraviolet rays or the like, and transferred to a dicing tape.
- the silicon device 100 is completed by separating the silicon substrate 100 on which the semiconductor elements and the multilayer wirings are formed using a dicing apparatus.
- the metal wiring 204 is formed so that the solder bump 270 and the first silicon through electrode 230 and the second silicon through electrode 240 are electrically connected using a flip chip bonder or the like.
- a semiconductor device is mounted on the chip mounting member 120 formed.
- FIG. 15 is an enlarged cross-sectional view of a main portion showing a part of the first connection wiring (A), the first connection wiring (B), and the first through silicon via.
- the first connection wiring (A) includes metal wirings 250, 251, 252, and 253 which are the same wiring layer. Each of the metal wirings 250, 251, 252, and 253 has a wiring width defined by W1, and the adjacent metal wirings 250, 251, 252, and 253 are separated by an interval defined by S1.
- the first connection wiring (B) includes metal wirings 260, 261, and 262 that are the same wiring layer. Each of the metal wirings 260, 261, and 262 has a wiring width defined by W2, and the adjacent metal wirings 260, 261, and 262 are separated by an interval defined by S2.
- FIG. 16 is an enlarged plan view of a main part of the first connection wiring (A), the first connection wiring (B), and a part of the first through silicon via.
- FIG. 15 described above corresponds to the cross section indicated by the line AA in FIG.
- Each of the metal wirings 250, 251, 252, and 253 constituting the first connection wiring (A) has a wiring width W1 and extends in the Y direction.
- Each of the metal wirings 250, 251, 252, and 253 is formed so as to be spaced apart from each other in the X direction orthogonal to the Y direction with a wiring interval S1.
- each of the metal wirings 260, 261, and 262 constituting the first connection wiring (B) has a wiring width W2 and is formed to extend in the Y direction.
- Each of the metal wirings 260, 261, and 262 is formed so as to be spaced apart from each other in the X direction with a wiring interval S2.
- the center of the width in the X direction of each of the metal wirings 260, 261, 262 and the center of the gap in the X direction of each of the metal wirings 250, 251, 252, 253 are made to coincide with each other.
- the wiring width W2 of each of the metal wirings 260, 261, and 262 is made larger than the wiring interval S1 of each of 251, 252, and 253.
- the center of the width in the X direction of each of the metal wirings 251 and 252 and the center of the gap in the X direction of each of the metal wirings 260, 261 and 262 are matched to each other.
- the wiring width W1 of each of the metal wirings 251 and 252 is made larger than the interval S2.
- the inside of the first silicon through electrode 230 has the metal wirings 250, 251, 252, 253 constituting the first connection wiring (A) or the metal wirings 260, 261 constituting the first connection wiring (B). , 262. That is, in plan view, the region where the first silicon through electrode 230 is formed is completely covered with the first connection wiring (A) and the first connection wiring (B).
- the wiring width W1 of each of the metal wirings 250, 251, 252, and 253 and the wiring width W2 of each of the metal wirings 260, 261, and 262 are, for example, 0.
- the wiring interval S1 of each of the metal wirings 250, 251, 252, and 253 and the wiring interval S2 of the metal wirings 260, 261, and 262 are set to 0.2 ⁇ m, for example.
- the metal wirings 250, 251, 252, and 253 constituting the first connection wiring (A) and the metal wirings 260, 261, and 262 constituting the first connection wiring (B) are the connection holes 520, They are electrically connected via 521, 522, 523, 524, 525.
- Each of the connection holes 520, 521, 522, 523, 524, and 525 constitutes the first connection wiring (B) and the metal wirings 250, 251, 252, and 253 constituting the first connection wiring (A) in plan view.
- the metal wirings 260, 261, and 262 are laid out in an overlapping area.
- connection holes 520 that connect the metal wirings 250, 251, 252, and 253 constituting the first connection wiring (A) and the metal wirings 260, 261, and 262 constituting the first connection wiring (B). 521, 522, 523, 524, and 525 are provided outside the first silicon through electrode 230.
- the circuit wiring 280 for connecting the first through silicon via 230 and the semiconductor element formed on the silicon substrate is formed of the same wiring layer as the first connection wiring (A). For example, it is integrally formed with the metal wiring 253 constituting the first connection wiring (A).
- the series resistance of the first through silicon via, the first connection wiring (A), and the first connection wiring (B) was evaluated by the Kelvin method.
- FIG. 17 is a graph showing a cumulative probability distribution (Cumulative-Probability) of Kelvin resistance (Kelvin-Resistance).
- connection portion of the first through silicon via, the first connection wiring (A), and the first connection wiring (B) was evaluated using a scanning electron microscope.
- FIG. 18 is a scanning electron micrograph showing connection portions of the first through silicon via, the first connection wiring (A), and the first connection wiring (B).
- the thickness of the first connection wiring (A) 210 is reduced by dry etching, but still remains. Further, due to the shape of the first through silicon via 230, it exists in the gap between the adjacent metal wirings constituting the first connection wiring (A) 210 (the region indicated by the wiring spacing S1 in FIGS. 15 and 16 described above). It can be seen that the wiring interlayer insulating film 310 that has been removed is removed by dry etching until the first connection wiring (B) 211 is reached. However, the first connection wiring (B) 211 remains almost complete, and the etching does not reach the metal wirings 205 and 206 in the upper layer of the first connection wiring (B) 211. Therefore, the metal wirings 205 and 206 in the upper layer of the first connection wiring (B) 211 can be used as normal circuit wiring.
- the first signal propagation for connection to the first connection wiring (A) 210 and the first connection wiring (B) 211 made of the lower layer wiring is provided on the main surface of the silicon substrate 100.
- the silicon through electrode 230 is formed, and the second silicon through electrode 240 for clock supply and power supply connected to the second connection wiring 220 made of the upper layer wiring can be formed.
- first connection wiring (A) 210 and the first connection wiring (B) 211 are electrically connected to the first through silicon via 230 to form the first connection wiring (A) 210.
- the metal wiring forming the first connection wiring (B) 211 and the metal wiring constituting the first connection wiring (B) 211 were arranged so as to completely cover the region where the first through silicon via 230 was formed. Thereby, the fall of the reliability of wiring can be suppressed.
- Example 2 the wiring width W1 of the metal wiring configuring the first connection wiring (A) and the wiring width W2 of the metal wiring configuring the first connection wiring (B) are 0.8 ⁇ m, and the first connection wiring (A).
- the wiring interval S1 between the adjacent metal wirings constituting the above and the wiring spacing S2 between the adjacent metal wirings constituting the first connection wiring (B) are set to 0.2 ⁇ m, but the wiring widths W1, W2 and the wiring spacings S1, S2 are set. Is not limited to this.
- the wiring widths W1 and W2 and the wiring intervals S1 and S2 are the layout of the wiring layer in which the metal wiring constituting the first connection wiring (A) and the metal wiring constituting the first connection wiring (B) are formed. You can decide according to the rules. As long as the layout rule allows, the wiring widths W1 and W2 are desirably as wide as possible, and the wiring intervals S1 and S2 are desirably as narrow as possible.
- the number of metal wirings constituting the first connection wiring (A) and the metal wiring constituting the first connection wiring (B) is also based on the wiring widths W1 and W2 and the wiring spacings S1 and S2 in the plan view. The number necessary for completely covering one through silicon via may be laid out.
- the width (or depth) of each of the first connection wiring (A) and the first connection wiring (B) is set to a dimension obtained by adding an alignment margin to the width (or depth) of the first through silicon via. It is desirable.
- Example 2 the center of the wiring width W1 of the metal wiring constituting the first connection wiring (A) and the center of the wiring interval S2 of the adjacent metal wirings constituting the first connection wiring (B) are matched. In addition, the center of the wiring width W2 of the metal wiring constituting the first connection wiring (B) and the center of the wiring interval S1 of the adjacent metal wirings constituting the first connection wiring (A) are matched. Although it has been laid out, it is not necessary to match it.
- the pattern formed by the logical sum of the wiring width W1 of the metal wiring that constitutes the first connection wiring (A) and the wiring width W2 of the metal wiring that constitutes the first connection wiring (B) is the first in a plan view. It is only necessary to completely cover the through silicon via. However, since the metal wiring constituting the first connection wiring (A) and the metal wiring constituting the first connection wiring (B) need to be electrically connected through the connection holes, respectively, They must overlap each other with the necessary alignment margin.
- connection hole that connects the metal wiring constituting the first connection wiring (A) and the metal wiring constituting the first connection wiring (B) is formed outside the first silicon through electrode in plan view. Although it has been laid out, it can also be laid out inside the first through silicon via in a plan view. In that case, since the total number of connection holes can be increased, parasitic resistance can be reduced. However, when forming the first opening for embedding the first silicon through electrode, if the metal wiring constituting the first connection wiring (A) is completely etched, the wiring interlayer insulating film has a protruding shape. Therefore, when the conductive material is embedded in the first opening, the reliability of the wiring may be lowered.
- Example 2 the first connection wiring (A) and the first connection wiring (B) were electrically connected to the first through silicon via in two wiring layers. However, three or more wiring layers are used. It is also possible. Moreover, although 2.0 ⁇ m was exemplified as the distance between the bottom surface of the first connection wiring (A) made of the lower layer wiring and the bottom surface of the second connection wiring made of the upper layer wiring (distance H shown in FIG. 8 described above), It is also possible to use different distance wiring as required.
- the etching direction If the relationship that the total thickness of the metal wirings constituting the first connection wiring (A) is larger than H / ⁇ is satisfied, the number of wiring layers used for the first connection wiring (A) and the first connection wiring The distance between the bottom surface of (A) and the bottom surface of the second connection wiring can be changed.
- Example 2 in order to connect the first through silicon via to the semiconductor element, the circuit wiring is connected to the metal wiring located on the outermost side of the first connection wiring (A). However, the first connection wiring (A) It is also possible to connect to other metal wirings that constitute the first connection wiring (B).
- wiring resources can be used more effectively by connecting to the first connection wiring (A) close to the silicon substrate.
- the second silicon through electrode including the alignment margin in one wiring layer is included. It is desirable to completely coat.
- the second connection is performed in accordance with, for example, the layout of the first connection wiring (A) and the first connection wiring (B) in the second embodiment.
- Each metal wiring of each wiring layer constituting the wiring is laid out. That is, the pattern formed by the logical sum of the wiring widths of the respective metal wirings of each wiring layer constituting the second connection wiring in the region where the second through silicon via is formed using two or more wiring layers. In the plan view, the second through silicon via may be completely covered.
- Example 2 a square was used as the shape of the first through silicon via in plan view, but other shapes may be used. For example, a rectangle, a hexagon, an octagon, a circle, or the like may be used. Further, the first silicon through electrode and the second silicon through electrode do not necessarily have the same shape. For example, since the second through silicon via electrode directly connected to the second connection wiring performs clock supply and power supply, the width (diameter) can be increased in order to reduce resistance.
- ⁇ Modification 8> In order to improve the flatness of the metal wiring, an electrically floating dummy metal is often formed in a region between adjacent metal wirings. However, since these dummy metals become an etching obstacle when the first silicon through electrode and the second silicon through electrode are etched, a dummy metal is formed in a region where the first silicon through electrode and the second silicon through electrode are formed. It is desirable not to.
- the silicon substrate on which the semiconductor element is formed is temporarily fixed to the fixed substrate made of silicon oxide using an adhesive, but the present invention is not limited to this.
- the fixed substrate may be a silicon substrate, and a permanent fixing resin such as polyimide may be used as an adhesive.
- one semiconductor device is stacked on the chip mounting member with the main surface on which the semiconductor element is formed facing upward (Face-up state).
- other stacked configurations can also be used. It is.
- the number of stacked layers may be two or more, and may be stacked with the main surface on which the semiconductor element is formed facing down (Face-down state) as necessary.
- First connection wiring First connection wiring
- First connection wiring (A) 211 First connection wiring (B) 220 second connection wiring 230 first silicon through electrode 240 second silicon through electrode 250, 251, 252, 253 metal wiring 260, 261, 262 metal wiring 270 solder bump 280 circuit wiring 300 device protection insulating film 310 wiring interlayer insulating film 320 Back surface insulating film 340
Abstract
Description
まず、実施例1によるシリコン貫通電極について説明する前に、従来技術によるシリコン貫通電極について説明する。
実施例1による半導体装置は、同一チップ内の上層配線および下層配線にそれぞれ直接接続されたシリコン貫通電極を通して、チップ外に電気的な接続を取り出し可能な半導体装置である。
実施例2による半導体装置の製造方法を図8~図14を参照しながら工程順に説明する。図8~図14は、半導体装置の製造方法を示す要部断面図である。
図15は、第1接続配線(A)、第1接続配線(B)、および第1シリコン貫通電極の一部を拡大して示す要部断面図である。
実施例2では、第1接続配線(A)を構成する金属配線の配線幅W1および第1接続配線(B)を構成する金属配線の配線幅W2を0.8μmとし、第1接続配線(A)を構成する隣り合う金属配線の配線間隔S1および第1接続配線(B)を構成する隣り合う金属配線の配線間隔S2を0.2μmとしたが、配線幅W1,W2および配線間隔S1,S2はこれに限定されるものではない。
実施例2では、第1接続配線(A)を構成する金属配線の配線幅W1の中心と、第1接続配線(B)を構成する隣り合う金属配線の配線間隔S2の中心とが一致するように、また、第1接続配線(B)を構成する金属配線の配線幅W2の中心と、第1接続配線(A)を構成する隣り合う金属配線の配線間隔S1の中心とが一致するようにレイアウトしたが、必ずしも一致させる必要はない。
実施例2では、第1接続配線(A)を構成する金属配線と第1接続配線(B)を構成する金属配線とを接続する接続孔は、平面視において、第1シリコン貫通電極の外側にレイアウトしたが、平面視において、第1シリコン貫通電極の内側にレイアウトすることも可能である。その場合、接続孔の合計数を増やすことができるので、寄生抵抗の低減が可能である。しかし、第1シリコン貫通電極を埋め込む第1開口部を形成する際に、第1接続配線(A)を構成する金属配線が完全にエッチングされてしまった場合には、配線層間絶縁膜に突起状の段差が形成されるので、第1開口部に導電性材料を埋め込むときに、配線の信頼度の低下を引き起こすおそれがある。
実施例2では、第1接続配線(A)と第1接続配線(B)の2層の配線層で第1シリコン貫通電極との電気的接続を行ったが、3層以上の配線層を使うことも可能である。また、下層配線からなる第1接続配線(A)の底面と、上層配線からなる第2接続配線の底面との距離として、2.0μmを例示したが(前述の図8に示す距離H)、必要に応じて異なる距離の配線を使用することも可能である。
実施例2では、第1シリコン貫通電極を半導体素子に接続するために、回路配線を、第1接続配線(A)の最も外側に位置する金属配線に接続したが、第1接続配線(A)を構成する他の金属配線に接続してもよく、また、第1接続配線(B)を構成する金属配線に接続することも可能である。
実施例1,2では、第2接続配線として、一辺が10μmの四角形の単層の金属配線を用いたが、この形態に限定されるものではない。
実施例2では、第1シリコン貫通電極の平面視における形状として、正方形を用いたが、これ以外の形状でもよい。例えば長方形、六角形、八角形、または円形等を用いてもよい。また、第1シリコン貫通電極と第2シリコン貫通電極とは必ずしも同一の形状である必要はない。例えば第2接続配線に直接接続される第2シリコン貫通電極は、クロック供給および電源供給を行うため、低抵抗化のために、その幅(径)を大きくすることも可能である。
金属配線の平坦性を向上させるために、隣り合う金属配線間の領域には電気的に浮遊状態のダミーメタルが形成される場合が多い。しかし、これらのダミーメタルは第1シリコン貫通電極および第2シリコン貫通電極のエッチング時にエッチング障害物となるため、第1シリコン貫通電極および第2シリコン貫通電極を形成する領域には、ダミーメタルを形成しないことが望ましい。
実施例1,2では、半導体素子が形成されたシリコン基板を酸化シリコンからなる固定基板に接着剤を用いて仮固定しているが、これに限定されるものではない。例えば固定基板はシリコン基板でもよく、また、接着剤としてポリイミド等の永久固定用樹脂を用いることも可能である。
実施例1,2では、チップ搭載部材上に、半導体素子が形成された主面を上に向けた状態(Face-up状態)で半導体装置を1層積層したが、他の積層形態も利用可能である。積層数は2層以上でもよく、また、必要に応じて半導体素子が形成された主面を下に向けた状態(Face-down状態)で積層してもよい。
120 チップ搭載部材
130 固定基板
200,201,202,203,204,205,206 金属配線
210 第1接続配線、第1接続配線(A)
211 第1接続配線(B)
220 第2接続配線
230 第1シリコン貫通電極
240 第2シリコン貫通電極
250,251,252,253 金属配線
260,261,262 金属配線
270 はんだバンプ
280 回路配線
300 デバイス保護絶縁膜
310 配線層間絶縁膜
320 裏面絶縁膜
340 接着剤
400,401 第1開口部
400A 第1貫通孔
410A 第2貫通孔
410,411 第2開口部
520,521,522,523,524,525 接続孔
H 距離
S1,S2 配線間隔
W1,W2 配線幅
Claims (15)
- 第1面、および前記第1面と反対側の第2面を有する基板と、
前記基板の前記第1面に形成された半導体素子と、
前記半導体素子を被覆する保護絶縁膜と、
前記保護絶縁膜上に形成された複数の配線層からなる多層配線と、
前記多層配線の一部の配線層により構成された第1接続配線と、
前記多層配線の他の一部の配線層により構成された第2接続配線と、
を備え、
前記第2接続配線を構成する最下層の配線層は、前記第1接続配線を構成する最下層の配線層よりも上層の配線層により形成され、
平面視における第1領域に前記基板を貫通して形成された第1貫通電極が、前記第1接続配線に接続され、
平面視における前記第1領域とは異なる第2領域に前記基板を貫通して形成された第2貫通電極が、前記第2接続配線に接続され、
平面視において、前記第1接続配線は前記第1貫通電極を内包し、
平面視において、前記第2接続配線は前記第2貫通電極を内包する、半導体装置。 - 請求項1記載の半導体装置において、
前記基板の前記第1面から前記第2接続配線を構成する最下層の配線層までの距離は、前記基板の前記第1面から前記第1接続配線を構成する最下層の配線層までの距離よりも長い、半導体装置。 - 請求項1記載の半導体装置において、
前記第1接続配線は、絶縁膜を介して配置された2層以上の配線層から構成され、
前記第1接続配線を構成する前記2層以上の配線層のそれぞれは、互いに離間して配置された複数の金属配線から構成される、半導体装置。 - 請求項1記載の半導体装置において、
前記第1接続配線は、絶縁膜を介して配置された下層に位置する複数の第1金属配線と、上層に位置する複数の第2金属配線とから構成され、
前記複数の第1金属配線は、第1方向に互いに離間して、前記第1方向と直交する第2方向に延在し、
前記複数の第2金属配線は、前記第1方向に互いに離間して、前記第2方向に延在し、
平面視において、前記第1金属配線は、前記第1方向に隣り合う前記第2金属配線の間隙を内包し、
平面視において、前記第2金属配線は、前記第1方向に隣り合う前記第1金属配線の間隙を内包する、半導体装置。 - 請求項1記載の半導体装置において、
前記第1接続配線を構成する最下層の配線層の下面と、前記第2接続配線を構成する最下層の配線層の下面との距離をHとし、
前記第1接続配線と前記第2接続配線との間に形成された絶縁膜に対する前記第1接続配線を構成する配線層のエッチング選択比をαとした場合、
前記第1接続配線を構成する配線層の厚みの合計が、H/αよりも大きい、半導体装置。 - 請求項5記載の半導体装置において、
前記絶縁膜は酸化シリコンおよび有機含有酸化シリコンを主たる構成材料とし、
前記第1接続配線を構成する配線層は銅を主成分とする、半導体装置。 - 請求項1記載の半導体装置において、
前記第1接続配線、前記第1貫通電極、および前記第2貫通電極は銅を含む、半導体装置。 - 請求項1記載の半導体装置において、
前記第1貫通電極は、信号の伝搬に用いられ、
前記第2貫通電極は、クロックまたは電源の供給に用いられる、半導体装置。 - (a)第1面、および前記第1面と反対側の第2面を有する基板を準備する工程、
(b)前記基板の前記第1面に半導体素子を形成した後、前記半導体素子を被覆する保護絶縁膜を形成する工程、
(c)前記保護絶縁膜上に複数の配線層からなる多層配線を形成し、
前記多層配線の一部の配線層を用いて第1接続配線を形成し、
前記多層配線の他の一部の配線層を用いて、前記第1接続配線を構成する最下層の配線層よりも上層の配線層を最下層とする第2接続配線を形成する工程、
(d)前記(c)工程の後、前記第2面から、前記基板の厚さを薄く加工する工程、
(e)前記(d)工程の後、前記第1接続配線を前記基板に投影した領域に内包される第1領域に、前記基板の前記第2面側から前記基板を貫通する第1貫通孔を形成し、
前記第2接続配線を前記基板に投影した領域に内包される第2領域に、前記基板の前記第2面側から前記基板を貫通する第2貫通孔を形成する工程、
(f)前記(e)工程の後、前記第1貫通孔および前記第2貫通孔の内壁を被覆するように、前記基板の前記第2面上の全面に裏面絶縁膜を形成する工程、
(g)前記(f)工程の後、前記第1貫通孔の底面および前記第2貫通孔の底面を同時にエッチングして、前記第1接続配線に達する第1開口部を形成する工程、
(h)前記(g)工程の後、前記第2貫通孔の底面をエッチングして、前記第2接続配線に達する第2開口部を形成する工程、
(i)前記(h)工程の後、前記第1開口部の内部に第1貫通電極を形成し、前記第2開口部の内部に第2貫通電極を形成する工程、
を含む、半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記第1接続配線は、絶縁膜を介して配置された2層以上の配線層から構成され、
前記第1接続配線を構成する前記2層以上の配線層のそれぞれは、互いに離間して配置された複数の金属配線から構成される、半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記第1接続配線は、絶縁膜を介して配置された下層に位置する複数の第1金属配線と、上層に位置する複数の第2金属配線とから構成され、
前記複数の第1金属配線は、第1方向に互いに離間して、前記第1方向と直交する第2方向に延在し、
前記複数の第2金属配線は、前記第1方向に互いに離間して、前記第2方向に延在し、
平面視において、前記第1金属配線は、前記第1方向に隣り合う前記第2金属配線の間隙を内包し、
平面視において、前記第2金属配線は、前記第1方向に隣り合う前記第1金属配線の間隙を内包する、半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記第1接続配線を構成する最下層の配線層の下面と、前記第2接続配線を構成する最下層の配線層の下面との距離をHとし、
前記第1接続配線と前記第2接続配線との間に形成された絶縁膜に対する前記第1接続配線を構成する配線層のエッチング選択比をαとした場合、
前記第1接続配線を構成する配線層の厚みの合計が、H/αよりも大きい、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
前記絶縁膜は酸化シリコンおよび有機含有酸化シリコンを主たる構成材料とし、
前記第1接続配線を構成する配線層は銅を主成分とする、半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記第1接続配線、前記第1貫通電極、および前記第2貫通電極は銅を含む、半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記第1貫通電極は、信号の伝搬に用いられ、
前記第2貫通電極は、クロックまたは電源の供給に用いられる、半導体装置の製造方法。
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JPH0922910A (ja) * | 1995-07-07 | 1997-01-21 | Nec Corp | 半導体装置 |
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JP2003528466A (ja) * | 2000-03-22 | 2003-09-24 | ジプトロニクス・インコーポレイテッド | 三次元デバイスの一体化方法および一体化されたデバイス |
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JPH0922910A (ja) * | 1995-07-07 | 1997-01-21 | Nec Corp | 半導体装置 |
JP2000260873A (ja) * | 1999-01-08 | 2000-09-22 | Nec Corp | 半導体装置のコンタクト又は配線の形成方法 |
JP2003528466A (ja) * | 2000-03-22 | 2003-09-24 | ジプトロニクス・インコーポレイテッド | 三次元デバイスの一体化方法および一体化されたデバイス |
JP2012243953A (ja) * | 2011-05-19 | 2012-12-10 | Panasonic Corp | 半導体装置及びその製造方法並びに積層型半導体装置 |
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JP7143608B2 (ja) | 2018-03-27 | 2022-09-29 | 富士通株式会社 | 半導体装置及び半導体装置の製造方法 |
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