JP5548173B2 - 半導体基板及びその製造方法 - Google Patents
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- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
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- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/83895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
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- H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/83896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
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- Condensed Matter Physics & Semiconductors (AREA)
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- Mechanical Treatment Of Semiconductor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
2 被接合半導体ウェハ
11 配線層
12 絶縁膜
31 エッジカット領域
32 配線層厚暫減領域(第5の領域)
33 配線層厚一定領域(第4の領域)
34 段差加工領域
35 非接合領域
40 ノッチ
41 ノッチの先端
50 半導体ウェハの中央部
51 半導体ウェハの外周部
60 第1の領域
61 第2の領域
Claims (8)
- 半導体基板と、
前記半導体基板上に形成された配線層と、を備え、
前記半導体基板は、前記配線層に覆われた第1の領域と、前記半導体基板の外周部に形成され、且つ、前記配線層に覆われていない第2の領域とを備え、
前記半導体基板の前記第2の領域に絶縁膜が形成され、
前記配線層の上面と前記絶縁膜の上面とは略同一の面であり、
前記半導体基板の前記外周部には、段差が形成された段差加工領域を備える、
ことを特徴とする半導体ウェハ。 - 前記配線層の上面と前記絶縁膜の上面との高さは同じである、
ことを特徴とする請求項1に記載の半導体ウェハ。 - 半導体基板と、
前記半導体基板上に形成された配線層と、を備え、
前記半導体基板は、前記配線層に覆われた第1の領域と、前記半導体基板の外周部に形成され、且つ、前記配線層に覆われていない第2の領域とを備え、
前記第1の領域の配線層において、前記第1の領域から前記第2の領域に向かって層厚が減少する第3の領域を備え、
前記第3の領域の前記配線層上に絶縁膜が形成され、
前記第1の領域における前記配線層の上面と前記絶縁膜の上面とは、略同一の面であり、
前記半導体基板の前記外周部には、段差が形成された段差加工領域を備える、
ことを特徴とする半導体ウェハ。 - 半導体基板と、
前記半導体基板上に形成された配線層と、を備え、
前記配線層は、前記配線層の上面がほぼ平坦であり、且つ、その高さが略同一であるような第4の領域と、前記第4の領域から前記半導体基板の周辺部に向かって、前記配線層の上面の高さが減少する第5の領域と、を備え、
前記第5の領域の前記配線層上に絶縁膜が形成され、
前記第4の領域における前記配線層の上面と前記第5の領域の前記絶縁膜の上面とは、略同一の面であり、
前記半導体基板の外周部には、段差が形成された段差加工領域を備える、
ことを特徴とする半導体ウェハ。 - 半導体基板と、
前記半導体基板上に形成された配線層と、を備え、
前記配線層は、前記配線層の上面がほぼ平坦であり、その高さが略同一である第4の領域と、前記第4の領域から前記半導体基板の周辺部に向かって、前記配線層の上面の高さが減少する第5の領域と、を備え、
前記第4の領域及び前記第5の領域の前記配線層上に絶縁膜が形成され、前記絶縁膜の上面がほぼ平坦であり、且つ、その高さが略同一であり、
前記半導体基板の外周部には、段差が形成された段差加工領域を備える、
ことを特徴とする半導体ウェハ。 - 前記絶縁膜は、酸化物もしくは窒化物からなることを特徴とする請求項1から5のいずれか1つに記載の半導体ウェハ。
- 請求項1から6のいずれか1つに記載の半導体ウェハと、
前記半導体ウェハにおいて略同一である前記配線層の上面と前記絶縁膜の上面とに接するように接合された被接合半導体ウェハとを、
備えることを特徴とする積層構造体。 - 半導体基板の中央部に第1の領域に配線層を形成し、
前記半導体基板の外周部に位置し、且つ、前記配線層に覆われていない第2の領域に絶縁膜を形成し、
前記絶縁膜を研磨することにより、前記配線層の上面と略同一の面であるような前記絶縁膜の上面を形成し、
前記絶縁膜を形成後、前記半導体基板の前記外周部の最外周部分に段差加工を行う、
ことを特徴とする半導体ウェハの製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2011189390A JP5548173B2 (ja) | 2011-08-31 | 2011-08-31 | 半導体基板及びその製造方法 |
US13/365,516 US8766407B2 (en) | 2011-08-31 | 2012-02-03 | Semiconductor wafer and laminate structure including the same |
TW101106734A TWI464781B (zh) | 2011-08-31 | 2012-03-01 | A semiconductor wafer and a laminated structure having the same |
CN201210055411.1A CN102969336B (zh) | 2011-08-31 | 2012-03-05 | 半导体晶片及具备该半导体晶片的叠层构造体 |
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JP2011189390A JP5548173B2 (ja) | 2011-08-31 | 2011-08-31 | 半導体基板及びその製造方法 |
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JP5548173B2 true JP5548173B2 (ja) | 2014-07-16 |
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JP (1) | JP5548173B2 (ja) |
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TW (1) | TWI464781B (ja) |
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CN110544436B (zh) * | 2014-09-12 | 2021-12-07 | 株式会社半导体能源研究所 | 显示装置 |
CN105070668B (zh) * | 2015-08-06 | 2019-03-12 | 武汉新芯集成电路制造有限公司 | 一种晶圆级芯片封装方法 |
KR102468793B1 (ko) * | 2016-01-08 | 2022-11-18 | 삼성전자주식회사 | 반도체 웨이퍼, 반도체 구조체 및 이를 제조하는 방법 |
JP2021048303A (ja) * | 2019-09-19 | 2021-03-25 | キオクシア株式会社 | 半導体装置 |
CN111739793A (zh) * | 2020-08-06 | 2020-10-02 | 中芯集成电路制造(绍兴)有限公司 | 晶圆的键合方法及键合结构 |
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JPH05226305A (ja) | 1992-02-10 | 1993-09-03 | Hitachi Ltd | 張合せウェハの製造方法 |
JPH06177351A (ja) * | 1992-12-02 | 1994-06-24 | Toshiba Corp | 半導体装置の製造方法 |
JP3935977B2 (ja) * | 1995-05-16 | 2007-06-27 | Sumco Techxiv株式会社 | ノッチ付き半導体ウェーハ |
JPH11204452A (ja) * | 1998-01-13 | 1999-07-30 | Mitsubishi Electric Corp | 半導体基板の処理方法および半導体基板 |
JP3496508B2 (ja) | 1998-03-02 | 2004-02-16 | 三菱住友シリコン株式会社 | 張り合わせシリコンウェーハおよびその製造方法 |
JP3558624B2 (ja) * | 2002-06-14 | 2004-08-25 | 沖電気工業株式会社 | 半導体素子の製造方法 |
JP2009099875A (ja) * | 2007-10-19 | 2009-05-07 | Sony Corp | 半導体装置の製造方法 |
JP2010239001A (ja) * | 2009-03-31 | 2010-10-21 | Sony Corp | 容量素子とその製造方法および固体撮像装置と撮像装置 |
JP2011258740A (ja) * | 2010-06-09 | 2011-12-22 | Toshiba Corp | 半導体装置、カメラモジュールおよび半導体装置の製造方法 |
JP2012039005A (ja) | 2010-08-10 | 2012-02-23 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2012174937A (ja) * | 2011-02-22 | 2012-09-10 | Sony Corp | 半導体装置、半導体装置の製造方法、半導体ウエハの貼り合わせ方法及び電子機器 |
JP2012221998A (ja) | 2011-04-04 | 2012-11-12 | Toshiba Corp | 半導体装置ならびにその製造方法 |
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CN102969336B (zh) | 2015-05-20 |
JP2013051354A (ja) | 2013-03-14 |
US20130049210A1 (en) | 2013-02-28 |
TW201310501A (zh) | 2013-03-01 |
CN102969336A (zh) | 2013-03-13 |
US8766407B2 (en) | 2014-07-01 |
TWI464781B (zh) | 2014-12-11 |
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