CN107017219B - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- CN107017219B CN107017219B CN201610848902.XA CN201610848902A CN107017219B CN 107017219 B CN107017219 B CN 107017219B CN 201610848902 A CN201610848902 A CN 201610848902A CN 107017219 B CN107017219 B CN 107017219B
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- element forming
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- bump electrodes
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Abstract
本发明提供能够防止基板的周边部的破裂、缺口的损伤,并且,防止突起电极的损伤的半导体装置及其制造方法。半导体装置(10)在半导体晶圆(12)的主面(12A)的中央部(14)具备元件形成区域(20)。在元件形成区域(20)配设有突起电极(44)。另一方面,在半导体晶圆(12)的主面(12A)的周边部(16)配设有虚拟突起电极(44D)。虚拟突起电极(44D)与元件形成区域(20)和周边部(16)的边界部分的三角形(60)重复地配设。虚拟突起电极(44D)在半导体晶圆(12)的背面的背面研磨处理中,防止周边部的破裂、缺口等损伤。
Description
技术领域
本发明涉及半导体装置及其制造方法。
背景技术
专利文献1公开了晶圆级芯片尺寸封装(WL-CSP:Wafer Level Chip SizePackage)的半导体装置的制造方法。在该半导体装置的制造方法中,最初,形成在有源面(表面)上排列了凸块电极的IC晶圆,在有源面上在IC晶圆的周边部分粘贴支承部件。并且,以覆盖凸块电极的方式在支承部件上粘贴背面研磨用保护带。在由保护带保护有源面的状态下通过背面研磨工序磨削IC晶圆的无源面(背面),IC晶圆的厚度变薄。若背面研磨工序结束,则剥离保护带以及支承部件。
根据这样的半导体装置的制造方法,在周边部分被支承部件机械地支承的状态下磨削IC晶圆的无源面,所以不容易产生IC晶圆的周边部分的破裂、缺口。
专利文献1:日本特开2004-288725公报
在上述半导体装置的制造方法中,在IC晶圆的有源面上形成了凸块电极之后,在IC晶圆的周边部分粘贴支承部件。在粘贴支承部件时,存在支承部件与凸块电极接触,而给予凸块电极损伤的可能性。另外,在上述半导体装置的制造方法中,除了保护带的粘贴工序之外还需要支承部件的粘贴工序,所以制造工序数目增加。因此,存在改善的余地。
发明内容
本发明考虑上述事实,提供能够防止基板的周边部的破裂、缺口的损伤且防止突起电极的损伤的半导体装置。
另外,本发明提供能够防止基板背面的磨削所引起的基板的破裂、缺口的损伤,并使制造工序数目减少,能够实现基板的轻薄化的半导体装置的制造方法。
本发明的实施方式所涉及的半导体装置具备:
基板,在主面的中央部,在第一方向配设n个矩形平面状的第一元件形成区域,并且,与上述第一元件形成区域在与第一方向交叉的第二方向上邻接来在第一方向配设n+m个与上述第一元件形成区域相同形状的第二元件形成区域;
突起电极,在上述第一元件形成区域上以及上述第二元件形成区域上分别形成多个突起电极;以及
虚拟突起电极,在上述主面的周边部,与三角形重复地形成多个虚拟突起电极,由与该周边部成为边界的上述第一元件形成区域的第一边和经由一角与该第一边邻接且与该周边部成为边界的上述第二元件形成区域的第二边确定上述三角形。
另外,本发明的实施方式所涉及的半导体装置的制造方法具备:
准备基板,在上述基板主面的中央部,在第一方向形成有n个矩形平面状的第一元件形成区域,并与上述第一元件形成区域在与第一方向交叉的第二方向上邻接来在第一方向形成n+m个与上述第一元件形成区域相同形状的第二元件形成区域;
在上述第一元件形成区域上以及上述第二元件形成区域上分别形成多个突起电极,并且在上述主面的周边部,与三角形重复地形成多个虚拟突起电极的突起电极形成工序,由与该周边部成为边界的上述第一元件形成区域的第一边和经由一角与该第一边邻接且与该周边部成为边界的上述第二元件形成区域的第二边确定上述三角形;
在上述主面的整个区域粘贴覆盖上述突起电极以及上述虚拟突起电极的保护带的保护带粘贴工序;以及
在粘贴了上述保护带的状态下,磨削上述基板的与上述主面对置的背面,使该基板的厚度变薄的薄膜化工序。
根据本发明,能够提供能够防止基板的周边部的破裂、缺口的损伤且防止突起电极的损伤的半导体装置。
另外,根据本发明,能够提供能够防止基板背面的磨削所引起的基板的破裂、缺口的损伤,并使制造工序数目减少,能够实现基板的轻薄化的半导体装置的制造方法。
附图说明
图1是本发明的第一实施方式所涉及的半导体装置的主要部分剖视图(在图3的A-A线切割的剖视图)。
图2是图1所示的半导体装置的整体的俯视图。
图3是图2所示的半导体装置的主要部分的放大俯视图(在图2附加符号B并由虚线包围的区域的放大俯视图)。
图4是说明第一实施方式所涉及的半导体装置的制造方法的与图1对应的第一工序剖视图。
图5是第二工序剖视图。
图6是第三工序剖视图。
图7是第四工序剖视图。
图8是第五工序剖视图。
图9是第六工序剖视图。
图10是第七工序剖视图。
图11是第八工序剖视图。
图12是第九工序剖视图。
图13是第十一工序剖视图。
图14是第十二工序剖视图。
图15是背面研磨处理时的第一实施方式所涉及的半导体装置的主要部分的放大工序剖视图。
图16是说明在第一实施方式所涉及的半导体装置的制造方法中,通过背面研磨处理形成的切削痕与虚拟突起电极的配置位置的关系的与图2对应的半导体装置的示意俯视图。
图17是背面研磨处理时的比较例所涉及的半导体装置的主要部分的放大工序剖视图。
图18是表示在第一实施方式所涉及的半导体装置的制造方法中,背面研磨处理时的基板的厚度与损伤产生率的关系的图。
图19是本发明的第二实施方式所涉及的半导体装置的与图3对应的主要部分的放大俯视图。
符号说明:10…半导体装置,12…半导体晶圆(基板),12A…主面,12B…背面,12D…磨削痕,14…中央部,16…周边部,20…元件形成区域,20A…第一边,20B…第二边,20C…一角,42…外部电极焊盘,42D…虚拟电极焊盘,44…突起电极,44D…虚拟突起电极,50…保护带,52…背面研磨轮,54…磨削磨石,60…三角形。
具体实施方式
以下,参照附图对本发明的实施方式所涉及的半导体装置及其制造方法进行说明。此外,在全部的实施方式中,对实质上具有同等功能的构成元件附加同一符号,并省略重复的说明。
[第一实施方式]
使用图1~图18,对本发明的第一实施方式所涉及的半导体装置及其制造方法进行说明。这里,第一实施方式所涉及的半导体装置及其制造方法以将本发明应用于具有晶圆级芯片尺寸封装结构的半导体装置及其制造方法为例进行说明。
(半导体装置的结构)
如图1~图3所示,本实施方式所涉及的半导体装置10具备作为基板的半导体晶圆12。在本实施方式中,半导体晶圆12使用单晶硅晶圆。如图2所示,半导体晶圆12在俯视时形成为圆形形状。而且,在半导体晶圆12的周边的一部分(图2下侧)形成有在制造、输送时作为定位使用的定向平面12C。半导体晶圆12在后述的背面研磨处理前例如设定为600μm~650μm的厚度。在背面研磨处理后,半导体晶圆12变薄至200μm以下,优选变薄至150μm以下的厚度。
在半导体晶圆12的主面12A的中央部14在第一方向以及与第一方向交叉的第二方向配设有多个重复具有成为图案的基本的相同的矩形平面状的元件形成区域20。在元件形成区域20安装有包含省略图示的逻辑电路以及存储电路的至少一个集成电路。另外,集成电路通过包含开关元件、电阻、电容以及布线而构建。多个元件形成区域20作为通过切割处理(切割加工)切断半导体晶圆12并芯片化的半导体装置10形成,或者将半导体晶圆12保持原样而作为晶圆级的半导体装置10形成。这里,第一方向是图2以及图3所示的X方向,例如是行方向。另外,第二方向是与X方向正交的Y方向,例如是列方向。
如图2所示,在半导体晶圆12的中央部14的成为最上段的第一段,作为第一元件形成区域,在第一方向配设有n个元件形成区域20(1,1)~元件形成区域20(1,n)。这里,“n”是除了零之外的自然数,虽然并不限定于该数,但在本实施方式中设定为“6”。在与该第一元件形成区域在第二方向邻接的下一段的第二段,作为第二元件形成区域,在第一方向配设有n+m个元件形成区域20(2,1)~元件形成区域20(2,n+m)。这里,“m”是除了零之外的自然数,在本实施方式中设定为“2”。在“m”的值是“2”、“4”等偶数的情况下,相对于元件形成区域20(1,1)~元件形成区域20(1,n)的第一方向的排列间距,元件形成区域20(2,1)~元件形成区域20(2,n+m)的同一方向的排列间距相同。在“m”的值为“1”、“3”等奇数的情况下,排列间距偏移二分之一。
在与第二元件形成区域在第二方向邻接的第三段,在第一方向配设有n+m+o个元件形成区域20(3,1)~元件形成区域20(3,n+m+o)。这里,“o”是除了零之外的自然数,在本实施方式中设定为“2”。在与第三元件形成区域在第二方向邻接的第四段配设有n+m+o+p个元件形成区域20(4,1)~元件形成区域20(4,n+m+o+p)。这里,“p”是除了零之外的自然数,在本实施方式中设定为“2”。
第一段的元件形成区域20与第二段的元件形成区域20的排列关系由于仅在下一段在第一方向增加m个或者o个元件形成区域20,所以和第二段的元件形成区域20与第三段的元件形成区域20的排列关系相同。另外,第二段的元件形成区域20与第三段的元件形成区域20的排列关系由于仅在下一段在第一方向增加o个或者p个元件形成区域20,所以和第三段的元件形成区域20与第四段的元件形成区域20的排列关系相同。因此,第二段的元件形成区域20与第三段的元件形成区域20的排列关系以及第三段的元件形成区域20与第四段的元件形成区域20的排列关系和第一段的元件形成区域20与第二段的元件形成区域20的排列关系相同。换言之,能够将上段的元件形成区域20视为第一元件形成区域,将下段的元件形成区域视为第二元件形成区域。
在与第四段的元件形成区域20在第二方向邻接的第五段~第九段,配设有n+m+o+p个元件形成区域20(5,1)~元件形成区域20(5,n+m+o+p)到n+m+o+p个元件形成区域20(9,1)~元件形成区域20(9,n+m+o+p)。第五段~第九段的元件形成区域20的第一方向的排列数设定为与第四段的元件形成区域20的第一方向的排列数相同。
在与第九段的元件形成区域20在第二方向邻接的第十段,配设有n+m+o个元件形成区域20(10,1)~元件形成区域20(10,n+m+o)。在与第十段的元件形成区域20在第二方向邻接的第十一段,配设有n+m个元件形成区域20(11,1)~元件形成区域20(11,n+m)。而且,在与第十一段的元件形成区域20在第二方向邻接的成为最终段的第十二段,配设有n个元件形成区域20(12,1)~元件形成区域20(12,n)。第九段的元件形成区域20~第十二段的元件形成区域20的排列关系相对于第一段的元件形成区域20~第四段的元件形成区域20的排列关系,在与第二方向相反的方向(从图2的下方朝向上方)相同。
在这样构成的半导体装置10中,能够在圆形形状的半导体晶圆12的主面12A较多地排列矩形形状的元件形成区域20。因此,能够有效地利用半导体晶圆12的主面12A。
如图1所示,在半导体晶圆12的主面12A上且在各个元件形成区域20在集成电路上经由层间绝缘层30配设有多个电极32。电极32是所谓的焊盘,并经由布线与省略图示的集成电路电连接。电极32例如以铝(Al)合金层为主体形成。在电极32上经由表面保护层34以及层间绝缘层36配设有再布线38。再布线38通过省略符号的连接孔(参照图5的符号36H)与电极32电连接。另外,在本实施方式中,如图7所示,再布线38作为依次层叠了最下层的基底金属层38A、中间层的防氧化层38B、最上层的金属层38C的各个的复合膜形成。作为基底金属层38A,例如使用钛(Ti)层。作为防氧化层38B,例如使用铜(Cu)层或者Cu合金层。而且,作为金属层38C,例如使用Cu层或者Cu合金层。这里,作为材料的Cu的比电阻值比Al的比电阻值低。
返回到图1,在半导体晶圆12的主面12A上的整个区域,形成有覆盖再布线38上的密封树脂层40。在密封树脂层40埋设有作为最终布线层的柱状的外部电极焊盘42,上述外部电极焊盘42在再布线38上与该再布线38电连接。外部电极焊盘42例如由Cu层或者Cu合金层形成。
而且,在外部电极焊盘42上按照每个外部电极焊盘42形成多个与该外部电极焊盘42电连接的突起电极(凸块电极)44。这里,在本实施方式所涉及的半导体装置10中,各个元件形成区域20作为排列了球状的突起电极44的球栅阵列(Ball Grid Array)封装形成。如图3所示,突起电极44在第一方向以及第二方向规则地排列。在突起电极44正下设有外部电极焊盘42,所以外部电极焊盘42与突起电极44的排列相同地在第一方向以及第二方向规则地排列。通过从电极32的再布线38的配置来布局这样的规则的突起电极44以及外部电极焊盘42的排列。在本实施方式中,作为突起电极44使用焊料凸块电极。此外,作为突起电极44,能够使用Cu凸块电极、销子状的凸块电极。
如图1以及图3所示,在半导体晶圆12的主面12A的周边部16配设有多个虚拟突起电极44D。如图3所示,虚拟突起电极44D在周边部16,与由与周边部16成为边界的元件形成区域20(1,n)的第一边(右边)20A、和经由一角20C与第一边20A邻接,并与周边部16成为边界的元件形成区域20(2,n+m)的第二边(上边)20B确定的三角形60重复地配设。为了帮助理解,方便地对三角形60附加影线进行描绘。由于元件形成区域20为正方形,第一边20A以及第二边20B的长度相等地设定,并且,一角20C的内角为90°,所以本实施方式的三角形60为等腰直角三角形。这里,“重复”以包含在俯视时,虚拟突起电极44D内包于三角形60的轮廓内的情况以及虚拟突起电极44D的一部分与三角形60的斜边20D重合的情况的意味使用。
如图1所示,虚拟突起电极44D与元件形成区域20的突起电极44为同一结构且由相同材料形成。虚拟突起电极44D的排列间隔设定为与突起电极44的排列间隔相同。虽然在后述的半导体装置10的制造方法中进行说明,但虚拟突起电极44D通过与突起电极44的制造工序相同的制造工序形成(参照图12)。另外,在虚拟突起电极44D正下设有虚拟电极焊盘42D以及虚拟再布线38D。虚拟电极焊盘42D与外部电极焊盘42为同一结构、相同材料,并且由相同的制造工序形成(参照图10)。同样地,虚拟再布线38D与再布线38为同一结构、相同材料,并且由相同的制造工序形成(参照图6~图8)。
在本实施方式中,如图3所示,在周边部16中在三角形60的外侧区域配设有虚拟电极焊盘42D,该虚拟电极焊盘42D的表面露出,但不形成虚拟突起电极44D。这是为了通过减少作为电意义上的构成元件不需要的虚拟突起电极44D的配设数目,高效地配设虚拟突起电极44D,并减少产品成本以及制造成本。
返回到图3,虚拟突起电极44D在周边部16,也与由与周边部16成为边界的元件形成区域20(2,n+m)的第一边(右边)20A、和经由一角20C与第一边20A邻接并与周边部16成为边界的元件形成区域20(3,n+m+o)的第二边(上边)20B确定的三角形60重复地配设。虽然省略图示,但虚拟突起电极44D在周边部16,也与由与周边部16成为边界的元件形成区域20(3,n+m+o)的第一边(右边)20A、和经由一角20C与第一边20A邻接并与周边部16成为边界的元件形成区域20(4,n+m+o+p)的第二边(上边)20B形成的三角形60重复地配设。
虽然省略详细的图示,但如图2所示,虚拟突起电极44D在周边部16中与由元件形成区域20(1,1)~元件形成区域20(4,1)、元件形成区域20(9,1)~元件形成区域20(12,1)的各个形成的三角形60重复地配设。同样地,虚拟突起电极44D在周边部16中,也与由元件形成区域20(9,n+m+o+p)~元件形成区域20(12,n)的各个形成的三角形60重复地配设。
此外,例如在第一段的元件形成区域20的排列间距与第二段的元件形成区域20的排列间距在第一方向偏移半间距的情况下(“m”为奇数的情况下),三角形60为第二边20B的长度相对于第一边20A的长度为一半的直角三角形。而且,与该三角形60重复地在周边部16配设多个虚拟突起电极44D。另外,在元件形成区域20为长方形平面状的情况下,也同样地,配设虚拟突起电极44D。
(半导体装置的制造方法)
本实施方式所涉及的半导体装置10的制造方法如以下那样。首先最初准备具有例如600μm~650μm的厚度的半导体晶圆12(参照图4)。在半导体晶圆12的主面12A,在中央部14在第一方向以及第二方向上规则地形成有多个省略图示的矩形平面状的元件形成区域20。接下来,在主面12A上,在包含中央部14以及周边部16的整个区域形成层间绝缘层30。层间绝缘层30例如由氧化硅膜、氮化硅膜的任意一个的单层膜或者双方的复合膜形成。
如图4所示,在中央部14的元件形成区域20中,形成电极32以及省略图示的布线。电极32例如通过溅射法形成,以Al合金层为主体形成。另外,电极32使用光刻技术以及蚀刻技术图案化。接着,在主面12A上的整个区域,依次形成覆盖电极32的表面保护层34、层间绝缘层36。表面保护层34例如通过等离子体化学气相析出(CVD)法形成,由氮化硅膜形成。另外,层间绝缘膜36例如通过旋涂法形成,由感光性树脂膜形成。如图5所示,有选择地去除电极32上的层间绝缘层36,形成露出电极32的表面的连接孔36H。连接孔36H的形成使用光刻技术以及蚀刻技术。
如图6所示,在层间绝缘层36上的整个区域依次层叠基底金属层38A、防氧化层38B的各个。基底金属层38A和防氧化层38B例如使用溅射法形成。基底金属层38A通过连接孔36H与电极32电连接。
接着,在防氧化层38B上形成具有再布线38的图案的掩模46(参照图7)。作为掩模46例如使用抗蚀剂膜,抗蚀剂膜通过光刻技术形成。这里,掩模46的省略符号的开口图案形成在元件形成区域20上,并且也形成在与周边部16的上述的三角形60重复的区域(虚拟再布线38D的形成区域)。使用将防氧化层38B作为电极的电镀法,如图7所示,在从掩模46露出的防氧化层38B上形成金属层38C。若形成金属层38C,则在元件形成区域20中,形成层叠了基底金属层38A、防氧化层38B以及金属层38C的再布线38。并且,通过与再布线38的制造工序相同的制造工序,形成与再布线38具有相同结构的虚拟再布线38D。其后,如图8所示,除去掩模46。此外,在该制造工序的阶段,多个再布线38间、多个虚拟再布线38D间、以及再布线38与虚拟再布线38D之间通过基底金属层38A以及防氧化层38B处于电连接的状态。
接着,在主面12A上的整个区域,形成覆盖再布线38以及虚拟再布线38D的掩模48(参照图9)。在掩模48形成有成为突起电极44的形成区域的与再布线38上以及虚拟再布线38D上贯通的开口部48H。作为掩模48例如使用抗蚀剂膜,抗蚀剂膜通过光刻技术形成。使用将再布线38(具体而言是金属层38C)作为电极的电镀法,如图9所示,在从掩模48的开口部48H露出的再布线38上形成柱状的外部电极焊盘42。在与该外部电极焊盘42的制造工序相同的制造工序中,在从掩模48的开口部48H露出的虚拟再布线38D上形成柱状的虚拟电极焊盘42D。其后,如图10所示,除去掩模48。
接下来,在主面12A上的整个区域,形成覆盖外部电极焊盘42上以及虚拟电极焊盘42D上且与它们的膜厚相比较厚的膜厚的密封树脂层40(参照图11)。密封树脂层40保护与外部电极焊盘42相比下层的再布线38、电极32以及集成电路。如图11所示,在密封树脂层40从表面除去厚度的一部分,露出外部电极焊盘42以及虚拟电极焊盘42D的表面。密封树脂层40的除去例如使用利用了磨床的磨削加工、化学机械抛光(CMP)法。由此,埋设到密封树脂层40的外部电极焊盘42以及虚拟电极焊盘42D由相同的制造工序形成。
如图12所示,在元件形成区域20中在外部电极焊盘42上形成与该外部电极焊盘42电连接的突起电极44。在与该突起电极44的制造工序相同的制造工序中,与周边部16的图3所示的三角形60重复地在虚拟电极焊盘42D上形成与该虚拟电极焊盘42D连接的虚拟突起电极44D。此外,在本实施方式所涉及的半导体装置10的制造方法中,不与周边部16的三角形60重复的区域的虚拟电极焊盘42D使表面露出,但不在该虚拟电极焊盘42D上形成虚拟突起电极44D。
如图13所示,在半导体晶圆12的主面12A上的整个区域粘贴覆盖突起电极44以及虚拟突起电极44D的背面研磨用保护带50。保护带50在对半导体晶圆12的背面12B(参照图1)实施背面研磨处理将半导体晶圆12的厚度较薄地加工时,保护突起电极44以及与其相比下层的外部电极焊盘42、再布线38、电极32、集成电路等。虽然省略详细的剖面结构,但在本实施方式中,保护带50为具有成为基材的带状的树脂制薄膜、和形成在该树脂制薄膜的突起电极44侧的表面的紫外线(UV)固化型粘合层的双层结构。这里,作为保护带50的树脂制薄膜,能够实用地使用具有透过紫外线的功能的例如具有180μm~220μm的厚度的聚烯烃树脂薄膜。另外,作为粘合层,能够实用地使用具有例如110μm~150μm的厚度的丙烯酸树脂层。
接下来,如图15所示,使半导体晶圆12反转,在粘贴了保护带50的状态下,使用背面研磨轮52在半导体晶圆12的背面12B进行背面研磨处理。由此,背面12B被磨削,半导体晶圆12的厚度在本实施方式中薄至200μm以下,优选薄至150μm左右。
这里,在背面研磨处理中,背面研磨轮52的磨削磨石54与半导体晶圆12的背面12B接触,且磨削磨石54相对于半导体晶圆12相对地旋转。由此,背面12B被磨削,半导体晶圆12的厚度变薄。此时,如图2、图3、图15以及图16所示,在半导体晶圆12的背面12B形成有向半导体晶圆12的旋转方向突出并从半导体晶圆12的中心向周边描绘圆弧状的许多的磨削痕(锯痕)12D。图2、图3以及图16示出从主面12A侧观察到的半导体晶圆12,但为了方便,投影在背里面12B形成的磨削痕12D在主面12A描绘。另外,在图2、图3中,为了使理解变得容易而示出图16所示的磨削痕(锯痕)12D的一条。
本发明者通过专心研究发现以下的事实。在如图17所示的比较例所涉及的半导体装置中,将半导体晶圆12的主面12A的中央部14与周边部16的边界(例如相当于图3所示的第一边20A)作为分界,在中央部14连续地配置有突起电极44,在周边部16不配置突起电极44。边界即是中央部14的配置在最靠周边部16侧的元件形成区域20与周边部16的分界,并且,也是最外侧的切割线。在沿边界排列的最靠周边部16侧的多个突起电极44的位置与沿边界延伸的磨削痕12D在半导体晶圆12的厚度方向一致的图3以及图16所示的区域A1~A4中,半导体晶圆12容易产生破裂、缺口等损伤。这是因为,如图17所示,在背面研磨处理中,从磨削磨石54受到的负荷F所引起的保护带50的厚度方向的伸缩量根据突起电极44的有无而不同。换言之,相对于配置了突起电极44的中央部14,在未配置突起电极44的周边部16的保护带50的厚度方向的伸缩量较大。因此,负荷F所引起的半导体晶圆12的周边部16的挠曲量与中央部14的挠曲量相比较大,由于该挠曲量的不同而应力集中在边界部分。
因此,在本实施方式所涉及的半导体装置10及其制造方法中,如图2、图3、图13、图15以及图16所示,在经由成为边界的第一边20A与元件形成区域20邻接的周边部16形成虚拟突起电极44D。特别是,在本实施方式中,例如与由元件形成区域20(1,n)的第一边20A和在第二方向上邻接并在第一方向上偏移规定排列间距的元件形成区域20(2,n+m)的第二边20B形成的三角形60重复地形成虚拟突起电极44D。
如图15所示,在与磨削痕12D重合的区域中,与元件形成区域20的突起电极44连续地在周边部16形成并且排列虚拟突起电极44D。换言之,从磨削磨石54受到的负荷F所引起的保护带50的厚度方向的伸缩量在元件形成区域20和周边部16相等,半导体晶圆12的周边部16的挠曲量(刚性)变小,所以能够抑制边界部分的应力的产生。因此,在半导体晶圆12的主面12A的周边部16,不产生破裂、缺口等损伤。
图18示出背面研磨处理后的半导体晶圆12的厚度与半导体晶圆12的周边部16的破裂、缺口等损伤的产生率的关系。横轴是半导体晶圆12的背面研磨处理后的厚度[μm]。纵轴是半导体晶圆12的周边部16产生的损伤产生率[%]。如图18所示,背面研磨处理后的半导体晶圆12的厚度从200μm开始损伤产生率急剧增加。在厚度为200μm时的损伤产生率为0.6%~0.7%。而且,若厚度达到150μm,则损伤产生率达到20%附近。因此,本实施方式所涉及的基板的制造方法在通过背面研磨处理,而半导体晶圆12的厚度在200μm以下的情况下,特别是在150μm以下的情况下有效。
返回到制造方法,再次使半导体晶圆12反转,并对保护带50照射紫外线,降低保护带50的粘合层的粘合力。然后,如图14所示,从半导体晶圆12的主面12A剥离保护带50。若这一系列的制造工序结束,则由图1所示的轻薄化后的半导体晶圆12构建的半导体装置10完成。
其后,半导体装置10作为具有晶圆级芯片尺寸封装结构的半导体装置使用。另外,虽然省略图示以及说明,但其后,对半导体装置10进行切割处理,按照每个元件形成区域20进行切割完成芯片状的半导体装置。
(本实施方式的作用以及效果)
如图1~图3所示,本实施方式所涉及的半导体装置10在半导体晶圆12的主面12A的周边部16,具备多个虚拟突起电极44D。若进行详细说明,则虚拟突起电极44D与图2以及图3所方便地描绘示出的三角形60重复地配设。三角形60的一个由与周边部16成为边界的元件形成区域20(1,n)的第一边20A、和经由一角20C与第一边20A邻接并与周边部16成为边界的元件形成区域20(2,n+m)的第二边20B确定。而且,同样地,也与由元件形成区域20(n+m)~元件形成区域20(4,n+m+o+p)以及元件形成区域20(9,n+m+o+p)~元件形成区域20(12,n)确定的三角形60重复地配设虚拟突起电极44D。并且,在由元件形成区域20(1,1)~元件形成区域20(4,1)以及元件形成区域20(9,1)~元件形成区域20(12,1)确定的三角形60也配设虚拟突起电极44D。
这里,如图15以及图16所示,虚拟突起电极44D至少配设在沿在背面研磨处理中形成在半导体晶圆12的背面12B的磨削痕12D的延伸方向的周边部16。由于相对于元件形成区域20的突起电极44在周边部16配设虚拟突起电极44D,所以相对于从背面研磨轮52受到的负荷F保护带50的伸缩率在元件形成区域20以及周边部16双方相等。因此,在背面研磨处理中,能够使半导体晶圆12的周边部16的挠曲量减少,所以能够使在半导体晶圆12的中央部14与周边部16的边界部分产生的应力减少。另一方面,不需要在半导体晶圆12的周边部16另外粘贴用于加强的支承部件,所以能够消除支承部件的粘贴时的与突起电极44的接触的重要因素。由此,能够提供能够防止背面研磨处理时的半导体晶圆12的周边部16的破裂、缺口等损伤,并且,能够防止突起电极44的损伤的、本实施方式所涉及的半导体装置10。
此外,在本实施方式所涉及的半导体装置10,在其制造方法中,包括作为以下的阶段的中间生成物的结构。图12所示的在半导体晶圆12的周边部16形成虚拟突起电极44D的阶段、图13所示的粘贴保护带50的阶段、图15所示的进行背面研磨处理的阶段、以及图14所示的剥离保护带50的阶段。除此之外,还有图1所示的剥离了保护带50之后的阶段。这里,在作为背面研磨处理后的中间生成物的半导体装置10,在半导体晶圆12的背面12B,形成图15以及图16所示的磨削痕12D。
另外,在本实施方式所涉及的半导体装置10中,如图1所示,在周边部16的虚拟突起电极44D下配设与该虚拟突起电极44D连接的虚拟电极焊盘42D。虚拟电极焊盘42D由与突起电极44下的外部电极焊盘42相同的结构形成。这里,虚拟电极焊盘42D与虚拟突起电极44D的粘合力例如比密封树脂层40与虚拟突起电极44D的粘合力强。因此,能够稳固地固定虚拟突起电极44D。例如,在图14所示的剥离保护带50的工序中,能够防止虚拟突起电极44D的脱落。
并且,在本实施方式所涉及的半导体装置10中,如图3所示,在半导体晶圆12的主面12A的周边部16,与三角形60重复地配设虚拟突起电极44D。由此,能够防止半导体晶圆12的周边部16的损伤,并抑制突起电极材料的消耗,所以能够高效地配设虚拟突起电极44D,并减少产品成本。此外,作为半导体装置10的制造方法,能够减少制造成本。
而且,在本实施方式所涉及的半导体装置10中,如图3所示,在半导体晶圆12的主面12A的周边部16,与三角形60重复地配设虚拟突起电极44D。因此,不需要对每个元件形成区域20的排列研究沿边界排列的最靠周边部16侧的多个突起电极44的位置与沿边界延伸的磨削痕12D在半导体晶圆12的厚度方向一致的区域A1~A4。由此,即使切削痕12D与突起电极44一致也能够防止半导体晶圆12的周边部16的损伤,并且,能够减少研究虚拟突起电极44D的配置时的设计工时。
另外,在本实施方式所涉及的半导体装置10中,如图3所示,在半导体晶圆12的主面12A的周边部16,在不与三角形60重复的区域配设虚拟电极焊盘42D。因此,能够不变更虚拟电极焊盘42D的配设形状,而与三角形60重复地简单地配设虚拟突起电极44D。例如,在本实施方式所涉及的半导体装置10的制造方法中,不需要变更图9所示的形成虚拟电极焊盘42D的掩模48的图案。
并且,在本实施方式所涉及的半导体装置10中,如图1所示,配设于元件形成区域20的突起电极44与元件形成区域20的集成电路,具体而言与元件电连接。另一方面,配设于周边部16的虚拟突起电极44D不与元件电连接。因此,不需要使虚拟突起电极44D具有电的功能,所以能够比较自由地配设虚拟突起电极44D。
另外,在本实施方式所涉及的半导体装置10的制造方法中,如图12所示,在周边部16形成虚拟突起电极44D的工序是与在元件形成区域20上形成突起电极44的工序相同的制造工序。因此,与分别独立地形成的情况相比,能够减少半导体装置10的制造工序数目。由此,在半导体装置10的制造方法中,能够防止半导体晶圆12的里面12B的磨削所引起的半导体晶圆12的周边部16的破裂、缺口的损伤,并使制造工序数目减少,能够实现半导体晶圆12的轻薄化。
并且,在本实施方式所涉及的半导体装置10的制造方法中,如图8以及图9所示,形成虚拟再布线38D、虚拟电极焊盘42D的各个的工序是与形成再布线38、外部电极焊盘42的各个的工序相同的制造工序。由此,能够进一步减少半导体装置10的制造工序数目。
[第二实施方式]
使用图19,对本发明的第二实施方式所涉及的半导体装置10及其制造方法进行说明。
如图19所示,在本实施方式所涉及的半导体装置10中,在半导体晶圆12的主面12A的周边部16,在不与方便地示出的三角形60重复的区域不配设虚拟电极焊盘42D。在该区域,露出密封树脂层40(参照图1)的表面。此外,在本实施方式中,虚拟电极焊盘42D下的虚拟再布线38D(参照图1)既可以配设,也可以不配设。虚拟电极焊盘42D以外的构成与第一实施方式所涉及的半导体装置10及其制造方法的构成相同。
(本实施方式的作用以及效果)
在本实施方式所涉及的半导体装置10以及其制造方法中,能够得到与通过前述的第一实施方式的半导体装置10以及其制造方法得到的作用效果相同的作用效果。
另外,本实施方式的半导体装置10及其制造方法中,能够减少虚拟电极焊盘42D的电极材料,所以能够进一步减少产品成本以及制造成本。
[其它的实施方式]
本发明并不限定于上述实施方式。例如,在上述实施方式中,作为基板使用了半导体晶圆,但本发明也可以使用化合物半导体基板、树脂基板、玻璃基板等作为基板。
Claims (4)
1.一种半导体装置,其特征在于,具备:
基板,在主面的中央部,在第一方向配设n个矩形平面状的第一元件形成区域,并且,在第一方向配设n+m个与上述第一元件形成区域相同形状的第二元件形成区域,上述第二元件形成区域与上述第一元件形成区域在与第一方向交叉的第二方向上邻接;
突起电极,在上述第一元件形成区域上以及上述第二元件形成区域上分别形成多个突起电极;以及
虚拟突起电极,在上述主面的周边部,与三角形区域重复地形成多个虚拟突起电极,上述三角形区域由与该周边部成为边界的上述第一元件形成区域的第一边和经由一角与该第一边邻接且与该周边部成为边界的上述第二元件形成区域的第二边确定,
在上述第一元件形成区域以及上述第二元件形成区域,分别在上述突起电极下配设多个与该突起电极电连接的外部电极焊盘,
在上述周边部,在上述虚拟突起电极下配设多个与该虚拟突起电极连接的虚拟电极焊盘,
在上述周边部,在不与上述三角形区域重复的区域,配设不连接上述虚拟突起电极的上述虚拟电极焊盘。
2.根据权利要求1所述的半导体装置,其特征在于,
在上述基板的与上述主面对置的背面,形成沿上述第一边或者上述第二边延伸的磨削痕。
3.根据权利要求1或2所述的半导体装置,其特征在于,
上述突起电极与形成在上述第一元件形成区域或者上述第二元件形成区域的元件电连接,
上述虚拟突起电极未与上述元件电连接。
4.一种半导体装置的制造方法,其特征在于,具备:
准备基板,在上述基板的主面的中央部,在第一方向形成有n个矩形平面状的第一元件形成区域,并在第一方向形成n+m个与上述第一元件形成区域相同形状的第二元件形成区域,上述第二元件形成区域与上述第一元件形成区域在与第一方向交叉的第二方向上邻接;
在上述第一元件形成区域上以及上述第二元件形成区域上分别形成多个突起电极,并且在上述主面的周边部,与三角形区域重复地形成多个虚拟突起电极的突起电极形成工序,上述三角形区域由与该周边部成为边界的上述第一元件形成区域的第一边和经由一角与该第一边邻接且与该周边部成为边界的上述第二元件形成区域的第二边确定;
在上述主面的整个区域粘贴覆盖上述突起电极以及上述虚拟突起电极的保护带的保护带粘贴工序;以及
在粘贴了上述保护带的状态下,磨削上述基板的与上述主面对置的背面,使该基板的厚度变薄的薄膜化工序,
在上述第一元件形成区域以及上述第二元件形成区域,分别在上述突起电极下配设多个与该突起电极电连接的外部电极焊盘,
在上述周边部,在上述虚拟突起电极下配设多个与该虚拟突起电极连接的虚拟电极焊盘,
在上述周边部,在不与上述三角形区域重复的区域,配设不连接上述虚拟突起电极的上述虚拟电极焊盘。
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