JP2017069277A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2017069277A JP2017069277A JP2015190200A JP2015190200A JP2017069277A JP 2017069277 A JP2017069277 A JP 2017069277A JP 2015190200 A JP2015190200 A JP 2015190200A JP 2015190200 A JP2015190200 A JP 2015190200A JP 2017069277 A JP2017069277 A JP 2017069277A
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- element formation
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Abstract
【解決手段】半導体装置10は、半導体ウェーハ12の主面12Aの中央部14に素子形成領域20を備えている。素子形成領域20には突起電極44が配設されている。一方、半導体ウェーハ12の主面12Aの周辺部16にはダミー突起電極44Dが配設されている。ダミー突起電極44Dは、素子形成領域20と周辺部16との境界部分の三角形60に重複して配設されている。ダミー突起電極44Dは、半導体ウェーハ12の裏面のバックグラインド処理において、周辺部の割れ、欠け等の損傷を防止する。
【選択図】図3
Description
また、本発明は、基板裏面の研削による基板の割れや欠けの損傷を防止しつつ、製造工程数を減少させることができ、基板の薄型化を実現することができる半導体装置の製造方法を提供することにある。
主面の中央部において、矩形平面状の第1素子形成領域が第1方向にn個配設され、かつ、第1素子形成領域に対して第1方向と交差する第2方向に隣接して第1素子形成領域と同一形状の第2素子形成領域が第1方向にn+m個配設された基板と、
第1素子形成領域上及び第2素子形成領域上に各々複数形成された突起電極と、
主面の周辺部において、周辺部と境界をなす第1素子形成領域の第1辺と、第1辺に1角を介して隣接し、周辺部と境界をなす第2素子形成領域の第2辺とにより確定される三角形に重複して複数形成されたダミー突起電極と、
を備えている。
基板主面の中央部において、第1方向にn個の矩形平面状の第1素子形成領域と、第1素子形成領域に対して第1方向と交差する第2方向に隣接して第1方向にn+m個の第1素子形成領域と同一形状の第2素子形成領域とを形成する工程と、
第1素子形成領域上及び第2素子形成領域上に各々複数の突起電極を形成すると共に、主面の周辺部において、周辺部と境界をなす第1素子形成領域の第1辺と、第1辺に1角を介して隣接し、周辺部と境界をなす第2素子形成領域の第2辺とにより確定される三角形に重複して複数のダミー突起電極を形成する工程と、
突起電極及びダミー突起電極を覆う保護テープを主面の全域に貼付ける工程と、
保護テープが貼付けられた状態において、基板の主面と対向する裏面を研削し、基板の厚さを薄くする工程と、
を備えている。
また、本発明によれば、基板裏面の研削による基板の割れや欠けの損傷を防止しつつ、製造工程数を減少させることができ、基板の薄型化を実現することができる半導体装置の製造方法を提供することができる。
図1〜図18を用いて、本発明の第1実施の形態に係る半導体装置及びその製造方法を説明する。ここで、第1実施の形態に係る半導体装置及びその製造方法は、本発明をウェーハレベル チップサイズ パッケージ構造を有する半導体装置及びその製造方法に適用した例を説明するものである。
図1〜図3に示されるように、本実施の形態に係る半導体装置10は、基板としての半導体ウェーハ12を備えている。本実施の形態では、半導体ウェーハ12にシリコン単結晶ウェーハが使用されている。図2に示されるように、半導体ウェーハ12は平面視において円形状に形成されている。そして、半導体ウェーハ12の周縁の一部(図2下側)には、製造や搬送の際に位置決めとして使用されるオリエンテーションフラット12Cが形成されている。半導体ウェーハ12は、後述するバックグラインド処理前では例えば600μm〜650μmの厚さに設定されている。バックグラインド処理後では、半導体ウェーハ12は、200μm以下、好ましくは150μm以下の厚さに薄くされている。
本実施の形態に係る半導体装置10の製造方法は以下の通りである。まず最初に、例えば600μm〜650μmの厚さを有する半導体ウェーハ12が準備される(図4参照)。半導体ウェーハ12の主面12Aにおいて、中央部14には、図示省略の矩形平面状の素子形成領域20が第1方向及び第2方向に規則的に複数形成されている。次に、主面12A上であって、中央部14及び周辺部16を含む全域に層間絶縁層30が形成される。層間絶縁層30は、例えばシリコン酸化膜、シリコン窒化膜のいずれかの単層膜、又は双方の複合膜により形成されている。
本実施の形態に係る半導体装置10は、図1〜図3に示されるように、半導体ウェーハ12の主面12Aの周辺部16において、複数のダミー突起電極44Dを備える。詳しく説明すると、ダミー突起電極44Dは、図2及び図3に便宜的に描いて示す三角形60に重複して配設される。三角形60の1つは、周辺部16と境界をなす素子形成領域20(1,n)の第1辺20Aと、第1辺20Aに1角20Cを介して隣接し、周辺部16と境界をなす素子形成領域20(2,n+m)の第2辺20Bとにより確定される。そして、同様に、素子形成領域20(n+m)〜素子形成領域20(4,n+m+o+p)及び素子形成領域20(9,n+m+o+p)〜素子形成領域20(12,n)により確定される三角形60にも重複してダミー突起電極44Dが配設される。さらに、素子形成領域20(1,1)〜素子形成領域20(4,1)及び素子形成領域20(9,1)〜素子形成領域20(12,1)により確定される三角形60にもダミー突起電極44Dが配設される。
図19を用いて、本発明の第2実施の形態に係る半導体装置10及びその製造方法を説明する。
本実施の形態に係る半導体装置10及びその製造方法では、前述の第1実施の形態に係る半導体装置10及びその製造方法により得られる作用効果と同様の作用効果を得ることができる。
本発明は上記実施の形態に限定されるものではない。例えば、上記実施の形態では、基板として半導体ウェーハが使用されているが、本発明は、基板として化合物半導体基板、樹脂基板、ガラス基板等を使用してもよい。
12 半導体ウェーハ(基板)
12A 主面
12B 裏面
12D 研削痕
14 中央部
16 周辺部
20 素子形成領域
20A 第1辺
20B 第2辺
20C 1角
42 外部電極パッド
42Dダミー電極パッド
44 突起電極
44D ダミー突起電極
50 保護テープ
52 バックグラインドホイール
54 研削砥石
60 三角形
Claims (7)
- 主面の中央部において、矩形平面状の第1素子形成領域が第1方向にn個配設され、かつ、前記第1素子形成領域に対して第1方向と交差する第2方向に隣接して前記第1素子形成領域と同一形状の第2素子形成領域が第1方向にn+m個配設された基板と、
前記第1素子形成領域上及び前記第2素子形成領域上に各々複数形成された突起電極と、
前記主面の周辺部において、当該周辺部と境界をなす前記第1素子形成領域の第1辺と、当該第1辺に1角を介して隣接し、当該周辺部と境界をなす前記第2素子形成領域の第2辺とにより確定される三角形に重複して複数形成されたダミー突起電極と、
を備えた半導体装置。 - 前記基板の前記主面と対向する裏面において、前記第1辺又は前記第2辺に沿って延在する研削痕が形成されている
請求項1に記載の半導体装置。 - 前記第1素子形成領域及び前記第2素子形成領域には、各々、前記突起電極下に当該突起電極に電気的に接続された外部電極パッドが複数配設され、
前記周辺部において、前記ダミー突起電極下に当該ダミー突起電極に接続されたダミー電極パッドが複数配設されている
請求項1又は請求項2に記載の半導体装置。 - 前記周辺部において、前記三角形に重複しない領域に、前記ダミー電極パッドが配設されている
請求項3に記載の半導体装置。 - 前記周辺部において、前記三角形に重複しない領域に、前記ダミー電極パッドが配設されていない
請求項3に記載の半導体装置。 - 前記突起電極は、前記第1素子形成領域又は前記第2素子形成領域に形成された素子に電気的に接続され、
前記ダミー突起電極は、前記素子に電気的に接続されていない
請求項1〜請求項5のいずれか1項に記載の半導体装置。 - 基板主面の中央部において、第1方向にn個の矩形平面状の第1素子形成領域と、前記第1素子形成領域に対して第1方向と交差する第2方向に隣接して第1方向にn+m個の前記第1素子形成領域と同一形状の第2素子形成領域とが形成された前記基板を準備する工程と、
前記第1素子形成領域上及び前記第2素子形成領域上に各々複数の突起電極を形成すると共に、前記主面の周辺部において、当該周辺部と境界をなす前記第1素子形成領域の第1辺と、当該第1辺に1角を介して隣接し、当該周辺部と境界をなす前記第2素子形成領域の第2辺とにより確定される三角形に重複して複数のダミー突起電極を形成する突起電極形成工程と、
前記突起電極及び前記ダミー突起電極を覆う保護テープを前記主面の全域に貼付ける保護テープ貼付工程と、
前記保護テープが貼付けられた状態において、前記基板の前記主面と対向する裏面を研削し、当該基板の厚さを薄くする薄膜化工程と、
を備えた半導体装置の製造方法。
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US10043773B2 (en) | 2018-08-07 |
JP6616143B2 (ja) | 2019-12-04 |
US9812417B2 (en) | 2017-11-07 |
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