JP5869902B2 - 半導体装置の製造方法及びウェハ - Google Patents
半導体装置の製造方法及びウェハ Download PDFInfo
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- JP5869902B2 JP5869902B2 JP2012029904A JP2012029904A JP5869902B2 JP 5869902 B2 JP5869902 B2 JP 5869902B2 JP 2012029904 A JP2012029904 A JP 2012029904A JP 2012029904 A JP2012029904 A JP 2012029904A JP 5869902 B2 JP5869902 B2 JP 5869902B2
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- insulating film
- pad electrode
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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Description
図1は、第1の実施形態に係る半導体装置の製造方法の一部を説明するための図である。本図に示す工程は、ウェハWFの状態の半導体チップを検査する工程である。本図に示す例では、半導体チップの検査を効率的に行うために、複数の半導体チップを同時に検査する。そして同一のテスト領域TEに属する半導体チップは、同時に検査される。ウェハのうち中央側に位置する部分は、製品化される半導体チップとなる有効領域CHAであるが、ウェハの縁に位置する部分は、製品化されない半導体チップとなる非有効領域DCHAである。
図15は、第2の実施形態に係る半導体装置の製造方法の要部を示す平面図である。本実施形態に係る半導体装置の製造方法は、非有効領域DCHAに形成されるバンプの形状を除いて、第1の実施形態と同様である。
第1の実施形態に示した方法を用いて、半導体装置を製造した(実施例1)。また比較例として、非有効領域DCHAに位置するバンプ形成用絶縁膜SRも、有効領域CHAに位置するバンプ形成用絶縁膜SRと同様に残した半導体装置を製造した(比較例1)。なお、半導体ウェハとしては、直径が300mmのSiウェハを使用した。
BPO バンプ形成用開口
BPO2 ダミー開口
CHA 有効領域
CHP 半導体チップ
CVF 保護絶縁膜
CVL 遮光部材
DBMP1 ダミーバンプ
DBMP2 ダミーバンプ(第2バンプ)
DBMP3 ダミーバンプ
DCHA 非有効領域
INT 配線基板
INS 層間絶縁膜
OP1 第1開口
PAD1 第1パッド電極
PAD2 第2パッド電極
PAD3 第3パッド電極
PLB プローブ針
RP 感光性膜
SEL シール部材
SEM シードメタル膜
SOB ハンダボール
SOM ハンダ層
SOM2 ハンダ層
SR バンプ形成用絶縁膜
TE テスト領域
UBM アンダーバンプメタル
WF ウェハ
Claims (9)
- 製品化される半導体チップとなる有効領域を有すると共に、製品化されない半導体チップとなる非有効領域を周縁部に有し、さらに前記有効領域に複数の第1パッド電極を有すると共に前記非有効領域に複数の第2パッド電極を有するウェハを準備する工程と、
前記複数の第1パッド電極上及び前記複数の第2パッド電極上に、バンプ形成用絶縁膜を形成する工程と、
前記第1パッド電極の上から前記バンプ形成用絶縁膜を除去して第1開口を形成すると共に、前記第2パッド電極のうち遮光部材の縁と交わる電極パッドである第3パッド電極の全体上から、前記非有効領域に位置する前記バンプ形成用絶縁膜を除去する工程と、
前記バンプ形成用絶縁膜上、前記第1パッド電極上、及び前記第2パッド電極上に、感光性膜を形成する工程と、
前記ウェハの周縁部を前記遮光部材で遮光した状態で、前記感光性膜を露光する工程と、
前記感光性膜を現像することにより、前記感光性膜に、前記第1パッド電極上、前記第2パッド電極上、及び前記第3パッド電極それぞれ上に位置するバンプ形成用開口を形成する工程と、
前記感光性膜をマスクとしてめっき処理を行うことにより、前記複数のバンプ形成用開口それぞれの内にバンプを形成する工程と、
を備える半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記バンプ形成用絶縁膜を除去する工程において、前記第3パッド電極上に位置する前記バンプ形成用開口内に前記バンプ形成用絶縁膜が残らないようにする半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第1パッド電極上に位置する前記バンプの直径はlであり、
前記バンプ形成用絶縁膜を除去する工程において、前記バンプ形成用絶縁膜の内、前記第3パッド電極上、及び前記第3パッド電極から距離0.5×lの範囲内に位置する部分を除去する半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第1パッド電極上に位置する前記バンプの直径はlであり、
前記バンプ形成用絶縁膜を除去する工程において、前記遮光部材の縁よりもl×2内側に位置する部分から、前記ウェハの縁の間に位置する前記バンプ形成用絶縁膜を除去する半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記バンプ形成用絶縁膜を除去する工程において、前記非有効領域上に位置する前記バンプ形成用絶縁膜のすべてを除去する半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第3パッド電極上に位置する前記バンプは、前記第1パッド電極上に位置するバンプよりも小さく形成される半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
プローブを用いて、前記有効領域に位置する前記バンプ、及び前記非有効領域に位置する前記バンプにプローブを接触させて、前記製品化される半導体チップを検査する工程と、
を備える半導体装置の製造方法。 - 製品化される半導体チップとなる有効領域を有すると共に、製品化されない半導体チップとなる非有効領域を周縁部に有し、
前記有効領域に設けられた複数の第1パッド電極と、
前記非有効領域に設けられた複数の第2パッド電極と、
前記有効領域及び前記非有効領域に形成され、前記第1パッド電極上及び前記第2パッド電極上に開口を有する保護絶縁膜と、
前記保護絶縁膜上に位置するバンプ形成用絶縁膜と、
前記バンプ形成用絶縁膜に形成され、前記第1パッド電極上に位置する第1開口と、
前記第1パッド電極上及び一部の前記第2パッド電極上に形成されたバンプと、
を備え、
前記バンプのうち最も外側に位置する前記バンプには、前記第1パッド電極上に位置する第1バンプよりも小さい第2バンプが含まれており、
平面視で前記第2バンプの底面と重なる領域からは、前記バンプ形成用絶縁膜が除去されているウェハ。 - 請求項8に記載のウェハにおいて、
前記非有効領域上に位置する前記バンプ形成用絶縁膜のすべてが除去されているウェハ。
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US11855028B2 (en) | 2021-01-21 | 2023-12-26 | Taiwan Semiconductor Manufacturing | Hybrid micro-bump integration with redistribution layer |
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