CN115377039A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN115377039A
CN115377039A CN202210124124.5A CN202210124124A CN115377039A CN 115377039 A CN115377039 A CN 115377039A CN 202210124124 A CN202210124124 A CN 202210124124A CN 115377039 A CN115377039 A CN 115377039A
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pad
conductive material
insulating
semiconductor device
semiconductor
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CN202210124124.5A
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渡边慎也
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Kioxia Corp
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Kioxia Corp
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Publication of CN115377039A publication Critical patent/CN115377039A/zh
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Abstract

本实施方式的半导体装置具备第1绝缘层。第1焊垫露出在第1绝缘层的表面。第2绝缘层接合于第1绝缘层。第2焊垫露出在第2绝缘层的表面，且接合于第1焊垫。在从相对于第1绝缘层的表面大致垂直方向的第1俯视时，在第1焊垫的内侧，存在第1导电性材料、及蚀刻速率比第1导电性材料低的第1绝缘性材料。第1绝缘性材料在第1导电性材料的内侧呈岛屿状设置。

Description

半导体装置
[相关申请案的引用]
本申请案基于2021年05月21日提出申请的在先日本专利申请案第2021-086411号的优先权而主张优先权利益，通过引用将其全部内容并入本文中。
技术领域
本实施方式涉及一种半导体装置。
背景技术
近年来，开发了将多个半导体芯片彼此贴合而将焊垫电接合的技术。另一方面，在CMP(Chemical Mechanical Polishing，化学机械抛光)法等研磨方法中，有时由于被研磨的材质的差异，而产生碟状变形(凹陷)。如果接合面的焊垫因碟状变形而凹陷，那么在将多个半导体芯片彼此贴合时，存在焊垫间的接触电阻上升，或者产生焊垫间的开路不良的情况。
发明内容
一实施方式提供一种能够抑制所贴合的半导体芯片间的接触电阻上升或者抑制开路不良的半导体装置。
本实施方式的半导体装置具备第1绝缘层。第1焊垫露出在第1绝缘层的表面。第2绝缘层接合于第1绝缘层。第2焊垫露出在第2绝缘层的表面，且接合于第1焊垫。在从相对于第1绝缘层的表面大致垂直方向的第1俯视时，在第1焊垫的内侧，有第1导电性材料、及蚀刻速率比第1导电性材料低的第1绝缘性材料。第1绝缘性材料在第1导电性材料的内侧呈岛屿状设置。
根据所述构成，可提供一种能够抑制所贴合的半导体芯片间的接触电阻上升或者抑制开路不良的半导体装置。
附图说明
图1是表示第1实施方式的半导体封装的构成例的剖视图。
图2是表示第1实施方式的半导体封装的一部分的构成例的剖视图。
图3A是表示焊垫的构成例的俯视图。
图3B是表示焊垫的构成例的俯视图。
图3C是表示配线层的构成的一例的俯视图。
图4是表示接合面的部分的构成例的剖视图。
图5是表示第1实施方式的焊垫的制造方法的一例的剖视图。
图6是表示接在图5之后的焊垫的制造方法的一例的剖视图。
图7是表示接在图6之后的焊垫的制造方法的一例的剖视图。
图8是表示接在图7之后的焊垫的制造方法的一例的剖视图。
图9是表示接在图8之后的焊垫的制造方法的一例的剖视图。
图10是表示接在图9之后的焊垫的制造方法的一例的剖视图。
图11是表示接在图10之后的焊垫的制造方法的一例的剖视图。
图12是表示电路芯片的贯通电极的区域的形成工序的一例的剖视图。
图13是表示接在图12之后的焊垫的制造方法的一例的剖视图。
图14是表示接在图13之后的焊垫的制造方法的一例的剖视图。
图15是表示接在图14之后的焊垫的制造方法的一例的剖视图。
图16是表示接在图15之后的焊垫的制造方法的一例的剖视图。
图17是表示接在图16之后的焊垫的制造方法的一例的剖视图。
图18A是表示焊垫的制造方法的另一例的剖视图。
图18B是表示接在图18A之后的焊垫的制造方法的剖视图。
图18C是表示接在图18B之后的焊垫的制造方法的剖视图。
图18D是表示接在图18C之后的焊垫的制造方法的剖视图。
图19A是表示焊垫的制造方法的又一例的剖视图。
图19B是表示接在图19A之后的焊垫的制造方法的剖视图。
图19C是表示接在图19B之后的焊垫的制造方法的剖视图。
图19D是表示接在图19C之后的焊垫的制造方法的剖视图。
图19E是表示接在图19D之后的焊垫的制造方法的剖视图。
图19F是表示接在图19E之后的焊垫的制造方法的剖视图。
图19G是表示接在图19F之后的焊垫的制造方法的剖视图。
图20A是表示电路芯片的贯通电极的区域的形成工序的另一例的剖视图。
图20B是表示接在图20A之后的贯通电极的区域的形成工序的另一例的剖视图。
图20C是表示接在图20B之后的贯通电极的区域的形成工序的另一例的剖视图。
图20D是表示接在图20C之后的贯通电极的区域的形成工序的另一例的剖视图。
图20E是表示接在图20D之后的贯通电极的区域的形成工序的另一例的剖视图。
图20F是表示接在图20E之后的贯通电极的区域的形成工序的另一例的剖视图。
图21是表示第2实施方式的焊垫的构成例的俯视图。
图22是表示第2实施方式的接合面的区域的构成例的剖视图。
图23是表示第3实施方式的焊垫的构成例的俯视图。
图24是表示第4实施方式的焊垫的构成例的俯视图。
图25是表示第5实施方式的接合面的区域的构成例的剖视图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。本实施方式并不限定本发明。在以下的实施方式中，半导体芯片的上下方向有时与依据重力加速度的上下方向不同。附图是示意性的图或概念性的图，各部分的比率等未必与实物相同。在说明书与附图中，对与上文中针对已出现的附图叙述过的内容相同的要素标注相同的符号并适当省略详细的说明。
(第1实施方式)图1是表示第1实施方式的半导体封装1的构成例的剖视图。本实施方式的半导体封装1是半导体存储器的封装的例子。然而，本实施方式也可以应用于其它半导体装置。
半导体封装1具备配线衬底10、金属凸块20、焊料球70、控制器芯片30、包含积层的多个存储器芯片的存储器芯片积层体40、以贯通各存储器芯片的方式设置的电极50、及密封树脂60。
配线衬底10具备绝缘体11、配线层12、及阻焊剂层13。绝缘体11例如使用玻璃环氧树脂等绝缘材料。配线层12是设置在绝缘体11的表面及背面的导电体。配线层12例如使用铜等低电阻金属材料。阻焊剂层13设置在配线层12之上。
金属凸块20设置在配线衬底10的表面侧，且电连接于配线层12的一部分。焊料球70设置在配线衬底10的背面侧，且电连接于配线层12的一部分。
控制器芯片30设置在配线衬底10的表面上方。控制器芯片30以控制多个存储器芯片的方式设置。
存储器芯片积层体40积层在控制器芯片30之上。多个存储器芯片例如为搭载NAND(Not And，与非)型存储单元的半导体芯片。各存储器芯片及控制器芯片30经由电极50而电连接。电极50传递电源电力、接地电压、控制信号、或数据等。电极50例如使用钨、镍、铜、金、铝、多晶硅等导电性材料。
密封树脂60设置在配线衬底10的表面上，且将控制器芯片30及存储器芯片积层体40密封。
图2是表示第1实施方式的半导体封装1的一部分的构成例的剖视图。在图2中，表示所积层的2个存储器芯片40＿1、40＿2的截面。存储器芯片40＿1与存储器芯片40＿2在接合面B＿chip中接合。
存储器芯片40＿1包括包含存储单元阵列MCA1的阵列芯片CH＿A1、及包含CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)电路CMOS1的电路芯片CH＿C1。存储器芯片40＿2包括包含存储单元阵列MCA2的阵列芯片CH＿A2、及包含CMOS电路CMOS2的电路芯片CH＿C2。
在存储器芯片40＿1中，也可以将存储单元阵列MCA1或CMOS1的任一者设为第1半导体电路，将另一者设为第2半导体电路。
在存储器芯片40＿2中，也可以将存储单元阵列MCA2或CMOS2的任一者设为第1半导体电路，将另一者设为第2半导体电路。
也可以隔着接合面B＿chip，将存储器芯片40＿1包含的存储单元阵列MCA1及CMOS1设为第1半导体电路，将存储器芯片40＿2包含的存储单元阵列MCA2及CMOS2设为第2半导体电路。
(存储器芯片40＿1)阵列芯片CH＿A1包含由层间绝缘膜ILD1＿1被覆的存储单元阵列MCA1。存储单元阵列MCA1具有在Z方向上积层且相互绝缘的多个字线WL1、及以在积层方向(Z方向)上贯通所积层的多个字线WL1的方式延伸的多个柱状体CL1。对应于字线WL1与柱状体CL1的交叉点而设置着存储单元MC1。多个柱状体CL1的一端共通连接于源极线SL1。多个柱状体CL1的另一端连接于在Y方向上延伸的位线BL1的任一个。
存储单元阵列MCA1设置在阵列区域R＿Arr。字线WL1在X方向上延伸到阶台区域R＿Trr，且在阶台区域R＿Trr中呈阶梯状形成。对呈阶梯状形成的各字线WL1的阶梯面，连接着接触插塞CC1。接触插塞CC1经由配线层W1＿1电连接于分别设置在阵列区域R＿Arr的焊垫P1＿1a与字线WL1之间。焊垫P1＿1a是从层间绝缘膜ILD1＿1的表面露出，且设置在阵列芯片CH＿A1的接合面B＿mc1的电极焊垫。配线层W1＿1经由接触插塞CC1将存储单元阵列MCA1与焊垫P1＿1a之间电连接。
在阵列区域R＿Arr及阶台区域R＿Trr的周围，设置着周边区域R＿Pri。周边区域R＿Pri也可以设置在不仅包含存储器芯片的周边部而且也包含存储器芯片的中央部在内的各种位置。在周边区域R＿Pri，接触插塞Cpri1以在Z方向上贯通阵列芯片CH＿A1的层间绝缘膜ILD1＿1的方式设置。接触插塞Cpri1的一端经由配线层W1＿1电连接于设置在周边区域R＿Pri的接合面B＿mc1的焊垫P1＿1a。接触插塞Cpri1的另一端电连接于设置在阵列芯片CH＿A1的与接合面B＿mc1相反一面的焊垫P1＿1b。
电路芯片CH＿C1设置在阵列芯片CH＿A1的下方(-Z方向)，且包含由层间绝缘膜ILD1＿2被覆的CMOS电路CMOS1。CMOS电路CMOS1设置在半导体层SUB1上，是包含P型MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金属氧化物半导体场效应晶体管)及N型MOSFET的电路。CMOS电路CMOS1也可以包含其它半导体元件(例如，电阻元件、电容元件)。CMOS电路CMOS1由层间绝缘膜ILD1＿2被覆。在层间绝缘膜ILD1＿2，设置着多层配线层W1＿2。多层配线层W1将CMOS电路CMOS1与焊垫P1＿2a之间电连接。焊垫P1＿2a是从层间绝缘膜ILD1＿2的表面露出，且设置在电路芯片CH＿C1的接合面B＿mc1的电极焊垫。焊垫P1＿2a也可以设置在阵列区域R＿Arr、阶台区域R＿Trr及周边区域R＿Pri中的任一个区域。
在电路芯片CH＿C1的周边区域R＿Pri，设置着贯通电极TSV1。贯通电极TSV1是电极50的一部分。贯通电极TSV1在Z方向上贯通半导体层SUB1，且电连接于焊垫P1＿2a与焊垫P1＿2b之间。焊垫P1＿2b是设置在与接合面B＿mc1相反侧的贯通电极TSV1的端部的电极焊垫。
阵列芯片CH＿A1与电路芯片CH＿C1在接合面B＿mc1被贴合。在接合面B＿mc1中，层间绝缘膜ILD1＿1、ILD1＿2被接合，焊垫P1＿1a与P1＿2a被接合。由此，电路芯片CH＿C1的CMOS电路CMOS1经由多层配线层W1＿2、焊垫P1＿2a、P1＿1a及接触插塞CC1电连接于存储单元阵列MCA1。结果，CMOS电路CMOS1能够控制存储单元阵列MCA1。另外，贯通电极TSV1经由焊垫P1＿2a、P1＿1a及配线层W1＿1电连接于接触插塞Cpri1。贯通电极TSV1例如是为了能够将电源电力或接地电位共通地传递到芯片间而设置。
(存储器芯片40＿2)阵列芯片CH＿A2包含由层间绝缘膜ILD2＿1被覆的存储单元阵列MCA2。存储单元阵列MCA2具有在Z方向上积层且相互绝缘的多个字线WL2、及以在积层方向(Z方向)上贯通所积层的多个字线WL2的方式延伸的多个柱状体CL2。对应于字线WL2与柱状体CL2的交叉点而设置着存储单元MC2。多个柱状体CL2的一端共通连接于源极线SL2。多个柱状体CL2的另一端连接于在Y方向上延伸的位线BL2的任一个。
存储单元阵列MCA2设置在阵列区域R＿Arr。字线WL2在X方向上延伸到阶台区域R＿Trr，且在阶台区域R＿Trr中呈阶梯状形成。针对呈阶梯状形成的各字线WL2的阶梯面，连接着接触插塞CC2。接触插塞CC2经由配线层W2＿1电连接于分别设置在阵列区域R＿Arr的焊垫P2＿1a与字线WL2之间。焊垫P2＿1a是露出在层间绝缘膜ILD2＿1的表面且设置在阵列芯片CH＿A2的接合面B＿mc2的电极焊垫。配线层W2＿1经由接触插塞CC2将存储单元阵列MCA2与焊垫P2＿1a之间电连接。
在阵列区域R＿Arr及阶台区域R＿Trr的周围，设置着周边区域R＿Pri。在周边区域R＿Pri，接触插塞Cpri2以在Z方向上贯通阵列芯片CH＿A2的层间绝缘膜ILD2＿1的方式设置。接触插塞Cpri2的一端经由配线层W2＿1电连接于设置在周边区域R＿Pri的接合面B＿mc2的焊垫P2＿1a。接触插塞Cpri2的另一端电连接于设置在阵列芯片CH＿A2的与接合面B＿mc2相反一面的焊垫P2＿1b。
电路芯片CH＿C2设置在阵列芯片CH＿A2的下方(-Z方向)，且包含由层间绝缘膜ILD2＿2被覆的CMOS电路CMOS2。CMOS电路CMOS2设置在半导体层SUB2上，是包含P型MOSFET及N型MOSFET的电路。CMOS电路CMOS2也可以包含其它半导体元件(例如，电阻元件、电容元件)。CMOS电路CMOS2由层间绝缘膜ILD2＿2被覆。在层间绝缘膜ILD2＿2，设置着多层配线层W2＿2。多层配线层W2＿2将CMOS电路CMOS2与焊垫P2＿2a之间电连接。焊垫P2＿2a是露出在层间绝缘膜ILD2＿2的表面且设置在电路芯片CH＿C2的接合面B＿mc2的电极焊垫。焊垫P2＿2a也可以设置在阵列区域R＿Arr、阶台区域R＿Trr及周边区域R＿Pri中的任一个区域。
在电路芯片CH＿C2的周边区域R＿Pri，设置着贯通电极TSV2。贯通电极TSV2在Z方向上贯通半导体层SUB2，且电连接于焊垫P2＿2a与焊垫P2＿2b之间。焊垫P2＿2b是设置在与接合面B＿mc2相反侧的贯通电极TSV2的端部的电极焊垫。
阵列芯片CH＿A2与电路芯片CH＿C2在接合面B＿mc2被贴合。在接合面B＿mc2中，层间绝缘膜ILD2＿1、ILD2＿2被接合，焊垫P2＿1a与P2＿2a被接合。由此，电路芯片CH＿C2的CMOS电路CMOS2经由多层配线层W2＿2、焊垫P2＿2a、P2＿1a及接触插塞CC2电连接于存储单元阵列MCA2。结果，CMOS电路CMOS2能够控制存储单元阵列MCA2。另外，贯通电极TSV2经由焊垫P2＿2a、P2＿1a及配线层W2＿1电连接于接触插塞Cpri2。贯通电极TSV2例如也是为了能够将电源电力或接地电位共通地传递到芯片间而设置。
(存储器芯片40＿1、40＿2间的接合)存储器芯片40＿1与存储器芯片40＿2在接合面B＿chip被接合。在接合面B＿chip中，焊垫P1＿1b与焊垫P2＿1b被接合。存储器芯片40＿1与40＿2经由相互接合的焊垫P1＿1b、P2＿1b电连接。由此，贯通电极TSV1、TSV2及接触插塞Cpri1、Cpri2被电连接，例如，能够将电源电力或接地电位在所积层的多个存储器芯片40＿1、40＿2间共通地传递。
(焊垫P1＿1a等的构成)图3A是表示焊垫P1＿1a的构成例的俯视图。在图3A中，在从相对于阵列芯片CH＿A1的层间绝缘膜ILD1＿1的表面(接合面B＿mc1)大致垂直方向的第1俯视(从Z方向观察的俯视)时，焊垫P1＿1a从层间绝缘膜ILD1＿1的表面露出。在所述俯视时，焊垫P1＿1a的周边被层间绝缘膜ILD1＿1包围，例如，该焊垫P1＿1a具有大致八边形的形状。焊垫P1＿1a的平面形状也可以为八边形以外的多边形、大致圆形、大致椭圆形。
在焊垫P1＿1a的内侧，设置着障壁金属膜101＿1a、导电性材料102＿1a、及绝缘性材料103＿1a。在焊垫P1＿1a的外侧，设置着层间绝缘膜ILD1＿1。
障壁金属膜101＿1a设置在焊垫P1＿1a的外缘，且设置在层间绝缘膜ILD1＿1或绝缘性材料103＿1a与导电性材料102＿1a之间。障壁金属膜101＿1a例如使用钛膜及氮化钛膜的积层膜等导电性材料。
导电性材料102＿1a设置在由障壁金属膜101＿1a包围的焊垫P1＿1a的内侧。导电性材料102＿1a例如使用铜、钨等导电性材料。绝缘性材料103＿1a在导电性材料102＿1a的内侧呈岛屿状设置，它的周围由导电性材料102＿1a包围。
在所述俯视时，多个绝缘性材料103＿1a在导电性材料102＿1a的表面，分别在Y方向上延伸，且具有细长形状。另外，在所述俯视时，多个绝缘性材料103＿1a在导电性材料102＿1a的表面，在相对于Y方向正交的X方向上呈条纹状或线与间隙状排列。换句话说，多个绝缘性材料103＿1a设置为大致平行地延伸的狭缝状或短条状。多个绝缘性材料103＿1a在所述俯视时，设置在焊垫P1＿1a的内侧，且未到达障壁金属膜101＿1a及层间绝缘膜ILD1＿1。此外，绝缘性材料103＿1a也可以在焊垫P1＿1a的下方与层间绝缘膜ILD1＿1相连。绝缘性材料103＿1a可使用与层间绝缘膜ILD1＿1相同的材料(例如，氧化硅膜)。
另外，在所述俯视时，焊垫P1＿1a的绝缘性材料103＿1a的面积小于导电性材料102＿1a的面积。通过使导电性材料102＿1a的面积相对较大，而与电路芯片CH＿C1的焊垫P1＿2a的导电性材料102＿2a的接触面积变大，能够将焊垫P1＿1a与焊垫P1＿2a之间的接触电阻抑制得较低。
此处，绝缘性材料103＿1a由CMP工序中的蚀刻速率比导电性材料102＿1a的材料(例如，铜或钨等金属材料)低的材料(例如，能够使用氧化硅膜等氧化膜、或氮化硅膜等氮化膜、碳化硅膜等碳化膜、或它们的复合材料等)形成。例如，绝缘性材料103＿1a也可以由比导电性材料102＿1a的材料更难研磨的物理上较硬的材料形成。或者，绝缘性材料103＿1a也可以由比导电性材料102＿1a的材料更难利用研磨剂(浆料)进行化学蚀刻的材料形成。因此，在CMP工序中，绝缘性材料103＿1a在导电性材料102＿1a的内侧成为支柱，能够缓和导电性材料102＿1a的中央部的膜厚变薄而出现凹陷(碟状变形)。
焊垫P1＿1a的X方向或Y方向的宽度Wp1＿1a例如约为1μm。绝缘性材料103＿1a的宽度W103＿1a例如约为几十nm。
由虚线表示的配线层W1＿1设置在焊垫P1＿1a之下。配线层W1＿1经由通孔触点V1＿1电连接于焊垫P1＿1a。在本实施方式中，9个通孔触点V1＿1设置在焊垫P1＿1a与配线层W1＿1之间。然而，通孔触点V1＿1的个数并不限定为9个，可为任意。另外，图3C是表示配线层W1＿1的构成的一例的俯视图。配线层W1＿1在所述俯视时在焊垫P1＿1a的下方在大致方形的框内形成为十字形状。在配线层W1＿1上，设置着9个通孔触点V1＿1。另外，配线层W1＿1也可以并非十字形状，而为立体形状。
图3B是表示焊垫P1＿1a的构成例的剖视图。图3B表示沿着图3A的B-B线的截面。焊垫P1＿1a填埋在层间绝缘膜ILD1＿1内，且露出在层间绝缘膜ILD1＿1的表面。导电性材料102＿1a经由通孔触点V1＿1电连接于设置在所述导电性材料102＿1a之下的配线层W1＿1。绝缘性材料103＿1a可以是层间绝缘膜ILD1＿1的一部分，也可以是相同材料。此外，导电性材料102＿1a的高度例如约为1μm。
这样，根据本实施方式，焊垫P1＿1a包含绝缘性材料103＿1a，所述绝缘性材料103＿1a在从相对于接合面B＿mc1大致垂直的方向俯视时，在导电性材料102＿1a的内侧呈岛屿状设置。绝缘性材料103＿1a由蚀刻速率比导电性材料102＿1a低的材料形成。因此，在对层间绝缘膜ILD1＿1及导电性材料102＿1a进行研磨的CMP工序中，绝缘性材料103＿1a在导电性材料102＿1a内成为支柱，能够缓和导电性材料102＿1a的碟状变形。
在未设置绝缘性材料103＿1a的情况下，导电性材料102＿1a以相对较宽的面积被研磨。在该情况下，在导电性材料102＿1a的内侧，呈大幅度碟状变形地凹陷。
相对于此，根据本实施方式，绝缘性材料103＿1a将导电性材料102＿1a分为相对较小的面积，在导电性材料102＿1a内成为支柱。由此，抑制导电性材料102＿1a的内侧产生碟状变形。
绝缘性材料103＿1a优选为在导电性材料102＿1a内大致均等地配置。由此，能够抑制局部大幅度地产生导电性材料102＿1a的碟状变形。
图3A及图3B对焊垫P1＿1a进行了说明，但关于焊垫P1＿2a、P2＿1a、P2＿2a、P1＿2b、P2＿1b也可以同样地构成。由此，关于焊垫P1＿1a以外的其它焊垫P1＿2a、P2＿1a、P2＿2a、P1＿2b、P2＿1b，同样地，在CMP工序中抑制碟状变形。此外，焊垫P1＿2a、P2＿1a、P2＿2a、P1＿2b、P2＿1b的构成只要参照图3A及图3B便能够容易地理解，所以省略其详细的说明。
图4是表示接合面B＿mc1的部分的构成例的剖视图。阵列芯片CH＿A1侧的焊垫P1＿1a与电路芯片CH＿C1侧的焊垫P1＿2a在接合面B＿mc1被接合。
焊垫P1＿1a及焊垫P1＿2a均具有图3A及图3B所示的构成。因此，与图3A所示的焊垫P1＿1a同样地，在从相对于层间绝缘膜ILD1＿2的表面大致垂直的方向俯视时，在焊垫P1＿2a的内侧，设置着障壁金属膜101＿2a、导电性材料102＿2a、及绝缘性材料103＿2a。
此外，在以下的焊垫P1＿2a的说明中，图3A及图3B的焊垫P1＿1a、层间绝缘膜ILD1＿1、障壁金属膜101＿1a、导电性材料102＿1a、及绝缘性材料103＿1a分别被改称为焊垫P1＿2a、层间绝缘膜ILD1＿2、障壁金属膜101＿2a、导电性材料102＿2a、及绝缘性材料103＿2a。在焊垫P1＿2a的外侧，设置着层间绝缘膜ILD1＿2。
障壁金属膜101＿2a设置在焊垫P1＿2a的外缘，且设置在层间绝缘膜ILD1＿2或绝缘性材料103＿2a与导电性材料102＿2a之间。障壁金属膜101＿2a例如使用钛膜及氮化钛膜的积层膜等导电性材料。
导电性材料102＿2a设置在由障壁金属膜101＿2a包围的焊垫P1＿2a的内侧。导电性材料102＿2a例如使用铜、钨等导电性材料。绝缘性材料103＿2a在导电性材料102＿2a的内侧呈岛屿状设置，它的周围由导电性材料102＿2a包围。
在所述俯视时，多个绝缘性材料103＿2a在导电性材料102＿2a的表面，分别在Y方向上延伸，且具有细长形状。另外，在所述俯视时，多个绝缘性材料103＿2a在导电性材料102＿2a的表面，在相对于Y方向正交的X方向上呈条纹状或线与间隙状排列。换句话说，多个绝缘性材料103＿2a设置为大致平行地延伸的狭缝状或短条状。多个绝缘性材料103＿2a在所述俯视时，设置在焊垫P1＿2a的内侧，且未到达障壁金属膜101＿2a及层间绝缘膜ILD1＿2。此外，绝缘性材料103＿2a可使用与层间绝缘膜ILD1＿2相同的材料(例如，氧化硅膜)。
此处，绝缘性材料103＿2a由蚀刻速率比导电性材料102＿2a的材料(例如，铜或钨等金属材料)低的材料(例如，氧化硅膜)形成。例如，绝缘性材料103＿2a也可以由比导电性材料102＿2a的材料更难研磨的物理上较硬的材料形成。或者，绝缘性材料103＿2a也可以由比导电性材料102＿2a的材料更难利用研磨剂(浆料)进行化学蚀刻的材料形成。因此，在CMP工序中，绝缘性材料103＿2a在导电性材料102＿2a的内侧成为支柱，能够缓和导电性材料102＿2a的碟状变形。
焊垫P1＿2a的X方向或Y方向的宽度Wp1＿2a例如约为1μm。绝缘性材料103＿2a的宽度W103＿2a例如约为几十nm。
焊垫P1＿2a填埋在层间绝缘膜ILD1＿2内，且露出在层间绝缘膜ILD1＿2的表面。导电性材料102＿2a电连接于设置在导电性材料102＿2a之下的配线层W1＿2。绝缘性材料103＿2a可以是层间绝缘膜ILD1＿2的一部分，也可以是相同材料。此外，导电性材料102＿2a的高度例如约为1μm。
这样，焊垫P1＿1a、P1＿2a具有大致相同的构成。焊垫P1＿1a与焊垫P1＿2a在焊垫P1＿1a与焊垫P1＿2a的接合面B＿mc1，以绝缘性材料103＿1a的延伸方向与绝缘性材料103＿2a的延伸方向成为大致相同的方向(例如，Y方向)的方式被接合。由此，在将阵列芯片CH＿A1与电路芯片CH＿C1贴合时，如图4所示，导电性材料102＿1a与导电性材料102＿2a在接合面B＿mc1以大致对向地一致的方式被接合。此时，焊垫P1＿1a、P1＿2a几乎不会产生碟状变形，导电性材料102＿1a、102＿2a在接合面B＿mc1几乎不会凹陷。也就是说，导电性材料102＿1a、102＿2a在接合面B＿mc1中设置在大致同一面。因此，虽然在导电性材料102＿1a及导电性材料102＿2a各自的内侧设置着绝缘性材料103＿1a、103＿2a，但是导电性材料102＿1a及导电性材料102＿2a在接合面B＿mc1能够以充分低的电阻接合。
如果不设置绝缘性材料103＿1a、103＿2a，那么虽然接合面B＿mc1中的导电性材料102＿1a、102＿2a的面积相应地变宽，但是导电性材料102＿1a、102＿2a容易因CMP工序中的碟状变形而产生接合不良。因此，担心导电性材料102＿1a与导电性材料102＿2a之间的接触电阻变高。
相对于此，根据本实施方式，由于设置着绝缘性材料103＿1a、103＿2a，所以接合面B＿mc1中的导电性材料102＿1a、102＿2a的面积相应地变小。然而，导电性材料102＿1a、102＿2a的碟状变形得到抑制，导电性材料102＿1a、102＿2a在接合面B＿mc1几乎不会凹陷。因此，能够使导电性材料102＿1a与导电性材料102＿2a之间的接触电阻较低且稳定。
接下来，对第1实施方式的焊垫P1＿1a、P1＿2a的制造方法进行说明。
图5～图11是表示第1实施方式的焊垫P1＿1a的制造方法的一例的剖视图。此外，焊垫P1＿2a的制造方法与焊垫P1＿1a的制造方法相同，所以省略其详细的说明。
首先，在阵列芯片CH＿A1的衬底(例如，硅衬底)形成存储单元阵列MCA1及层间绝缘膜ILD1＿1等。接下来，在阵列芯片CH＿A1的层间绝缘膜ILD1＿1形成配线层W1＿1。接下来，在配线层W1＿1及层间绝缘膜ILD1＿1上进而堆积绝缘膜。绝缘膜可以是与层间绝缘膜ILD1＿1相同的材料(例如，氧化硅膜)。因此，也将配线层W1＿1上的绝缘膜称为层间绝缘膜ILD1＿1。由此，获得图5所示的构造。
接下来，使用光刻技术及蚀刻技术，对配线层W1＿1上的层间绝缘膜ILD1＿1进行加工。由此，如图6所示，将配线层W1＿1上的层间绝缘膜ILD1＿1加工成通孔触点V1＿1的图案。
接下来，如图7所示，在层间绝缘膜ILD1＿1及配线层W1＿1上堆积障壁金属膜201＿1a及导电性材料202＿1a。障壁金属膜201＿1a例如使用钛膜与氮化钛膜的积层膜等。导电性材料202＿1a例如使用铜、钨等导电性材料。
接下来，使用CMP法，对障壁金属膜201＿1a及导电性材料202＿1a进行研磨，直到层间绝缘膜ILD1＿1露出为止。由此，如图8所示，形成包括障壁金属膜201＿1a及导电性材料202＿1a的通孔触点V1＿1。
接下来，在通孔触点V1＿1上进而堆积绝缘膜。绝缘膜可以是与层间绝缘膜ILD1＿1相同的材料(例如，氧化硅膜)。因此，也将通孔触点V＿1上的绝缘膜称为层间绝缘膜ILD1＿1。接下来，使用光刻技术及蚀刻技术，如图9所示，将通孔触点V1＿1上的层间绝缘膜IL＿1加工成焊垫P1＿1a的图案。此处，也可以在焊垫P1＿1a形成第1凹部Con＿1，在它的周围形成第1绝缘层，在第1凹部的内侧形成第1绝缘性材料。
接下来，如图10所示，在层间绝缘膜ILD1＿1及通孔触点V1＿1上堆积障壁金属膜101＿1a及导电性材料102＿1a。障壁金属膜101＿1a例如使用钛膜与氮化钛膜的积层膜等。导电性材料102＿1a例如使用铜、钨等导电性材料。
接下来，使用CMP法，对障壁金属膜101＿1a及导电性材料102＿1a进行研磨，直到层间绝缘膜ILD1＿1露出为止。由此，如图11所示，形成包含障壁金属膜101＿1a及导电性材料102＿1a的焊垫P1＿1a。此外，在CMP工序中露出的层间绝缘膜ILD1＿1成为所述绝缘性材料103＿1a。
此处，如图3A所示，绝缘性材料103＿1a在导电性材料102＿1a的内侧设置成岛屿状(例如，条纹状或线与间隙状)。在障壁金属膜101＿1a及导电性材料102＿1a的CMP工序中，绝缘性材料103＿1a在导电性材料102＿1a内作为支柱发挥功能。由此，焊垫P1＿1a中导电性材料102＿1a的碟状变形(凹陷)得到抑制。
以上，对阵列芯片CH＿A1的焊垫P1＿1a的制造方法进行了说明。电路芯片CH＿C1的焊垫P1＿2a虽然连接于CMOS电路CMOS1，但是与焊垫P1＿1a同样地形成。因此，焊垫P1＿2a中导电性材料102＿2a的碟状变形(凹陷)也得到抑制。
阵列芯片CH＿A1的焊垫P1＿1a及电路芯片CH＿C1的焊垫P1＿2a的碟状变形得到抑制。因此，在将阵列芯片CH＿A1与电路芯片CH＿C1贴合时，如图4所示，焊垫P1＿1a与焊垫P1＿2a几乎无间隙地充分接合。结果，能够抑制阵列芯片CH＿A1与电路芯片CH＿C1之间的焊垫间的接触电阻上升，抑制开路不良。
以上，对阵列芯片CH＿A1与电路芯片CH＿C1之间的接合进行了说明，但本实施方式也能够应用于存储器芯片40＿1、40＿2间的接合。
(存储器芯片40＿1、40＿2间的接合)如图2所示，存储器芯片40＿1与存储器芯片40＿2在接合面B＿chip被接合。存储器芯片40＿1、40＿2具有相同的构成。
在接合面B＿chip中，存储器芯片40＿1的焊垫P1＿2b与存储器芯片40＿2的焊垫P2＿1b电连接。焊垫P1＿2b经由再配线层(未图示)电连接于设置在存储器芯片40＿1的电路芯片CH＿C1的贯通电极TSV1。焊垫P2＿1b电连接于存储器芯片40＿2的阵列芯片CH＿A2的接触插塞Cpri2。
此处，焊垫P1＿2b、P2＿1b可分别具有与图3A及图3B所示的焊垫P1＿1a相同的构成。由此，焊垫P1＿2b与焊垫P1＿1a与图4所示的焊垫P1＿1a与焊垫P1＿2a同样地被接合。因此，在存储器芯片40＿1、40＿2间的接合中也能够获得本实施方式的效果。
图12～图17是表示电路芯片CH＿C1的贯通电极TSV1的区域的形成工序的一例的剖视图。
首先，使用半导体制造工艺，在衬底(例如，硅衬底)SUB1上形成CMOS电路CMOS1。如图12所示，CMOS电路CMOS1经由焊垫P1＿2b及配线W1＿2(或者贯通电极的承接电极)电连接于贯通电极TSV1。此外，在图13以后，省略了CMOS电路CMOS1、焊垫P1＿2b及配线W1＿2的图示。
接下来，使用光刻技术及蚀刻技术在贯通电极TSV1的形成区域形成孔。在该孔的内壁成膜间隔绝缘膜SP1。接下来，使用镀覆法等，在间隔绝缘膜(例如，氧化硅膜)SP1的内侧填埋贯通电极TSV1的材料(例如，铜、钨)。接下来，在衬底SUB1上堆积层间绝缘膜ILD1＿2。由此，获得图12所示的构造。
这样，贯通电极TSV1在形成CMOS电路之后形成。因此，由于在CMOS电路的高温热处理之后形成贯通电极TSV1，所以贯通电极TSV1的材料(例如，铜、钨)能够使用镀覆法成膜。贯通电极TSV1的CMOS电路侧的端部既可以与CMOS电路电连接，也可以与外部电极电连接。
接下来，将电路芯片CH＿C1与阵列芯片CH＿A1贴合。此时，焊垫P1＿1a与焊垫P1＿2a被接合(参照图2)。
接下来，如图13所示，使衬底SUB1的上下反转。接下来，如图14所示，对衬底SUB1的背面侧进行蚀刻，而使贯通电极TSV1及间隔绝缘膜SP1的端部露出。
接下来，如图15所示，将绝缘膜91、92堆积在衬底SUB1及贯通电极TSV1上。绝缘膜91例如为氮化硅膜，绝缘膜92例如为氧化硅膜。
接下来，如图16所示，使用CMP法对绝缘膜91、92进行研磨，直到使贯通电极TSV1露出为止。由此，贯通电极TSV1形成在衬底SUB1内。贯通电极TSV1在利用间隔绝缘膜SP1与衬底SUB1电绝缘的状态下，贯通衬底SUB1。
接下来，如图17所示，形成再配线层RW1。接下来，在再配线层RW1上形成焊垫P1＿2b。焊垫P1＿2b的构成及形成方法与参照图3A～图11所说明的内容相同。
然后，将存储器芯片40＿1、40＿2贴合。由此，如图2所示，焊垫P1＿2b与焊垫P2＿1b贴合。
此外，当在阵列芯片CH＿A1设置着贯通电极的情况下，阵列芯片CH＿A1的贯通电极也可与图12～图17所示的方法同样地形成。
(变化例1)图18A～图18D是表示焊垫P1＿1a的制造方法的另一例的剖视图。此外，焊垫P1＿2a的制造方法与焊垫P1＿1a的制造方法相同，所以省略其详细的说明。
在形成图5所示的构造之后，使用光刻技术及蚀刻技术，对配线层W1＿1上的层间绝缘膜ILD1＿1进行加工。由此，如图18A所示，将配线层W1＿1上的层间绝缘膜ILD1＿1加工成通孔触点V1＿1的图案。
接下来，再次使用光刻技术及蚀刻技术，对层间绝缘膜ILD1＿1进行加工，如图18B所示，将层间绝缘膜ILD1＿1的上部加工成焊垫P1＿1a的图案。由此，焊垫P1＿1a的图案形成在层间绝缘膜ILD1＿1的上部，通孔触点V1＿1的图案以接在焊垫P1＿1a的图案之下的方式形成。
接下来，如图18C所示，在层间绝缘膜ILD1＿1及配线层W1＿1上堆积障壁金属膜101＿1a及导电性材料102＿1a。
接下来，使用CMP法，对障壁金属膜101＿1a及导电性材料102＿1a进行研磨，直到层间绝缘膜ILD1＿1露出为止。由此，如图18D所示，同时形成包括障壁金属膜101＿1a及导电性材料102＿1a的通孔触点V1＿1及焊垫P1＿1a。在该CMP工序中，绝缘性材料103＿1a在导电性材料102＿1a的内侧成为支柱，能够缓和导电性材料102＿1a的碟状变形。
变化例1中，同时形成通孔触点V1＿1及焊垫P1＿1a。因此，变化例1能够利用比第1实施方式少的工序形成焊垫P1＿1a。变化例1的其它制造工序可与第1实施方式相同。因此，本变化例1能够获得与第1实施方式相同的效果。
(变化例2)图19A～图19G是表示焊垫P1＿1a的制造方法的又一例的剖视图。此外，焊垫P1＿2a的制造方法与焊垫P1＿1a的制造方法相同，所以省略其详细的说明。
在形成图5所示的构造之后，使用光刻技术及蚀刻技术，将配线层W1＿1上的层间绝缘膜ILD1＿1中焊垫P1＿1a的整个形成区域的层间绝缘膜ILD1＿1去除。由此，获得图19A所示的构造。
接下来，如图19B所示，在层间绝缘膜ILD1＿1及配线层W1＿1上堆积障壁金属膜101＿1a及导电性材料102＿1a。
接下来，使用CMP法，对障壁金属膜101＿1a及导电性材料102＿1a进行研磨，直到层间绝缘膜ILD1＿1露出为止。由此，如图19C所示，障壁金属膜101＿1a及导电性材料102＿1a形成在焊垫P1＿1a的整个形成区域。
接下来，使用光刻技术及蚀刻技术，对导电性材料102＿1a的上部进行加工，将处于绝缘性材料103＿1a的形成区域的导电性材料102＿1a去除。由此，获得图19D所示的构造。
接下来，如图19E所示，在层间绝缘膜ILD1＿1及导电性材料102＿1a上堆积障壁金属膜101＿3。
接下来，如图19F所示，将绝缘性材料103＿1a堆积在障壁金属膜101＿3上。
接下来，使用CMP法，对绝缘性材料103＿1a进行研磨，直到层间绝缘膜ILD1＿1露出为止。由此，如图19G所示，形成焊垫P1＿1a。在该CMP工序中，即便导电性材料102＿1a露出，绝缘性材料103＿1a在导电性材料102＿1a的内侧也会成为支柱，从而能够缓和导电性材料102＿1a的碟状变形。
在变化例2中，通孔触点V1＿1设置在焊垫P1＿1a的整个形成区域。在该情况下，焊垫P1＿1a经由通孔触点V1＿1连接于配线层W1＿1。
变化例2中，同样地，同时形成通孔触点V1＿1及焊垫P1＿1a。因此，变化例2能够利用比第1实施方式少的工序形成焊垫P1＿1a。变化例2的其它形成工序可与第1实施方式相同。因此，本变化例2能够获得与第1实施方式相同的效果。此外，使用由变化例2形成的焊垫P1＿1a的实施方式将参照图25在下文叙述。
(变化例3)图20A～图20F是表示电路芯片CH＿C1的贯通电极TSV1的区域的形成工序的另一例的剖视图。在该变化例中，在形成CMOS电路并使衬底SUB1反转之后，形成贯通电极TSV1。
首先，将未图示的CMOS电路形成在衬底SUB1上，在其上堆积层间绝缘膜ILD1＿2。由此，获得图20A所示的构造。
接下来，如图20B所示，使用光刻技术及蚀刻技术在贯通电极TSV1的形成区域形成孔。
接下来，如图20C所示，在该孔的内壁成膜间隔绝缘膜SP1，并进行回蚀，由此将处于孔底部的间隔绝缘膜SP1去除。
接下来，如图20D所示，使用镀覆法等，在间隔绝缘膜SP1的内侧填埋贯通电极TSV1的材料。
这样，贯通电极TSV1在形成CMOS电路之后形成。因此，由于在CMOS电路的高温热处理之后形成贯通电极TSV1，所以贯通电极TSV1的材料(例如，铜、钨)能够使用镀覆法成膜。
接下来，使用CMP法，对贯通电极TSV1的材料进行研磨，直到间隔绝缘膜SP1的表面露出为止。由此，如图20E所示，贯通电极TSV1形成在衬底SUB1内。贯通电极TSV1在利用间隔绝缘膜SP1与衬底SUB1电绝缘的状态下，贯通衬底SUB1。
接下来，如图20F所示，形成再配线层RW1。接下来，在再配线层RW1上形成焊垫P1＿2b。焊垫P1＿2b的构成及形成方法如参照图3A～图11所说明那样。
然后，将存储器芯片40＿1、40＿2贴合。由此，如图2所示，焊垫P1＿2b与焊垫P2＿1b被贴合。
此外，当在阵列芯片CH＿A1设置着贯通电极的情况下，阵列芯片CH＿A1的贯通电极也可与本变化例同样地形成。
(第2实施方式)图21是表示第2实施方式的焊垫P1＿2a的构成例的俯视图。像第1实施方式一样，在焊垫P1＿1a与焊垫P1＿2a为相同构成的情况下，如果在图4的X方向上使焊垫P1＿1a与焊垫P1＿2a相对偏移，那么担心导电性材料102＿1a与绝缘性材料103＿2a对向，导电性材料102＿2a与绝缘性材料103＿1a对向。在该情况下，担心导电性材料102＿1a与导电性材料102＿12a的接触面积变得极小，焊垫P1＿1a与焊垫P1＿2a的接触电阻变高，且变得不稳定。
相对于此，在第2实施方式中，在从Z方向观察的俯视时，焊垫P1＿2a的绝缘性材料103＿2a在相对于X及Y方向倾斜的方向上延伸。焊垫P1＿1a的构成可与第1实施方式的焊垫P1＿1a的构成相同。
图22是表示第2实施方式的接合面B＿mc1的区域的构成例的剖视图。在第2实施方式中，在将阵列芯片CH＿A1与电路芯片CH＿C1贴合时，焊垫P1＿1a与焊垫P1＿2a在接合面B＿mc1中，以绝缘性材料103＿1a的延伸方向(例如，Y方向)与绝缘性材料103＿2a的延伸方向(相对于X及Y方向倾斜的方向)交叉的方式接合。此外，沿着图21的B-B线的截面表示为图22的焊垫P1＿2a。
从与衬底垂直的方向观察，彼此分离的多个绝缘性材料103＿1a与导电性材料102＿2a一部分重叠，分离的多个绝缘性材料103＿2a与导电性材料102＿1a一部分重叠。
由于绝缘性材料103＿1a的延伸方向与绝缘性材料103＿2a的延伸方向交叉，所以即便焊垫P1＿1a与焊垫P1＿2a在X或Y方向上某程度地偏移，导电性材料102＿1a与导电性材料102＿2a的接触面积也不那么降低。因此，第2实施方式中，能够相对于接合面B＿mc1中的焊垫P1＿1a与焊垫P1＿2a的偏移使接触电阻低且稳定。
(第3实施方式)
图23是表示第3实施方式的焊垫P1＿1a的构成例的俯视图。在第2实施方式中，在从Z方向观察的俯视时，焊垫P1＿1a的导电性材料102＿1a在层间绝缘膜ILD1＿1的表面，具有包括在X方向上延伸的细长形状与在Y方向上延伸的细长形状的网眼构造。因此，在从Z方向观察的俯视时，绝缘性材料103＿1a在层间绝缘膜ILD1＿1的表面形成为岛屿状(点状)，在X方向及Y方向上呈矩阵状二维排列。在将绝缘材料103＿1a的一个设为第1绝缘部In1＿1时，会形成与所述第1绝缘部In1＿1在Y方向上排列且最接近的第2绝缘部In2＿1、及与所述第1绝缘部In1＿1在X方向上排列且最接近的第3绝缘部In3＿1。
绝缘性材料103＿1a由蚀刻速率比导电性材料102＿1a的材料(例如，铜或钨等金属材料)低的材料(例如，氧化硅膜)形成。例如，绝缘性材料103＿1a也可以由比导电性材料102＿1a的材料更难研磨的物理上较硬的材料形成。或者，绝缘性材料103＿1a也可以由比导电性材料102＿1a的材料更难利用研磨剂(浆料)进行化学蚀刻的材料形成。因此，在CMP工序中，绝缘性材料103＿1a在导电性材料102＿1a的内侧成为支柱，能够缓和导电性材料102＿1a的碟状变形。
另外，焊垫P1＿2a也具有与图23的焊垫P1＿1a相同的构成。因此，虽然未图示，但是焊垫P1＿2a同样地，在从Z方向观察的俯视时，导电性材料102＿2a在层间绝缘膜ILD1＿2的表面中，具有包括在X方向上延伸的细长形状与在Y方向上延伸的细长形状的网眼构造。也就是说，在从Z方向观察的俯视时，绝缘性材料103＿2a在层间绝缘膜ILD1＿2的表面形成为岛屿状(点状)，在X方向及Y方向上呈矩阵状二维排列。因此，在CMP工序中，绝缘性材料103＿2a在导电性材料102＿2a的内侧成为支柱，能够缓和导电性材料102＿2a的碟状变形。
由此，能够使导电性材料102＿1a与导电性材料102＿2a之间的接触电阻低且稳定。
此外，第3实施方式也可以与第1实施方式、第2实施方式、变化例1、变化例2的任一者组合。也就是说，也可以使第3实施方式的焊垫P1＿1a与第1实施方式、第2实施方式、变化例1、变化例2的任一者的焊垫P1＿2a接合。
另外，第3实施方式也可以用于存储器芯片40＿1、40＿2间的接合。也就是说，第3实施方式也可以应用于存储器芯片40＿1的焊垫P1＿2b与存储器芯片40＿2的焊垫P2＿1b。由此，能够抑制焊垫P1＿2b及焊垫P2＿1b的碟状变形，且存储器芯片40＿1、40＿2间的接合也以低电阻稳定化。
(第4实施方式)
图24是表示第4实施方式的焊垫P1＿2a的构成例的俯视图。在第4实施方式中，在从Z方向观察的俯视时，焊垫P1＿2a的导电性材料102＿2a在相对于X及Y方向倾斜的方向上延伸。焊垫P1＿1a的构成可与第1～第3实施方式、变化例1、2的任一者相同。第3实施方式的焊垫P1＿1a中在X方向、Y方向上最接近的点状绝缘性材料的距离，与像第4实施方式一样倾斜的情况下在X方向、Y方向上最接近的点状绝缘性材料的距离不同。例如，在将绝缘材料103＿2a的一个设为第4绝缘部In4＿2时，会形成与所述第4绝缘部In4＿2在Y方向上排列且最接近的第5绝缘部In5＿2、及与所述第4绝缘部In4＿2在X方向上排列且最接近近的第6绝缘部In6＿2。在Y方向观察时的第1绝缘部In1＿1与第2绝缘部In2＿1的距离比第4绝缘部In4＿2与第5绝缘部In5＿2的距离近。在X方向观察时的第1绝缘部In1＿1与第3绝缘部In3＿1的距离比第4绝缘部In4＿2与第6绝缘部In6＿2的距离近。
在第4实施方式中，在将阵列芯片CH＿A1与电路芯片CH＿C1贴合时，焊垫P1＿1a与焊垫P1＿2a在接合面B＿mc1中，以导电性材料102＿1a的延伸方向与导电性材料102＿2a的延伸方向交叉的方式接合。由于绝缘性材料103＿1a的延伸方向与绝缘性材料103＿2a的延伸方向交叉，所以即便焊垫P1＿1a与焊垫P1＿2a在X或Y方向上某程度地偏移，导电性材料102＿1a与导电性材料102＿2a的接触面积也不那么变化。因此，第4实施方式能够相对于接合面B＿mc1中的焊垫P1＿1a与焊垫P1＿2a的偏移使接触电阻稳定化。
第4实施方式的其它构成可与第1～第3实施方式的对应的构成相同。因此，第4实施方式也能够获得第1～第3实施方式的任一者的效果。
(第5实施方式)图25是表示第5实施方式的接合面B＿mc1的区域的构成例的剖视图。在第5实施方式中，使用由所述变化例2形成的焊垫P1＿1a、P1＿2a。
在第5实施方式中，通孔触点V1＿1设置在焊垫P1＿1a的下方，且共通地电连接于导电性材料102＿1a。通孔触点V1＿1将导电性材料102＿1a电连接于配线层W1＿1。这样，通孔触点V1＿1与导电性材料102＿1a作为一体设置在焊垫P1＿1a的整个形成区域。由此，焊垫P1＿1a的导电性材料102＿1a因通孔触点V1＿1及导电性材料102＿1a的体积膨胀(热膨胀)而从接合面B＿mc1稍微鼓起。
另外，关于焊垫P1＿2a也同样地，通孔触点V1＿2设置在焊垫P1＿2a的下方，且共通地电连接于导电性材料102＿2a。通孔触点V1＿2将导电性材料102＿2a电连接于配线层W1＿2。这样，通孔触点V1＿2也与导电性材料102＿2a作为一体设置在焊垫P1＿2a的整个形成区域。由此，焊垫P1＿2a的导电性材料102＿2a因通孔触点V1＿2及导电性材料102＿2a的体积膨胀(热膨胀)而从接合面B＿mc1稍微鼓起。
通过焊垫P1＿1a、P1＿2a从接合面B＿mc1相互鼓起，接合面B＿mc1中的焊垫P1＿1a、P1＿2a相互确实地接合。由此，焊垫P1＿1a、P1＿2a能够相互以低电阻稳定地连接。
对本发明的几个实施方式进行了说明，但这些实施方式是作为示例而提出的，并不旨在限定发明的范围。这些实施方式能够以其它的各种方式实施，在不脱离发明的主旨的范围内，能够进行各种省略、置换、变更。这些实施方式或其变化包含在发明的范围或主旨中，同样地包含在权利要求书中所记载的发明及与其均等的范围中。

Claims (14)

1.一种半导体装置，其特征在于具备：
衬底，设置着第1半导体电路；
第1焊垫，设置在所述衬底；
第1绝缘层，设置在所述第1焊垫的外侧；
第2焊垫，与所述第1焊垫接合；以及
第2绝缘层，设置在所述第2焊垫的外侧，且与所述第1绝缘层接合；且
所述第1焊垫在所述第1焊垫与所述第2焊垫的接合面，包含第1导电性材料、及设置在所述第1导电性材料的内侧的第1绝缘性材料。
2.根据权利要求1所述的半导体装置，其特征在于：在所述接合面，所述第1绝缘性材料的至少一部分在第1方向延伸。
3.根据权利要求1或2所述的半导体装置，其特征在于：在所述接合面，所述第1绝缘性材料的面积小于所述第1导电性材料的面积。
4.根据权利要求1或2所述的半导体装置，其特征在于：
所述第2焊垫在所述接合面，包含第2导电性材料、及设置在所述第2导电性材料的内侧的第2绝缘性材料。
5.根据权利要求4所述的半导体装置，其特征在于：在所述接合面，所述第2绝缘性材料的至少一部分在第2方向延伸，该第2方向是处于所述接合面内的方向且与所述第1方向不同。
6.根据权利要求1所述的半导体装置，其特征在于：
在所述接合面，
所述第1绝缘性材料包含：
第1绝缘部；
第2绝缘部，与所述第1绝缘部在所述第1方向排列且最接近所述第1绝缘部；以及
第3绝缘部，与所述第1绝缘部在第2方向排列且最接近所述第1绝缘部，所述第2方向是处于所述接合面内的方向且与所述第1方向垂直。
7.根据权利要求6所述的半导体装置，其特征在于：
在所述接合面，
所述第2绝缘性材料包含：
第4绝缘部；
第5绝缘部，与所述第4绝缘部在所述第1方向排列且最接近所述第4绝缘部；以及
第6绝缘部，与所述第4绝缘部在所述第2方向排列且最接近所述第4绝缘部；且
将与所述第1绝缘部在所述第1方向最接近的所述第2绝缘部的距离设为第1距离，
将与所述第4绝缘部在所述第1方向最接近的所述第5绝缘部的距离设为第2距离时，
所述第1距离与所述第2距离不同。
8.根据权利要求1所述的半导体装置，其特征在于：
所述第1半导体电路包含存储单元阵列与控制所述存储单元阵列的CMOS电路的任一者，且
在隔着所述接合面而与所述第1半导体电路相反方向侧，还具备第2半导体电路，所述第2半导体电路包含所述存储单元阵列与控制所述存储单元阵列的CMOS电路的另一者。
9.根据权利要求1所述的半导体装置，其特征在于：
所述第1半导体电路包含第1存储单元阵列与控制所述第1存储单元阵列的第1CMOS电路，且
在隔着所述接合面而与所述第1半导体电路相反方向侧，还具备第2半导体电路，所述第2半导体电路包含第2存储单元阵列与控制所述第2存储单元阵列的第2CMOS电路。
10.根据权利要求1所述的半导体装置，其特征在于：
所述第1绝缘层与所述第1绝缘性材料同时形成。
11.根据权利要求1所述的半导体装置，其特征在于：
所述第1绝缘层及所述第1绝缘性材料包含氧与硅，
所述第1导电性材料包含铜、金、或铜及金。
12.一种半导体装置的制造方法，其特征在于：
在第1衬底设置第1半导体电路；
设置覆盖所述第1半导体电路的第1膜；
在所述第1膜，以在第1凹部的周围形成第1绝缘层，且在所述第1凹部的内侧形成第1绝缘性材料的方式，形成所述第1凹部；
在所述第1凹部设置第1导电材料；
以露出所述第1绝缘层的表面及所述第1绝缘性材料的表面的方式研磨所述第1导电材料；
在第2衬底设置第2半导体电路；
设置覆盖所述第2半导体电路的第2膜；
在所述第2膜，以在第2凹部的周围形成第2绝缘层的方式，形成所述第2凹部；
在所述第2凹部设置第2导电材料；
以露出所述第2绝缘层的表面的方式研磨所述第2导电材料；以及
将所述第1绝缘层与所述第2绝缘层接合，将所述第1导电材料与所述第2导电材料接合。
13.根据权利要求12所述的半导体装置的制造方法，其特征在于：
在形成所述第2凹部时，在所述第2凹部的内侧形成第2绝缘性材料，
在以露出所述第2绝缘层的表面的方式研磨所述第2导电材料时，也露出所述第2绝缘性材料的表面。
14.根据权利要求13所述的半导体装置的制造方法，其特征在于：
所述第1绝缘性材料包含各自分离的多个第1部，
所述第2绝缘性材料包含各自分离的多个第2部，
从与所述第1衬底垂直的方向观察，所述多个第1部与所述第2导电材料重叠，
所述多个第2部与所述第1导电材料重叠。
CN202210124124.5A 2021-05-21 2022-02-10 半导体装置 Pending CN115377039A (zh)

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