TWI812926B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI812926B
TWI812926B TW110106298A TW110106298A TWI812926B TW I812926 B TWI812926 B TW I812926B TW 110106298 A TW110106298 A TW 110106298A TW 110106298 A TW110106298 A TW 110106298A TW I812926 B TWI812926 B TW I812926B
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Taiwan
Prior art keywords
electrode
wire
semiconductor device
conductive layer
semiconductor
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TW110106298A
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English (en)
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TW202220130A (zh
Inventor
長谷川一磨
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日商鎧俠股份有限公司
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Publication of TW202220130A publication Critical patent/TW202220130A/zh
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Publication of TWI812926B publication Critical patent/TWI812926B/zh

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Abstract

實施方式提供一種能夠抑制接合焊針等連接機構與其他導線干涉之問題的半導體裝置。 實施方式之半導體裝置具備：基板，其具有第1面；第1半導體晶片，其設置於第1面，且設置有第1電極、第2電極、及第3電極；樹脂，其覆蓋第1面與第1半導體晶片，具有與第1面對向之第2面及位於第2面之相反側之第3面；第1導線，其連接於第1電極，且自第3面露出；第2導線，其連接於第2電極，且自第3面露出；第3導線，其連接於第1面，且自第3面露出；及第4導線，其將第1面與第3電極連接；第3電極形成於第1電極與第2電極之間。

Description

半導體裝置
所揭示之實施方式係關於一種半導體裝置。
例如，半導體裝置具備積層之複數個半導體晶片。藉由在各半導體晶片接合導線，能夠進行資訊之授受。若積層之半導體晶片數量變多，則積層體變厚，需要與其對應之高度之導線。
由於打線接合機之接合焊針之前端形狀為圓錐形，故於接合時，可能產生焊針與其他導線干涉之問題。
本發明提供一種能夠抑制接合焊針等連接機構與其他導線干涉之問題之半導體裝置。
本發明之半導體裝置具備：基板，其具有第1面；第1半導體晶片，其設置於第1面，且設置有第1電極、第2電極、及第3電極；樹脂，其覆蓋第1面與第1半導體晶片，具有與第1面對向之第2面及位於第2面之相反側之第3面；第1導線，其連接於第1電極，且自第3面露出；第2導線，其連接於第2電極，且自第3面露出；第3導線，其連接於第1面，且自第3面露出；及第4導線，其將第1面與第3電極連接；第3電極形成於第1電極與第2電極之間。
以下，一面參照隨附圖式一面對本實施方式進行說明。為了容易理解說明，於各圖式中對相同之構成要素儘可能標註相同之符號，並省略重複說明。
圖1A係模式性地表示第1實施方式之半導體裝置10之一部分之立體圖。圖1B係圖1A中之區域AR之放大圖。圖2A係模式性地表示半導體裝置10之剖面之剖視圖，圖2B係通過形成於支持體40之第1電極層42之開口OP的剖面中之半導體裝置10之模式性剖視圖。
半導體裝置10具備積層之複數個半導體晶片20(以下，有時將積層之複數個半導體晶片稱為「積層體」)。於圖1A至圖2B中，為了容易理解說明，示出了其中2片半導體晶片20積層之情況。進而，半導體裝置10具備：複數條第1導線W1，其等係一端連接於半導體晶片20且至少延伸至積層體30之上端之高度；及複數條第2導線W2，其等將2個半導體晶片20彼此相互連接。如下所述，第1導線W1之另一端連接於配設在積層體30上方之再配線層50(「基板」之一例，圖3J)。再者，本發明中之上方(圖2A等中之紙面上方向)、下方(圖2A等中之紙面下方向)、水平方向(圖2A等中之紙面左右或垂直方向)等表示方向之語句用以方便表示相對之位置關係。
本實施方式之半導體裝置10進而具備：支持體40，其支持積層體30；複數條第3導線W3，其等係一端連接於支持體40，朝相對於「作為基板之」支持體40之表面大致垂直之方向豎立設置，且另一端連接於再配線層50；及複數條第4導線W4，其等將支持體40與半導體晶片20連接。
半導體晶片20例如由形成為各邊數mm之矩形板狀之矽基板形成。於半導體晶片20之上表面設置有複數個電極20T。各電極20T例如由外部連接墊構成，該外部連接墊用以經由形成於鈍化膜之開口將半導體晶片20與外部機器電性連接，上述鈍化膜覆蓋半導體晶片20之表面。如圖1A所示，複數個電極20T於未被積層於上方之半導體晶片20覆蓋之端部排列成一行。
半導體晶片20例如係具備三維地設置之記憶胞陣列之三維積層型NAND(Not And，反及)型快閃記憶體晶片(以下，有時稱為「半導體記憶體晶片」)。半導體記憶體晶片20M進而具備I/O(Input/Output，輸入/輸出)介面電路、控制電路、電壓產生電路、感測放大器、行解碼器、資料鎖存器、及列解碼器等周邊電路。
半導體記憶體晶片20M分別具備複數個用以對I/O介面電路等供給大致固定之電位之VCCQ端子20TC、用以供給接地電位之VSS端子20TS、用以輸入輸出資料之I/O端子20TI、用以供給命令鎖存賦能等控制信號之控制端子，作為電極20T。又，至少一部分I/O端子20TI隔在VSS端子20TS及VCCQ端子20TC之間設置。
此種半導體記憶體晶片20M積層而構成積層體30。半導體記憶體晶片20M相對於正下方之半導體記憶體晶片20M向特定方向位移，呈階梯狀積層，以使於上表面之端部形成為一行之電極20T露出。半導體記憶體晶片20M彼此例如利用由包含丙烯酸聚合物與環氧樹脂之材料形成之晶粒接合膜(Die Attach Film)22而相互接著。再者，亦可使用除晶粒接合膜以外之接著劑等，將半導體記憶體晶片20M彼此接著。
進而，於最上層之半導體記憶體晶片20M上，積層用以控制複數個半導體記憶體晶片20M之控制器晶片(圖3D，以下，有時稱為「介面晶片」)20C。控制器晶片20C接收來自供半導體裝置10連接之主機裝置等外部機器(未圖示)之命令，按照該命令使半導體記憶體晶片20M讀取資訊，或使半導體記憶體晶片20M記錄資訊。於控制器晶片20C之上表面，例如，二維地排列形成有複數個電極。例如，如圖3G所示，積層體30包含8片半導體記憶體晶片20M及積層於半導體記憶體晶片20M上之1片控制器晶片20C。
於積層於積層體30之最上層之控制器晶片20C上表面所設置之複數個電極，設置有自控制器晶片20C之上表面(積層體之上表面)向上方突出且形成為圓柱狀之由銅柱構成之端子(以下，有時稱為「銅柱端子」)32(圖3D)。控制器晶片20C經由銅柱端子32進行信號之收發。可根據晶片尺寸及焊墊數量、電極數量使用銅柱，亦可使用導線。又，與連接於半導體記憶體晶片20M之電極之第1導線W1等相比，銅柱端子32於上下方向上形成得較短。例如，銅柱端子32之高度為10 μm至300 μm。
支持體40係於形成積層體30時支持半導體晶片20之基體。如圖2A所示，例如，支持體40藉由具備包括第2電極層44(「電極層」之一例)、設置於第2電極層44上且作為介電體發揮功能之絕緣層46、及設置於絕緣層46上之第1電極層42(「電極層」之一例)之3層構造，而作為具備隔著介電體具有電位差之第1電極層42及第2電極層44之電容器(電容)發揮功能。第1電極層42及第2電極層44可遍及支持體40之整個面形成，亦可形成於其一部分。例如，較佳為，以於俯視時設置有積層體30之區域與形成有第1電極層42及第2電極層44之區域於至少一部分重疊之方式形成。進而，於第1電極層42形成有複數個開口OP，於開口OP處，露出第2電極層44。
第1導線W1將半導體記憶體晶片20M之電極20T與配設於積層體30之上方之再配線層50(圖3J)電性連接。第1導線W1在相對於半導體記憶體晶片20M之表面大致垂直之方向豎立設置，下端連接於半導體記憶體晶片20M之電極20T，且朝上方向延伸，上端電性連接於作為設置於再配線層50上之凸塊電極70(圖3J)之一的第1外部電極。例如，將第1導線W1之下端與上端連接之直線、與第1導線W1所連接之半導體記憶體晶片20M表面之法線所成之角度為20度以內。第1導線W1由金等導電性金屬設置。第1外部電極用於半導體記憶體晶片之輸入輸出信號之互換。
第2導線W2將鄰接之半導體記憶體晶片20M之電極彼此電性連接。由於第2導線W2連接之2個電極20T均朝向相同之方向(上方)，故第2導線W2如圖2A所示設置成環狀，即，以向上方延伸後彎曲而向下方延伸之方式設置。
第3導線W3將支持體40之電極與配設於較積層體30更靠上方之再配線層50電性連接。第3導線W3於相對於支持體之表面大致垂直之方向豎立設置。如圖1A等所示，複數條第3導線W3中之一部分即第3導線W31之下端連接於作為支持體40之電極的第1電極層42，且向上方延伸，上端連接於再配線層50。第3導線W31與作為設置於再配線層50上之凸塊電極70(圖3J)之一的第2外部電極電性連接，將相當於VCCQ之電壓供給至第1電極層42。
複數條第3導線W3中之另一部分即第3導線W32之下端連接於作為支持體40之電極的第2電極層44，且向上方延伸，上端連接於再配線層50。第3導線W32與作為設置於再配線層50上之凸塊電極70之一的第3外部電極電性連接，將相當於VSS之接地電位供給至第2電極層44。該等第3導線W3由直徑較第1導線W1大之導電性金屬形成。
第4導線W4將支持體40之電極與半導體記憶體晶片20M之電極20T電性連接。複數條第4導線W4中之一部分即第4導線W41之一端連接於作為支持體40之電極的第1電極層42，另一端連接於作為半導體記憶體晶片20M之電極20T的VCCQ端子20TC。
複數條第4導線W4中之另一部分即第4導線W42之一端連接於作為支持體40之電極的第2電極層44，另一端連接於作為半導體記憶體晶片20M之電極的VSS端子20S。由於該等第4導線W4連接之2個電極均朝向相同之方向(上方)，故第4導線W4如圖2B所示設置成環狀。
如圖1B所示，於本實施方式之半導體裝置10中，連接於同一半導體記憶體晶片20M之複數條第1導線W1中，在至少一部分第1導線W1及與其鄰接之第1導線W1之間，設置有呈環狀設置之第2導線W2。即，設置於同一半導體記憶體晶片20M之電極20T中，第2導線W2所連接之電極20T隔在鄰接之兩條第1導線W1所連接之兩個電極20T之間。同樣地，在至少一部分第1導線W1及與其鄰接之第1導線W1之間，設置有呈環狀設置之第4導線W4。即，同一半導體記憶體晶片20M上之電極20T中，第4導線W4所連接之電極20T隔在鄰接之兩條第1導線W1所連接之兩個電極20T之間。例如，鄰接之兩條第1導線W1分別連接於半導體記憶體晶片20M之2個I/O端子20TI。又，於該I/O端子20TI之間，設置有第4導線W4所連接之VCCQ端子20TC。該第4導線W4之另一端連接於第1電極層42。
於該VCCQ端子20TC進而連接有第2導線W2，且第2導線W2連接於一個上層之半導體記憶體晶片20M之VCCQ端子20TC。藉由如此構成，可經由第3導線W3對支持體40供給電源，進而，利用連接於支持體40之第4導線W4及將半導體記憶體晶片20M間連接之複數條第2導線W2，對各半導體記憶體晶片20M之VCCQ端子20TC供給電源。於半導體記憶體晶片20M附近，設置有作為電容發揮功能之支持體40，故而即便於經由I/O端子20TI收發高頻信號之情形時，亦能夠降低由此引起而可能於VCCQ端子20TC產生之電源雜訊之影響。另外，由於利用第1導線W1將I/O端子20TI與再配線層50連接，故而與經由環狀導線之情形相比，能夠實現通信速度之高速化。
進而，關於同一半導體記憶體晶片20M，在鄰接之第1導線W1間設置環狀之第2導線W2或第3導線W3，藉此能夠擴大鄰接之第1導線W1之間隔，故而於接合第1導線W1時，能夠抑制接合焊針等連接機構與其他導線干涉之問題。
例如，若鄰接之導線之間隔變窄，則於接合導線時，接合焊針等連接機構與其他導線干涉之風險增加。為了避免干涉，必須減小導線之高度。例如，若將鄰接之導線之間隔設為70 μm，則導線之高度必須為200 μm以下。
然而，本實施方式之半導體裝置10藉由在連接於同一半導體記憶體晶片20M之鄰接之2條第1導線W1之間連接環狀之第2導線W2或第4導線W4，而能夠擴大鄰接之第1導線W1之間隔(例如，100 μm以上)。因此，能夠抑制接合焊針等連接機構與其他導線干涉之問題。其結果，能夠提供第1導線W1之高度增大且半導體記憶體晶片20M之積層數量增加之半導體裝置10。
同樣地，於鄰接之第1導線W1所連接之2個I/O端子20TI之間，可設置供第4導線W4連接之VSS端子20TS。又，可於該VSS端子20TS進而連接第2導線W2，且於上一層之半導體記憶體晶片20M之VSS端子20TS連接該第2導線W2。藉由如此構成，能夠經由第3導線W3對支持體40供給接地電位，且藉由連接於支持體40之第4導線W4及連接半導體記憶體晶片20M間之複數條第2導線W2，對各半導體記憶體晶片20M之VSS端子20TS供給接地電位。由於在半導體記憶體晶片20M附近設置有作為電容發揮功能之支持體40，故而即便於經由I/O端子20TI收發高頻信號之情形時，亦能夠降低由此引起而可能於VSS端子20TS產生之雜訊之影響。
另外，支持體40之第1電極層42及第2電極層44亦作為防護層發揮功能。尤其，於俯視時，設置有半導體晶片20之區域與形成有第1電極層42及第2電極層44之區域至少一部分重疊之情形時，能夠較佳地進行防護而避免自半導體晶片20產生之電磁波洩漏至較支持體40更下方。進而，亦能夠較佳地防護半導體裝置10使其不受自其他裝置等產生之電磁波影響。例如，於將半導體裝置10安裝於印刷配線基板之情形時，能夠較佳地防護半導體裝置10，使其不受因高頻信號而自配線等產生之電磁波影響。
半導體裝置10亦可具備密封樹脂60(圖3I)。密封樹脂60以被覆第1導線W1、第2導線W2、第3導線W3、第4導線W4、積層體30及銅柱端子32之方式，設置於支持體40上。惟，第1導線W1、第3導線W3及銅柱端子32之上端因與再配線層50連接，而自密封樹脂60露出。
第1導線W1、第3導線W3及銅柱端子32之上端亦可連接於再配線層50。於本實施方式之半導體裝置10中，於自積層體30朝上方離開之位置(例如，自積層體30之上表面朝上方離開相當於銅柱端子32之高度的數100 μm之位置)設置再配線層50。再配線層50將設置於再配線層50上之凸塊電極70與第1導線W1、第3導線W3及銅柱端子32分別電性連接。再配線層50例如具備複數個絕緣層、以及形成於各絕緣層內之配線及將配線間連接之通孔。絕緣層例如由聚合物材料設置，配線及通孔例如由銅設置。再配線層係作為於將凸塊電極70安裝於印刷配線基板等時支持密封樹脂60及由其被覆之積層體30的基板發揮功能。本實施方式中之再配線層50於俯視時形成得較積層體30大，故而半導體裝置10具有扇出型晶圓級晶片尺寸封裝(WLCSP)構造。於再配線層50上形成複數個凸塊電極70(圖3J)。凸塊電極70例如係將複數個球狀之凸塊電極二維排列而成之BGA(Ball Grid Array，球柵陣列)。又，亦可於自密封樹脂60露出之第1導線W1、第3導線W3及銅柱端子32之上端直接形成凸塊電極70，將其作為再配線層50。
具備此種構成之半導體裝置10例如藉由安裝於主機裝置等外部機器之印刷配線基板，可按照經由BGA自外部機器接收之命令，自半導體記憶體晶片20M讀取資訊，或使自外部機器接收之資訊記錄於半導體記憶體晶片20M。
[半導體裝置之製造方法] 對具備如上構成之半導體裝置10之製造方法進行說明。首先，如圖3A所示，提供支持體40。如該圖所示，支持體40之第1電極層42及第2電極層44可形成於支持體40之整個面。但是，支持體40之第1電極層42及第2電極層44之至少一部分亦可由樹脂等覆蓋。繼而，如圖3B所示，於支持體40之第1電極層42形成複數個開口OP。藉由開口OP將第1電極層42及絕緣層46去除，故而第2電極層44露出。
繼而，如圖3C所示，積層複數個半導體記憶體晶片20M。如上所述，半導體記憶體晶片20M係相對於正下方之半導體記憶體晶片20M向特定方向位移而積層。因此，形成於半導體記憶體晶片20M端部之複數個電極20T不被上層之半導體記憶體晶片20M覆蓋，自與半導體記憶體晶片20M之表面垂直之方向觀察時之俯視時能夠被視認。各半導體記憶體晶片20M藉由晶粒接合膜22而接著於下層之半導體記憶體晶片20M或支持體40。
然後，如圖3D所示，於最上層之半導體記憶體晶片20M之上積層控制器晶片20C而設置積層體30。於控制器晶片20C之複數個電極，預先設置有向上方突出且形成為圓柱狀之由銅柱構成之銅柱端子32。銅柱端子32例如能夠藉由鍍覆製程而形成。但是，亦可代替銅柱端子32，將導線及其他導電體以向上方突出之方式設置於積層體30之最上層之半導體晶片20之電極。再者，控制器晶片20C藉由晶粒接合膜22而接著於最上層之半導體記憶體晶片20M。此處，存在如下情形：若半導體記憶體晶片20M之積層數量變多，則因半導體記憶體晶片20M及晶粒接合膜22之公差影響，積層體30之高度發生變動。因此，亦可執行如下步驟：基於積層體30之高度，來決定連接於最上層之半導體晶片20之導線、銅柱端子及其他導電體之長度。於執行該步驟之情形時，然後執行將已決定之長度之導電體設置於最上層之半導體晶片20之電極上之步驟。繼而，如圖3E所示，藉由打線接合機將第2導線W2及第4導線W4接合。藉由該工序，將各半導體記憶體晶片20M之VCCQ端子與支持體40之第1電極層42電性連接。又，將各半導體記憶體晶片20M之VSS端子20TS與支持體40之第2電極層44電性連接。
然後，如圖3F所示，藉由打線接合機將第1導線W1接合於半導體記憶體晶片20M之電極20T(例如，I/O端子及控制端子)。第1導線W1係使用打線接合機等並利用施加超音波或熱之公知技術，使構成第1導線W1之金屬(例如，金)擴散，藉此連接於半導體記憶體晶片20M之電極20T。第1導線W1向上方延伸至與銅柱端子32之上端相當之高度之後，例如，使用全切方式等公知技術被切斷。
此時，第1導線W1之下端連接於半導體記憶體晶片20M之電極20T，且向上方向延伸，上端成為自由端。第1導線W1之上端大致成為與銅柱端子32之上端相等之高度。
第2導線W2及第4導線W4由於設置成環狀，故於接合第1導線W1時不會成為較大之阻礙。又，如上所述，關於同一半導體記憶體晶片20M，構成為於至少一部分鄰接之第1導線W1間接合第2導線W2或第4導線W4，故能夠增大鄰接之第1導線W1之間隔，因此，能夠抑制於接合第1導線W1時接合焊針等連接機構與周圍之第1導線W1干涉之問題。其結果，能夠增大第1導線W1之高度，進而增加半導體記憶體晶片20M之積層數量(於本實施方式中為8層)。
繼而，如圖3G所示，與第1導線W1同樣地，藉由打線接合機將複數條第3導線W3分別接合於支持體40之第1電極層42及第2電極層44。第3導線W3於向上方延伸至與銅柱端子32之上端相當之高度之後，被切斷。
此時，第3導線W3之下端連接於支持體40，且向上方向延伸，上端成為自由端。第3導線W3之上端大致成為與銅柱端子32之上端及第1導線W1之上端相等之高度。如該圖所示，較佳為第3導線W3之直徑大於第1導線W1之直徑。藉由增大第3導線W3之直徑，能夠將穩定之電源(或接地電位)供給至支持體40。但是，亦可將第3導線W3與第1導線W1之直徑設為相同直徑。
然後，如圖3H所示，以被覆第1導線W1、第2導線W2、第3導線W3、第4導線W4及積層體30之方式，於支持體40上設置密封樹脂60。密封樹脂60例如係含有氧化鋁、氧化矽、氫氧化鋁、氮化鋁中之任一種填料之塑模樹脂。
繼而，如圖3I所示，利用磨石等對密封樹脂60進行研削(研磨)，使第1導線W1、第3導線W3及銅柱端子32之各上端露出。此時，亦可將露出之導線或柱之上端設為「外部電極」。
然後，如圖3J所示，於密封樹脂60上，形成再配線層50(「基板」之一例)及設置於再配線層50上之凸塊電極70。再配線層50以將第1導線W1、第3導線W3及銅柱端子32之各上端與BGA之各凸塊電極70電性連接之方式設置。再配線層50之配線及通孔例如藉由鍍銅而形成。
根據如上之半導體裝置10，由於具備連接於一個半導體晶片20且至少延伸至積層體30上端之高度之第1導線W1、以及將兩個半導體晶片20相互連接之第2導線W2，故與設置垂直於所有電極延伸之導線之情形相比，能夠抑制於接合第1導線W1時連接機構與其他導線干涉之問題。又，藉由將第1導線W1之上端與再配線層50或其他電極等連接，能夠實現通信速度之高速化。
再者，亦可代替形成再配線層50而採用覆晶構造，該覆晶構造係於使圖3I所示之第1導線W1等之上端露出之上表面的面朝下，將第1導線W1、第3導線W3、銅柱端子32之上端壓抵於形成在配線基板上之凸塊電極等電極之狀態下，藉由施加荷重與超音波而使電極熔融，使第1導線W1等連接於電極。或者，亦可於第1導線W1、第3導線W3、銅柱端子32之上端形成凸塊電極之後，使凸塊電極連接於形成在配線基板上之電極。
進而，支持體40亦可供給其他電位或信號。例如，亦可為第1電極層42供給VCC電源，第2電極層44供給VCCQ電源。進而，支持體40亦可設為3層以上之構造。於設為3層構造之情形時，支持體40除了具備第1電極層42、絕緣層46及第2電極層44以外，亦可具備第2絕緣層、及與第2電極層44隔著第2絕緣層之第3電極層。亦可對各電極層供給不同電位之電源。再者，積層體30亦可不具備控制器晶片20C。於該情形時，亦可構成為於控制器晶片設置BGA等電極，能夠利用再配線層將該BGA等電極與第1導線W1等連接。進而，亦可將控制器晶片設置於半導體裝置10之外部。
又，如上所述之半導體裝置10之製造方法具有如下步驟：將複數個半導體晶片20積層而設置積層體30；使用第2導線W2將兩個半導體晶片20相互連接；以及將第1導線W1連接於一個半導體晶片20，並使其至少延伸至積層體30上端之高度。
根據此種半導體裝置10之製造方法，與將所有電極連接於第1導線之情形相比，藉由併用第2導線W2與第1導線W1兩者，能夠抑制於接合第1導線W1時接合焊針等連接機構與其他導線干涉之問題。較佳為，於使用第2導線W2將兩個半導體晶片20相互連接之後，將第1導線W1連接於一個半導體晶片20。
再者，亦可應用預先形成再配線層50並配設於密封樹脂60上之RDL(Redistribution Layer，重布層) First法來製造半導體裝置10。
[第2實施方式] 以下，對第2實施方式之半導體裝置10A進行說明。以與第1實施方式不同之部分為中心進行說明，對相同或類似之部分及業者能夠理解之部分標註相同或類似之符號，並且省略或簡化說明。
第2實施方式之半導體裝置10A不具備支持體、第3導線及第4導線。即，半導體裝置10A具備：積層體30，其具備積層之複數個半導體晶片20；第1導線W1，其連接於一個半導體晶片20，且至少延伸至積層體30上端之高度；及第2導線W2，其將兩個半導體晶片20相互連接。
即便為此種構成，藉由併用第1導線W1與第2導線W2，利用第2導線W2將本來連接第1導線W1之電極20T連接，亦能夠擴大至少一部分鄰接之第1導線W1之間隔，故而能夠抑制第1導線W1與其他第1導線W1干涉之問題。
例如，如圖4所示，此種半導體裝置10A可藉由如下方法製造：於支持體40A上積層複數個半導體晶片20而設置積層體30，使用第2導線W2(未圖示)將兩個半導體晶片20相互連接，然後，將第1導線W1連接於至少一個半導體晶片20，並使其至少延伸至積層體30上端之高度之後，藉由研削等將支持體40A去除。該圖模式性地表示將第1導線W1(第2導線未圖示)連接於對支持體40A進行支持之積層體30且將支持體40A去除前之時間點之半導體裝置10A的側面。
再者，於此種半導體裝置10A中，連接於同一半導體晶片20之鄰接之兩條第1導線W1可分別連接於設置在該半導體晶片20之2個端子20T(例如I/O端子20TI)。進而，至少一條第2導線W2可連接於設置在該2個端子20T之間的其他端子20T(例如VCCQ端子20TC或VSS端子20TS)。而且，其他端子20T亦可構成為經由第1導線W1而連接於再配線層50，上述第1導線W1連接於藉由第2導線W2而連接之其他層(例如，最上層)之半導體晶片20之端子20T。藉由此種構成，能夠擴大第1導線W1彼此之間隔。
又，亦可於連接有環狀導線即第2導線W2或第4導線W4之電極20T，進而連接第1導線W1。
[第3實施方式] 以下，對第3實施方式之半導體裝置10B進行說明。第3實施方式之半導體裝置10B就支持體40B之構成與第1實施方式之支持體40不同。圖5A係半導體裝置10B之立體圖。半導體裝置10B之支持體40B如該圖所示，具備如下構成：交替地形成有用以供給固定電位(例如，相當於VCCQ之電位)之區域40B1、及用以供給另一固定電位(例如，接地電位)之區域40B2。區域40B1與區域40B2藉由絕緣層(未圖示)而絕緣。而且，於區域40B1例如連接第3導線W31，於區域40B2連接第3導線W32。根據此種半導體裝置10B，無需設置如支持體40般之層構造，便能夠設置用以對支持體40B供給不同電位之區域。作為半導體裝置10B之變化例，圖5B表示於支持體40C上設置有電容器40C1之半導體裝置10C。如該圖所示，半導體裝置10C於支持體40C之上具備電容器40C1，該電容器40C1具備2個電極層及夾在2個電極層之間的絕緣層。藉由具備此種構成，亦無需設置如支持體40般之層構造，便能夠使用設置成環狀之導線向各半導體晶片20提供不同電位。再者，支持體40C亦可於樹脂密封後被局部或整體去除。
[第4實施方式] 以下，對第4實施方式之半導體裝置10D進行說明。第4實施方式之半導體裝置10D於不具備設置成環狀之導線之方面，與其他實施方式所示之半導體裝置不同。具體而言，半導體裝置10D具備：積層體，其具備積層之複數個半導體晶片20；支持體40，其支持積層體；第1導線W1，其連接於一個半導體晶片20，且至少延伸至積層體上端之高度；及第3導線W3，其連接於支持體40，且至少延伸至積層體上端之高度。第1導線W1連接於包含VCCQ端子20TC、VSS端子20TS、I/O端子20TI之各電極20T。如圖2A所例示，支持體40可具備第1電極層42及第2電極層44。又，第3導線W3亦可具備連接於第1電極層42之第3導線W31、及連接於第2電極層44之第3導線W32。
藉由此種構成之半導體裝置10D，亦能夠使支持體40作為防護層發揮功能。又，由於支持體40構成電容器，故而即便於經由I/O端子20TI收發高頻信號之情形時，亦能夠降低由此引起而可能於VSS端子20TS等產生之雜訊之影響。
以上，參照具體例對本實施方式進行了說明。但是，本發明並不限定於該等具體例。由業者對該等具體例適當增加設計變更所得者只要具備本發明之特徵，則亦包含於本發明之範圍。上述各具體例所具備之各要素及其配置、條件、形狀等並不限定於所例示者，可適當進行變更。上述各具體例所具備之各要素只要不產生技術矛盾，則可適當改變組合。 [相關申請案]
本申請案享有以日本專利申請案2020-137632號(申請日：2020年8月17日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之所有內容。
10:半導體裝置 10A:半導體裝置 10B:半導體裝置 10C:半導體裝置 10D:半導體裝置 20:半導體晶片 20C:控制器晶片 20M:半導體記憶體晶片 20T:電極 20TC:VCCQ端子 20TI:I/O端子 20TS:VSS端子 22:晶粒接合膜 30:積層體 32:銅柱端子 40:支持體 40A:支持體 40B:支持體 40B1:區域 40B2:區域 40C:支持體 40C1:電容器 42:第1電極層 44:第2電極層 46:絕緣層 50:再配線層 60:密封樹脂 70:凸塊電極 AR:區域 OP:開口 W1:第1導線 W2:第2導線 W3:第3導線 W4:第4導線 W31:第3導線 W32:第3導線 W41:第4導線 W42:第4導線
圖1A係模式性地表示第1實施方式之半導體裝置10之立體圖。 圖1B係圖1A中之區域AR之放大圖。 圖2A係模式性地表示半導體裝置10之剖面之剖視圖。 圖2B係模式性地表示半導體裝置10之剖面之剖視圖。 圖3A～J係表示半導體裝置10之製造工序之立體圖。 圖4係模式性地表示第2實施方式之半導體裝置10A之側視圖。 圖5A係模式性地表示第3實施方式之半導體裝置10B之立體圖。 圖5B係模式性地表示第3實施方式之半導體裝置10C之立體圖。 圖5C係模式性地表示第4實施方式之半導體裝置10D之立體圖。
10:半導體裝置
20:半導體晶片
20M:半導體記憶體晶片
30:積層體
44:第2電極層
AR:區域
W1:第1導線
W2:第2導線
W3:第3導線
W4:第4導線
W31:第3導線
W32:第3導線
W41:第4導線
W42:第4導線

Claims (10)

  1. 一種半導體裝置，其具備：基板，其具有第1面；第1半導體晶片，其設置於上述第1面，且設置有第1電極、第2電極、及第3電極；第2半導體晶片，其設置於上述第1半導體晶片上，且形成有第4電極；樹脂，其覆蓋上述第1面與上述第1半導體晶片，具有與上述第1面對向之第2面及位於上述第2面之相反側之第3面；第1導線，其連接於上述第1電極，且自上述第3面露出；第2導線，其連接於上述第2電極，且自上述第3面露出；第3導線，其連接於上述第1面，且自上述第3面露出；第4導線，其將上述第1面與上述第3電極連接；及第5導線，其將上述第3電極與上述第4電極連接；且上述第3電極形成於上述第1電極與上述第2電極之間。
  2. 一種半導體裝置，其具備：基板，其具有第1面；第1半導體晶片，其設置於上述第1面，且設置有第1電極、第2電極、及第3電極；樹脂，其覆蓋上述第1面與上述第1半導體晶片，具有與上述第1面對向之第2面及位於上述第2面之相反側之第3面； 第1導線，其連接於上述第1電極，且自上述第3面露出；第2導線，其連接於上述第2電極，且自上述第3面露出；第3導線，其連接於上述第1面，且自上述第3面露出；及第4導線，其將上述第1面與上述第3電極連接；且上述第3電極形成於上述第1電極與上述第2電極之間，上述基板包含第1導電層及第2導電層，上述第3導線連接於上述第1導電層，上述半導體裝置具備第6導線，該第6導線與上述第2導電層連接，且自上述第3面露出。
  3. 如請求項2之半導體裝置，其具備設置於上述第1導電層與上述第2導電層之間之介電層，於上述第1導電層及上述介電層形成開口，上述第6導線與上述第2導電層之自上述開口露出之部分連接。
  4. 如請求項2之半導體裝置，其具備設置於上述樹脂之上述第3面上方的第1外部電極、第2外部電極、及第3外部電極，上述第1導線與第1外部電極電性連接，上述第3導線與第2外部電極電性連接，上述第6導線與第3外部電極電性連接。
  5. 一種半導體裝置，其具備：基板，其於第1面側設置有第1導電層及與上述第1導電層絕緣之第2 導電層；第1半導體晶片，其設置於上述基板之上述第1面側，且形成有第1電極；樹脂，其覆蓋上述基板之上述第1面與上述第1半導體晶片；第1外部電極、第2外部電極及第3外部電極，其等設置於上述樹脂；第1導線，其將上述第1電極與上述第1外部電極連接；第2導線，其將上述第1導電層與上述第2外部電極連接；及第3導線，其將上述第2導電層與上述第3外部電極連接。
  6. 如請求項5之半導體裝置，其中於上述第1半導體晶片設置有第2電極及第3電極；且上述半導體裝置具備：第4導線，其將上述第1導電層與上述第2電極連接；及第5導線，其將上述第2導電層與上述第3電極連接；上述第1電極位於上述第2電極與上述第3電極之間。
  7. 如請求項6之半導體裝置，其具備：第2半導體晶片，其設置於上述第1半導體晶片之上，且形成有第4電極，及第6導線，其連接上述第2電極與上述第4電極。
  8. 如請求項5之半導體裝置，其具備設置於上述第1導電層與上述第2導電層之間之介電層，於上述第1導電層及上述介電層形成開口， 上述第3導線與上述第2導電層之自上述開口露出之部分連接。
  9. 如請求項4至8中任一項之半導體裝置，其中可對上述第2外部電極供給第1電壓，且可對上述第3外部電極供給與上述第1電壓不同之第2電壓。
  10. 如請求項9之半導體裝置，其中可對上述第1外部電極供給輸入輸出信號，上述第1電壓為驅動電壓或接地電壓中之一者，上述第2電壓為上述驅動電壓或上述接地電壓中之另一者。
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US20180240773A1 (en) * 2015-12-30 2018-08-23 Invensas Corporation Embedded Wire Bond Wires for Vertical Integration With Separate Surface Mount and Wire Bond Mounting Surfaces

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