CN115954329A - 扇出型封装结构及其制造方法 - Google Patents

扇出型封装结构及其制造方法 Download PDF

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Publication number
CN115954329A
CN115954329A CN202111419542.9A CN202111419542A CN115954329A CN 115954329 A CN115954329 A CN 115954329A CN 202111419542 A CN202111419542 A CN 202111419542A CN 115954329 A CN115954329 A CN 115954329A
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Prior art keywords
redistribution layer
upper redistribution
die
fan
layer
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CN202111419542.9A
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Inventor
蔡佩君
徐宏欣
廖敬伟
张简上煜
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Powertech Technology Inc
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Powertech Technology Inc
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    • H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
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    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
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Abstract

本申请公开了一种扇出型封装结构及其制造方法。扇出型封装结构包括：上重布线层、晶粒、无源元件和有源元件。上重布线层包含第一面和相对所述第一面的第二面。晶粒设置在所述上重布线层的所述第一面上且与所述上重布线层电连接。无源元件设置在所述上重布线层的所述第二面上且与所述上重布线层电连接。有源元件设置在所述上重布线层的所述第二面上且与所述上重布线层电连接，其中所述有源元件与所述无源元件横向地相邻，以及所述晶粒通过所述上重布线层与所述有源元件和所述无源元件电连接。本申请通过无源元件的设置，使得可在不增加封装尺寸的前提下实现多个元件之间的电连接。

Description

扇出型封装结构及其制造方法
技术领域
本申请涉及一种半导体领域，特别是关于一种扇出型封装结构及其制造方法。
背景技术
随着半导体技术的快速发展，对于封装结构轻薄化的需求逐渐提升。目前，先进封装主要有两种发展方向，一是减少封装面积，使其接近芯片大小，另一种则是将多个芯片整合在同一封装内，增加封装内部整合程度。因此，对于多芯片的封装结构，如何在不增加封装宽度的前提下实现多个元件之间的电连接，为目前产业界研究的焦点和需解决的技术问题。
有鉴于此，本申请提供一种扇出型封装结构及其制造方法，以解决上述技术问题。
发明内容
为解决上述现有技术的问题，本申请提供一种扇出型封装结构及其制造方法，在不增加封装尺寸的前提下实现多个元件之间的电连接。
在一方面，本申请提供一种扇出型封装结构，包括：上重布线层、晶粒、无源元件和有源元件。上重布线层包含第一面和相对所述第一面的第二面。晶粒设置在所述上重布线层的所述第一面上且与所述上重布线层电连接。无源元件设置在所述上重布线层的所述第二面上且与所述上重布线层电连接。有源元件设置在所述上重布线层的所述第二面上且与所述上重布线层电连接，其中所述有源元件与所述无源元件横向地相邻，以及所述晶粒通过所述上重布线层与所述有源元件和所述无源元件电连接。
在一些实施例中，所述有源元件在所述上重布线层上的正投影与所述晶粒在所述上重布线层上的正投影部分重叠，以及所述无源元件在所述上重布线层上的正投影与所述晶粒在所述上重布线层上的所述正投影重叠。
在一些实施例中，所述上重布线层包含：第一连接垫、多个第二连接垫、第三连接垫、第一导线和第二导线。第一连接垫形成在所述第一面，配置为与所述晶粒连接。多个第二连接垫形成在所述第二面，配置为与所述无源元件连接。第三连接垫形成在所述第二面，配置为与所述有源元件连接。第一导线形成在所述上重布线层内，配置为纵向连接所述第一连接垫和所述多个第二连接垫的其中之一。第二导线形成在所述上重布线层内，配置为横向连接所述多个第二连接垫的其中之一和所述第三连接垫。
在一些实施例中，所述扇出型封装结构还包含：第一绝缘层和第二绝缘层。第一绝缘层设置所述上重布线层的所述第二面上，配置为封装所述无源元件和所述有源元件。第二绝缘层设置在所述晶粒和所述上重布线层上，配置为封装所述晶粒，其中所述第二绝缘层包含开口，且所述晶粒的表面通过所述开口曝露在外部。
在一些实施例中，所述扇出型封装结构还包含：下重布线层和图案化黏胶层。图案化黏胶层设置在所述下重布线层上，其中所述无源元件和所述有源元件的表面通过所述图案化黏胶层与所述下重布线层黏接，以及所述无源元件和所述有源元件的另一表面与所述上重布线层电连接。
在一些实施例中，所述扇出型封装结构还包含：第一导电柱、第二导电柱、和第三导电柱。第一导电柱连接所述上重布线层和所述下重布线层。第二导电柱连接所述无源元件和所述上重布线层。第三导电柱连接所述有源元件和所述上重布线层，其中所述第一导电柱的间距大于或等于所述第三导电柱的间距，且所述第三导电柱的所述间距大于或等于所述第二导电柱的间距。
在一些实施例中，所述扇出型封装结构还包含底胶层，设置在所述上重布线层和所述晶粒之间。
在一些实施例中，所述扇出型封装结构还包含保护环或保护盖，设置在所述上重布线层的所述第一面上且环绕所述晶粒。
在另一方面，本申请还提供一种扇出型封装结构的制造方法，包含：提供下重布线层；形成无源元件和有源元件在所述下重布线层上；形成上重布线层在所述无源元件和所述有源元件上，其中所述无源元件和所述有源元件与所述上重布线层电连接，且所述无源元件和所述有源元件横向地相邻；形成晶粒在所述上重布线层上，其中所述晶粒通过所述上重布线层与所述无源元件和所述有源元件电连接。
在一些实施例中，在形成所述晶粒在所述上重布线层上的步骤中，所述晶粒设置为与所述有源元件部分重叠以及与所述无源元件重叠。
在本申请的扇出型封装结构及其制造方法中，无源元件可为桥接芯片或者是整合有桥接功能的功能芯片。通过无源元件可实现晶粒与有源元件之间的信号传递，使得晶粒与有源元件的设置更加弹性和灵活，且不受限于两者仅仅能采用特定的排列方式。举例来说，通过无源元件的设置，使得晶粒与有源元件可设置在不同的水平高度，并且从一俯视视角观看时，晶粒与有源元件可设置为彼此重叠。因此，在本申请的扇出型封装结构中，在符合封装宽度的条件下，通过无源元件实现了小型化且紧凑设计的多芯片的三维封装，进而为本申请的扇出型封装结构在高端产品的应用提供更多的设计灵活性和自由度。
附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1显示根据本申请第一实施例的扇出型封装结构的示意图。
图2A至图2L显示一系列的剖面图，用于阐明图1的扇出型封装结构的制造流程。
图3显示根据本申请第二实施例的扇出型封装结构的示意图。
图4显示根据本申请第三实施例的扇出型封装结构的示意图。
图5显示根据本申请第四实施例的扇出型封装结构的示意图。
图6显示根据本申请第五实施例的扇出型封装结构的示意图。
具体实施方式
现参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例。相反，提供这些实施方式使得本申请将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。附图仅为本申请的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。
参照图1，其显示根据本申请第一实施例的扇出型封装结构的示意图。扇出型封装结构10包含下重布线层(redistribution layer，RDL)110、图案化黏胶层120、无源元件130、有源元件140、第一绝缘层150、上重布线层160、晶粒170、底胶层180和第二绝缘层190。
如图1所示，下重布线层110包含第一连接面111和第二连接面112，并且第一连接面111和第二连接面112上皆形成有多个连接垫。下重布线层110的第一连接面111通过其对应的连接垫与多个第一导电柱101电连接，以及下重布线层110的第二连接面112通过其对应的连接垫与多个导电端子104电连接。在本实施例中，第一导电柱101的数量为两个，惟不局限于此。第一导电柱101可由铜、铝、锡、金、银或上述的组合所构成。再者，导电端子104可通过使用植球工艺、电镀工艺或其他合适的工艺形成。在一些实施例中，导电端子104是通过植球工艺所形成的焊球，从而降低制造成本并提高制造效率。应当理解的是，根据设计要求，导电端子104可采用其他可能的材料和形状，不局限于此。可选地，通过焊接工艺和回焊工艺以增强导电端子104和下重布线层110的对应连接垫之间的接合力。
如图1所示，图案化黏胶层120纵向地设置在下重布线层110的第一连接面111上，以及无源元件130和有源元件140纵向地设置在图案化黏胶层120上。无源元件130和有源元件140通过图案化黏胶层120与下重布线层110黏接。具体来说，图案化黏胶层120包含多个黏胶单元，且所述多个黏胶单元排列在下重布线层110的第一连接面111上。无源元件130与其中之一黏胶单元对应设置，以及有源元件140与另一黏胶单元对应设置。通过图案化黏胶层120将无源元件130和有源元件140黏接至下重布线层110。较佳地，图案化黏胶层120可采用芯片贴膜(die attach film，DAF)，图案化黏胶层120可有效地增强无源元件130和有源元件140的稳定性，进而避免无源元件130和有源元件140在后续工艺时发生位移或脱落。应当注意的是，无源元件130和有源元件140彼此横向地相邻，并且两者设置在一相同或大致相同的水平高度上。此外，无源元件130在远离图案化黏胶层120的表面上形成有多个连接垫和设置在多个连接垫上的多个第二导电柱102。相似地，有源元件140在远离图案化黏胶层120的表面上也形成有多个连接垫和设置在多个连接垫上的多个第三导电柱103。第二导电柱102和第三导电柱103可由铜、铝、锡、金、银或上述的组合所构成。
如图1所示，第一绝缘层150纵向地设置在下重布线层110的第一连接面111、无源元件130和有源元件140上。第一绝缘层150将下重布线层110的第一连接面111和设置在其上的元件(第一导电柱101、无源元件130和有源元件140)包封，并仅仅曝露出第一导电柱101、第二导电柱102和第三导电柱103的一对应的表面，以用于与后续形成的元件电连接。
如图1所示，上重布线层160纵向地设置在第一绝缘层150的远离下重布线层110的表面上。上重布线层160包含第一面161和相对第一面161的第二面162。上重布线层160的第一面161形成有多个第一连接垫163，上重布线层160的第二面162形成有多个第二连接垫164和多个第三连接垫165。上重布线层160通过多个第二连接垫164与无源元件130的第二导电柱102电连接，以及上重布线层160通过多个第三连接垫165与有源元件140的第三导电柱103电连接。再者，上重布线层160还包含多个第一导线166和至少一第二导线167。第一导线166和第二导线167皆形成在上重布线层160的内部，其中第一导线166配置为纵向连接其中之一第一连接垫163和其中之一第二连接垫164，以及第二导线167配置为横向连接其中之一第二连接垫164和其中之一第三连接垫165。此外，上重布线层160的内部还设置有至少一第三导线168和一对第四导线169。第三导线168配置为纵向连接其中之一第一连接垫163和其中之一第三连接垫165。第四导线169通过对应的连接垫与第一导电柱101电连接。在本实施例中，透过第二导电柱102和第三导电柱103实现无源元件130和有源元件140与上重布线层160的电连接，可避免因外部施加应力或工艺内含应力，致使低介电系数(low-k)材料与无源元件130和有源元件140的接合界面破裂(cracking)，进而造成导线断裂和可靠度低的问题。
如图1所示，晶粒170纵向地设置在上重布线层160的第一面161上且与上重布线层160电连接。晶粒170包含有源面171和相对有源面171的背面172。晶粒170的有源面171上设置有多个第一凸块173、多个第二凸块174和至少一第三凸块175。第一凸块173、第二凸块174和第三凸块175的材料可以是或可包括铜、金、镍、金属合金等。晶粒170执行倒装芯片接合以将第一凸块173、第二凸块174和第三凸块175接合到上重布线层160，以实现晶粒170与上重布线层160的电连接。具体来说，上重布线层160设置有突出于第一面161的连接件，且所述多个连接件与第一面161上的第一连接垫163对应设置。所述多个连接件亦与晶粒170的所述多个凸块对应设置，并且可通过焊接等技术将连接件与凸块对应连接。在一些实施例中，上重布线层160的连接件亦可被省略，以简化工艺和提高生产效率。
如图1所示，晶粒170通过第一凸块173通过上重布线层160的第四导线169和第一导电柱101与下重布线层110电连接。第一凸块173、第四导线169和第一导电柱101共同形成的路径作为晶粒170的电源路径。又，晶粒170通过第二凸块174通过重布线层160的第一导线166和第二导电柱102与无源元件130电连接。第二凸块174、第一导线166和第二导电柱102共同形成的路径P1作为晶粒170的主要信号传递路径。无源元件130通过第二导电柱102通过上重布线层160的第二导线167和第三导电柱103与有源元件140电连接。第二导电柱102、第二导线167和第三导电柱103共同形成的路径P2作为有源元件140的主要信号传递路径。也就是说，晶粒170与有源元件140之间的主要信号是通过路径P1和路径P2来传递，并且无源元件130作为晶粒170与有源元件140之间的桥接元件。另一方面，晶粒170通过第三凸块175通过上重布线层160的第三导线168和第三导电柱103与有源元件140电连接。第三凸块175、第三导线168和第三导电柱103共同形成的路径P3作为有源元件140的接地或是电源传输路径。应当注意的是，路径P3的数量少于路径P1的数量。
如图1所示，第一凸块173的间距相近于第一导电柱101的间距W1，第二凸块174的间距相近于第二导电柱102的间距W2，以及第三凸块175的间距相近于第三导电柱103的间距W3。对于用于连接不同元件的凸块与导电柱具有不同的间距(pitch)。举例来说，第一导电柱101的间距W1大于第三导电柱103的间距W3，且第三导电柱103的间距W3大于或等于第二导电柱102的间距W2。通过尺寸最大的第一导电柱101和第一凸块173纵向地连接晶粒170、上重布线层160、下重布线层110，可以有效地降低阻抗、缩短电源路径和降低功率衰退(power drop)，进而获得良好的电源完整性能。中间尺寸的第三凸块175和第三导电柱103为有源元件140提供良好的接地线路。较佳地，第二凸块174、第二导电柱102、和上重布线层160的第二连接垫164和第一导线166采用细间距技术来形成。采用细间距技术能使得对应连接的芯片体积缩小和芯片功能增加，以实现在小体积的芯片里容纳更多的I/O端子。在一些实施例中，第二导电柱102的间距W2(细间距)可介于45至50微米之间，或者是小于40微米。
如图1所示，底胶层180设置在上重布线层160和晶粒170之间。具体来说，底胶层180可形成在晶粒170的有源面171和上重布线层160的上表面161之间的间隙中，且横向地覆盖有源面171和上表面161的对应连接件，以增强晶粒170和上重布线层160之间的接合力和增强接合的可靠性。在一些实施例中，底胶层180可被省略，以简化工艺和提高生产效率。
如图1所示，第二绝缘层190纵向地设置在晶粒170和上重布线层160上，配置为封装晶粒170。在本实施例中，第二绝缘层190包含一开口，且晶粒170的背面172通过所述开口曝露在外部。藉此设计，可有效地提高晶粒170的散热性能。
在本实施例中，晶粒170可为系统单芯片(system on a chip，SoC)。无源元件130可为桥接芯片或者是整合有桥接功能的功能芯片。有源元件140可为存储器芯片等，例如非易失性和/或易失性存储器。非易失性存储器可包括只读存储器(read only memory，ROM)、可编程ROM(PROM)、电可编程ROM(EPROM)、电可擦除可编程ROM(EEPROM)或快闪存储器。易失性存储器可包括随机存取存储器(RAM)等。在本申请中，通过无源元件130来实现晶粒170与有源元件140之间的信号传递，使得晶粒170与有源元件140的设置更加弹性和灵活，且不受限于两者仅仅能采用特定的排列方式，如传统的封装结构是将所有的有源元件并行地排列在同一层。举例来说，在本实施例中，通过无源元件130的设置，使得晶粒170与有源元件140可设置在不同的水平高度，并且从一俯视视角观看时，晶粒170与有源元件140可设置为彼此重叠。具体来说，晶粒170与有源元件140分别设置在上重布线层160的相对两面。并且，有源元件140在上重布线层160上的正投影141与晶粒170在上重布线层160上的正投影176部分重叠。在一些实施例中，有源元件140在上重布线层160上的正投影141亦可设计为与晶粒170在上重布线层160上的正投影176重叠，即正投影141在正投影176的范围内。因此，在本申请的扇出型封装结构10中，在符合封装宽度的条件下，通过无源元件130实现了小型化且紧凑设计的多芯片的三维封装，进而为本申请的扇出型封装结构10在高端产品的应用提供更多的设计灵活性和自由度。另一方面，在本实施例中，无源元件130在上重布线层160上的正投影131与晶粒170在上重布线层160上的正投影176重叠，即正投影131在正投影176的范围内。通过无源元件130与晶粒170重叠的设计，可有效地缩短主要信号的传递路径P1。
在本实施例中，大尺寸的第一导电柱101、无源元件130和有源元件140采用内埋(embedded)式技术设置在扇出型封装结构10内部，以最大限度地减少了扇出型封装结构10的外形尺寸，进而保持封装高度要求。内埋式技术的优点包括可提升电性、降低杂信、缩小产品宽度，以及降低成本等。再者，本申请通过上重布线层160的精细布线作为多芯片之间的信号传递路径，可有效地提高信号传递的速度和缩小布线面积，进而确保了多芯片之间的电连接，和实现了高电路密度和细间距的设计。另一方面，在传统的封装结构，为了避免翘曲的问题，需要在与无源元件130和第一导电柱101相同的层中额外设置无功能的晶粒(dummy die)。相较于传统的封装结构，本申请通过将有源元件140设置在与无源元件130和第一导电柱101相同的层中，可有效地减少无功能的晶粒的数量，并进一步减少第一绝缘层150的材料使用量，同时还解决了扇出型封装结构10容易发生翘曲的问题。
参照图2A至图2L，其显示一系列的剖面图，用于阐明图1的扇出型封装结构10的制造流程。
如图2A所示，提供一载板105，并且在载板105上纵向形成分离层106。分离层106配置为将后续形成的膜层从载板105的表面分离。此外，分离层106还可以为载板105和后续形成的膜层之间提供足够的结合力(通过黏合和/或其他结合力)，使得后续的膜层可顺利形成。
如图2B所示，在分离层106远离载板105的表面上依序形成下重布线层110和多个第一导电柱101。下重布线层110和多个第一导电柱101的具体结构参照上述，在此不加以赘述。可选地，下重布线层110可用光刻微影工艺来形成，以及第一导电柱101可采用电镀法来形成。
如图2C所示，在下重布线层110远离分离层106的表面上纵向形成图案化黏胶层120，以及在图案化黏胶层120远离下重布线层110的表面上纵向形成多个无源元件130和多个有源元件140。无源元件130和有源元件140通过图案化黏胶层120与下重布线层110黏接(bonding)。具体来说，图案化黏胶层120包含多个黏胶单元，且所述多个黏胶单元排列在下重布线层110上。每一无源元件130和每一有源元件140与其中之一黏胶单元对应设置。通过图案化黏胶层120将无源元件130和有源元件140黏接至下重布线层110。较佳地，图案化黏胶层120可采用芯片贴膜(die attach film，DAF)，图案化黏胶层120可有效地增强无源元件130和有源元件140的稳定性，进而避免无源元件130和有源元件140在后续工艺时发生位移或脱落。如图2C所示，在无源元件130和有源元件140远离下重布线层110的表面上形成有对应的第二导电柱102和第三导电柱103。无源元件130、有源元件140、第二导电柱102和第三导电柱103的具体结构参照上述，在此不加以赘述。
如图2D所示，在下重布线层110、无源元件130和有源元件140远离下重布线层110的表面上纵向形成第一绝缘层150。在此步骤中，第一绝缘层150完全地覆盖下重布线层110的表面和无源元件130与有源元件140所有表面，以包封无源元件130和有源元件140。在一些实施例中，第一绝缘层150可以包括通过模塑工艺(molding process)所形成的模塑化合物(molding compound)。可选地，第一绝缘层150可以是由例如是环氧树脂或其他适宜树脂等绝缘材料所形成。
如图2E所示，对第一绝缘层150施加一薄化工艺，以减少第一绝缘层150的厚度和曝露出第一导电柱101、无源元件130上的第二导电柱102和有源元件140上的第三导电柱103的一对应的表面，以用于与后续形成的元件电连接。可选地，薄化工艺可通过使用研磨机来实现。
如图2F所示，在第一绝缘层150远离下重布线层110的表面上纵向形成上重布线层160。上重布线层160包含第一面161和相对第一面161的第二面162。上重布线层160的第一面161和第二面162形成有多个连接垫。上重布线层160通过对应的连接垫与无源元件130的第二导电柱102和有源元件140的第三导电柱103电连接。再者，上重布线层160内部形成有多条导线，配置为连接对应的连接垫。上重布线层160的具体结构参照上述，在此不加以赘述。在本实施例中，上重布线层160还形成有突出于第一面161的连接件107，且所述多个连接件107与第一面161上的连接垫对应设置。在一些实施例中，上重布线层160的连接件107亦可被省略，以简化工艺和提高生产效率。可选地，上重布线层160可用光刻微影工艺来形成。
如图2G所示，在上重布线层160的第一面161纵向形成多个晶粒170。晶粒170的有源面上形成有多个凸块。凸块的材料可以是或可包括铜、金、金属合金等。晶粒170采用倒装芯片接合技术以将凸块接合到上重布线层160，以实现晶粒170与上重布线层160的电连接。晶粒170的具体结构参照上述，在此不加以赘述。应当注意的是，在形成晶粒170在上重布线层160上的步骤中，晶粒170设置为与对应的有源元件140部分重叠以及与对应的无源元件130重叠。在本实施例中，在上重布线层160和晶粒170之间还设置有底胶层180。具体来说，底胶层180可形成在晶粒170的有源面和上重布线层160的上表面161之间的间隙中，且横向地覆盖有源面和上表面161的对应连接件，以增强晶粒170和上重布线层160之间的接合力和增强接合的可靠性。在一些实施例中，底胶层180可被省略，以简化工艺和提高生产效率。
如图2H所示，在上重布线层160的第一面161和晶粒170上纵向形成第二绝缘层190。在此步骤中，第二绝缘层190完全地覆盖上重布线层160的第一面161和晶粒170的所有表面，以封装晶粒170。在一些实施例中，第二绝缘层190可以包括通过模塑工艺(moldingprocess)所形成的模塑化合物(molding compound)。可选地，第二绝缘层190可以是由例如是环氧树脂或其他适宜树脂等绝缘材料所形成。
如图2I所示，对第二绝缘层190施加一薄化工艺，以减少第二绝缘层190的厚度和曝露出晶粒170的背面172。也就是说，在本实施例中，第二绝缘层190包含开口，且晶粒170的背面172通过所述开口曝露在外部。藉此设计，可有效地提高晶粒170的散热性能。可选地，薄化工艺可通过使用研磨机来实现。
如图2J所示，通过分离层106将载板105与下重布线层110分离。载板105可对其上方形成的元件提供良好的支撑性，以避免在图2A至图2I对应的步骤中结构发生形变的风险。并且，在图2J对应的步骤中将载板105分离，可有效地减少结构整体的厚度。
如图2K所示，在下重布线层110远离无源元件130和有源元件140的表面纵向形成多个导电端子104。导电端子104可通过使用植球工艺、电镀工艺或其他合适的工艺形成。在一些实施例中，导电端子104是通过植球工艺所形成的焊球，从而降低制造成本并提高制造效率。应当理解的是，根据设计要求，导电端子104可采用其他可能的材料和形状，不局限于此。可选地，通过焊接工艺和回焊工艺以增强导电端子104和下重布线层110的对应电接垫之间的接合力。
如图2L所示，将图2K对应的半成品沿着分离线108断开，以形成多个独立的扇出型封装结构10。可选地，半成品的断开可通过切割机来实现。
应当注意的是，根据图2A至图2L对应的步骤所制造形成的扇出型封装结构10中，晶粒170可为系统单芯片。无源元件130可为桥接芯片或者是整合有桥接功能的功能芯片。有源元件140可为存储器芯片等。通过无源元件130可实现晶粒170与有源元件140之间的信号传递，使得晶粒170与有源元件140的设置更加弹性和灵活，且不受限于两者仅仅能采用特定的排列方式，如传统的并行排列。举例来说，在本实施例中，通过无源元件130的设置，使得晶粒170与有源元件140可设置在不同的水平高度，并且从一俯视视角观看时，晶粒170与有源元件140可设置为彼此重叠。具体来说，晶粒170与有源元件140分别设置在上重布线层160的相对两面。并且，有源元件140在上重布线层160上的正投影与晶粒170在上重布线层160上的正投影部分重叠。在一些实施例中，有源元件140在上重布线层160上的正投影亦可设计为与晶粒170在上重布线层160上的正投影重叠，即有源元件140的正投影在晶粒170的正投影的范围内。因此，在本申请的扇出型封装结构10中，在符合封装宽度的条件下，通过无源元件130实现了小型化且紧凑设计的多芯片的三维封装，进而为本申请的扇出型封装结构10在高端产品的应用提供更多的设计灵活性和自由度。另一方面，在本实施例中，无源元件130在上重布线层160上的正投影与晶粒170在上重布线层160上的正投影重叠。通过无源元件130与晶粒170重叠的设计，可有效地缩短主要信号的传递路径。
参照图3，其显示根据本申请第二实施例的扇出型封装结构20的示意图。第二实施例的扇出型封装结构20与第一实施例的扇出型封装结构10的结构大致相同，两者差别在于，第一实施例的底胶层180在第二实施例中被省略，以简化工艺和提高生产效率。再者，在第二实施例的扇出型封装结构20中，第二绝缘层190形成在晶粒170的有源面和上重布线层160的上表面之间的间隙中，且横向地覆盖晶粒170的有源面和上表面161的对应连接件。因此，通过第二绝缘层190可实现晶粒170和上重布线层160的封装，并增强晶粒170和上重布线层160之间的接合力和增强接合的可靠性。
参照图4，其显示根据本申请第三实施例的扇出型封装结构30的示意图。第三实施例的扇出型封装结构30与第一实施例的扇出型封装结构10的结构大致相同，两者差别在于，第一实施例的第二绝缘层190在第三实施例中被省略，以简化工艺和提高生产效率。再者，在第三实施例的扇出型封装结构30中，通过底胶层180可实现晶粒170和上重布线层160的封装，并增强晶粒170和上重布线层160之间的接合力和增强接合的可靠性。在本实施例中，晶粒170的背面可暴露在外部，确保晶粒170具有良好的散热性能。
参照图5，其显示根据本申请第四实施例的扇出型封装结构40的示意图。第四实施例的扇出型封装结构40与第一实施例的扇出型封装结构10的结构大致相同，两者差别在于，第一实施例的第二绝缘层190在第四实施例中被省略，以简化工艺和提高生产效率。并且，第四实施例的扇出型封装结构40还包含保护盖191。保护盖191较佳地以金属材料制成。保护盖191纵向地覆盖住上重布线层160和晶粒170，以增强扇出型封装结构40的稳定性，避免翘曲变形。
参照图6，其显示根据本申请第五实施例的扇出型封装结构50的示意图。第五实施例的扇出型封装结构50与第一实施例的扇出型封装结构10的结构大致相同，两者差别在于，第一实施例的第二绝缘层190在第四实施例中被省略，以简化工艺和提高生产效率。并且，第五实施例的扇出型封装结构50还包含保护环192。保护环192较佳地以金属材料制成。保护环192纵向地设置在上重布线层160的第一面上且环绕晶粒170。可选地，保护环192沿着上重布线层160的第一面的外周缘设置，以增强扇出型封装结构40的稳定性，避免翘曲变形。另一方面，通过保护环192的设计，使得晶粒170的背面可暴露在外部，确保晶粒170具有良好的散热性能。
综上所述，在本申请的扇出型封装结构及其制造方法中，无源元件130可为桥接芯片或者是整合有桥接功能的功能芯片。通过无源元件130可实现晶粒170与有源元件140之间的信号传递，使得晶粒170与有源元件140的设置更加弹性和灵活，且不受限于两者仅仅能采用特定的排列方式，如传统的并行排列。举例来说，通过无源元件130的设置，使得晶粒170与有源元件140可设置在不同的水平高度，并且从一俯视视角观看时，晶粒170与有源元件140可设置为彼此重叠。因此，在本申请的扇出型封装结构中，在符合封装宽度的条件下，通过无源元件130实现了小型化且紧凑设计的多芯片的三维封装。也就是说，在不增加封装尺寸的前提下实现多个元件之间的电连接，进而为本申请的扇出型封装结构在高端产品的应用提供更多的设计灵活性和自由度。
以上所述仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何所属技术领域通常知识者在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (10)

1.一种扇出型封装结构，其特征在于，所述扇出型封装结构包括：
上重布线层，包含第一面和相对所述第一面的第二面；
晶粒设置在所述上重布线层的所述第一面上且与所述上重布线层电连接；
无源元件，设置在所述上重布线层的所述第二面上且与所述上重布线层电连接；以及
有源元件，设置在所述上重布线层的所述第二面上且与所述上重布线层电连接，其中所述有源元件与所述无源元件横向相邻，以及所述晶粒通过所述上重布线层与所述有源元件和所述无源元件电连接。
2.如权利要求1所述的扇出型封装结构，其特征在于，所述有源元件在所述上重布线层上的正投影与所述晶粒在所述上重布线层上的正投影部分重叠，以及所述无源元件在所述上重布线层上的正投影与所述晶粒在所述上重布线层上的所述正投影重叠。
3.如权利要求1所述的扇出型封装结构，其特征在于，所述上重布线层包含：
第一连接垫，形成在所述第一面，配置为与所述晶粒连接；
多个第二连接垫，形成在所述第二面，配置为与所述无源元件连接；
第三连接垫，形成在所述第二面，配置为与所述有源元件连接；
第一导线，形成在所述上重布线层内，配置为纵向连接所述第一连接垫和所述多个第二连接垫的其中之一；
第二导线，形成在所述上重布线层内，配置为横向连接所述多个第二连接垫的其中之一和所述第三连接垫。
4.如权利要求1所述的扇出型封装结构，其特征在于，所述扇出型封装结构还包含：
第一绝缘层，设置所述上重布线层的所述第二面上，配置为封装所述无源元件和所述有源元件；以及
第二绝缘层，设置在所述晶粒和所述上重布线层上，配置为封装所述晶粒，其中所述第二绝缘层包含开口，且所述晶粒的表面通过所述开口曝露在外部。
5.如权利要求1所述的扇出型封装结构，其特征在于，所述扇出型封装结构还包含：
下重布线层；以及
图案化黏胶层，设置在所述下重布线层上，其中所述无源元件和所述有源元件的表面通过所述图案化黏胶层与所述下重布线层黏接，以及所述无源元件和所述有源元件的另一表面与所述上重布线层电连接。
6.如权利要求5所述的扇出型封装结构，其特征在于，所述扇出型封装结构还包含：
第一导电柱，连接所述上重布线层和所述下重布线层；
第二导电柱，连接所述无源元件和所述上重布线层；以及
第三导电柱，连接所述有源元件和所述上重布线层，其中所述第一导电柱的间距大于或等于所述第三导电柱的间距，且所述第三导电柱的所述间距大于或等于所述第二导电柱的间距。
7.如权利要求1所述的扇出型封装结构，其特征在于，所述扇出型封装结构还包含底胶层，设置在所述上重布线层和所述晶粒之间。
8.如权利要求1所述的扇出型封装结构，其特征在于，所述扇出型封装结构还包含保护环或保护盖，设置在所述上重布线层的所述第一面上且环绕所述晶粒。
9.一种扇出型封装结构的制造方法，其特征在于，所述扇出型封装结构的制造方法包含：
提供下重布线层；
形成无源元件和有源元件在所述下重布线层上；
形成一上重布线层在所述无源元件和所述有源元件上，其中所述无源元件和所述有源元件与所述上重布线层电连接，且所述无源元件和所述有源元件横向地相邻；以及
形成晶粒在所述上重布线层上，其中所述晶粒通过所述上重布线层与所述无源元件和所述有源元件电连接。
10.如权利要求9所述的扇出型封装结构的制造方法，其特征在于，在形成所述晶粒在所述上重布线层上的步骤中，所述晶粒设置为与所述有源元件部分重叠以及与所述无源元件重叠。
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